MPC941FA

MOTOROLA Freescale Semiconductor, Inc. SEMICONDUCTOR TECHNICAL DATA MPC941 Freescale Semiconductor, Inc... Low Voltage 1:27 Clock Distribution Chip The MPC941 is a 1:27 low voltage clock distribution chip. The device features the capability to select either a differential LVPECL or an LVCMOS compatible input. The 27 outputs are LVCMOS compatible and feature the drive strength to drive 50Ω series or parallel terminated transmission lines. With output–to–output skews of 250ps, the MPC941 is ideal as a clock distribution chip for the most demanding of synchronous systems. For a similar product with a smaller number of outputs, please consult the MPC940 data sheet. • • • • • • • Order this document by MPC941/D LOW VOLTAGE 3.3V/2.5V 1:27 CLOCK DISTRIBUTION CHIP LVPECL or LVCMOS Clock Input 250ps Maximum Output–to–Output Skew Drives Up to 54 Independent Clock Lines Maximum Output Frequency of 250MHz High Impedance Output Enable 48–Lead LQFP Packaging 3.3V or 2.5V VCC Supply Voltage FA SUFFIX 48–LEAD LQFP PACKAGE CASE 932–02 With a low output impedance, in both the HIGH and LOW logic states, the output buffers of the MPC941 are ideal for driving series terminated transmission lines. More specifically, each of the 27 MPC941 outputs can drive two series terminated 50Ω transmission lines. With this capability, the MPC941 has an effective fanout of 1:54. With this level of fanout, the MPC941 provides enough copies of low skew clocks for most high performance synchronous systems. The differential LVPECL inputs of the MPC941 allow the device to interface directly with an LVPECL fanout buffer like the MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS input provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In addition, the two clock sources can be used as a test clock interface as well as the primary system clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the LVCMOS level clock input. The MPC941 is fully 3.3V and 2.5V compatible. The 48–lead LQFP package was chosen to optimize performance, board space and cost of the device. The 48–lead LQFP has a 7x7mm body size. 02/01  Motorola, Inc. 2001 For More Information On This Product, REV 4 1 Go to: www.freescale.com Freescale Semiconductor, Inc. MPC941 LOGIC DIAGRAM PECL_CLK pulldown 0 PECL_CLK Q0 1 LVCMOS_CLK pulldown LVCMOS_CLK_Sel 25 Q1–Q25 pulldown Q26 OE pulldown GND Q8 Q9 Q10 VCC Q11 Q12 GND Q13 Q14 Q15 VCC 36 35 34 33 32 31 30 29 28 27 26 25 VCC 37 24 GND Q7 38 23 Q16 Q6 39 22 Q17 Q5 40 21 Q18 GND 41 20 VCC Q4 42 19 Q19 Q3 43 18 Q20 VCC 44 17 GND Q2 45 16 Q21 Q1 46 15 Q22 Q0 47 14 Q23 GND 48 13 VCC 3 4 5 6 7 8 9 10 LVCMOS_CLK LVCMOS_CLKSEL VCC PECL_CLK PECL_CLK VCC Q26 Q25 11 12 Q24 2 GND 1 OE MPC941 GND Freescale Semiconductor, Inc... Pinout: 48–Lead QFP (Top View) FUNCTION TABLE LVCMOS_CLK_Sel 0 1 Input PECL_CLK LVCMOS_CLK Table 1: PIN CONFIGURATIONS Pin I/O PECL_CLK, PECL_CLK Input LVPECL LVPECL differential reference clock inputs LVCMOS_CLK Input LVCMOS Alternative reference clock input LVCMOS_CLK_Sel Input LVCMOS Input reference clock select OE Input LVCMOS Output tristate control GND Supply Negative voltage supply output bank (GND) VCC Supply Positive voltage supply LVCMOS Clock outputs Q0 - Q26 MOTOROLA Output Type Function For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC941 Table 2: ABSOLUTE MAXIMUM RATINGS* Symbol VCC VIN Min Max Unit Supply Voltage Characteristics -0.3 3.6 V VCC+0.3 VCC+0.3 V DC Input Voltage -0.3 VOUT IIN DC Output Voltage -0.3 DC Input Current ±20 mA IOUT TS DC Output Current ±50 mA 125 °C Storage temperature -40 V * Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Table 3: DC CHARACTERISTICS (VCC = 3.3V Freescale Semiconductor, Inc... Symbol ± 5%, TA = –40 to +85°C) Characteristics Min VIH VIL Input high voltage LVCMOS_CLK 2.0 Input low voltage LVCMOS_CLK -0.3 IIN VPP Input current Peak-to-peak input voltage PECL_CLK, PECL_CLK 500 Common Mode Range PECL_CLK, PECL_CLK 1.2 VCMR VOH VOL Output High Voltage IOZ ZOUT CPD Output tristate leakage current CIN ICCQ VTT Typ Max Unit VCC + 0.3 0.8 ±120a V LVCMOS V LVCMOS VCC-0.8 2.4 Output Low Voltage Output impedance Power Dissipation Capacitance 7-8 Input capacitance 4.0 LVPECL V LVPECL V IOH=-24 mAb IOL= 24mA b IOL=12mA V V 100 µA 10 pF W Per Output pF Maximum Quiescent Supply Current 5 VCC÷2 Output termination voltage µA mV 0.55 0.40 14 - 17 Condition mA All VCC Pins V a. Input pull-up / pull-down resistors influence input current. b. The MPC941 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. Table 4: AC CHARACTERISTICS (VCC = 3.3V Symbol Characteristics fMAX tr, tf Maximum Output Frequency tPLH tPHL Propagation delay tPLZ, HZ tPZL, LZ ± 5%, TA = –40 to +85°C)a Typ 0 LVCMOS_CLK Input Rise/Fall Time PECL_CLK to any Q LVCMOS_CLK to any Q 1.2 0.9 1.8 1.5 Max Unit 250b 1.0c MHz 2.6 2.3 ns ns Output Disable Time ns Condition 0.8 to 2.0V ns Output Enable Time ns tsk(O) Output-to-output Skew PECL_CLK to any Q LVCMOS_CLK to any Q tsk(PP) tsk(PP) DCQ Min 250 250 ps Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q 1000 1000 ps ps For a given TA and VCC, any Q Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q 1400 1400 ps ps For any TA, VCC and Q 60 55 % % DCREF = 50% DCREF = 50% Output Duty Cycle PECL_CLK to any Q LVCMOS_CLK to any Q 125 125 45 45 50 50 tr, tf Output Rise/Fall Time 0.2 1.0 ns 0.55 to 2.4V a. AC characteristics apply for parallel output termination of 50Ω to VTT. b. AC characteristics are guaranteed up to fmax. Please refer to applications section for information on power consumption versus operating frequency and thermal management. c. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal transition times smaller than 3 ns can be applied to the MPC941. TIMING SOLUTIONS DL207 — Rev 0 For More Information On This Product, 3 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC941 Table 5: DC CHARACTERISTICS (VCC = 2.5V Symbol Characteristics Min Typ Max Unit Condition VIH Input high voltage LVCMOS_CLK 1.7 VCC + 0.3 V LVCMOS VIL Input low voltage LVCMOS_CLK -0.3 0.7 V LVCMOS IIN VPP VCMR Freescale Semiconductor, Inc... ± 5%, TA = –40 to +85°C) ±120a Input current Peak-to-peak input voltage PECL_CLK, PECL_CLK 500 Common Mode Range PECL_CLK, PECL_CLK 1.1 VCC-0.7 LVPECL V LVPECL V IOH=-15 mAb IOL= 15 mAb VOH Output High Voltage VOL Output Low Voltage 0.6 V IOZ Output tristate leakage current 100 µA 10 pF 5 mA ZOUT 1.8 µA mV Output impedance Power Dissipation Capacitance 7–8 CIN Input capacitance 4.0 ICCQ W 18 – 20 CPD Maximum Quiescent Supply Current Per Output pF All VCC Pins VTT Output termination voltage VCC÷2 V a. Input pull-up / pull-down resistors influence input current. b. The MPC941 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. Table 6: AC CHARACTERISTICS (VCC = 2.5V Symbol fMAX ± 5%, TA = –40 to +85°C)a Characteristics Maximum Output Frequency tr, tf LVCMOS_CLK Input Rise/Fall Time tPLH tPHL Propagation delay PECL_CLK to any Q LVCMOS_CLK to any Q Min Typ 0 1.3 1.0 2.1 1.8 Max Unit 250b MHz 1.0c ns 2.9 2.6 ns ns tPLZ, HZ Output Disable Time ns tPZL, LZ Output Enable Time ns tsk(O) Output-to-output Skew PECL_CLK to any Q LVCMOS_CLK to any Q tsk(PP) tsk(PP) DCQ 0.7 to 1.7V 250 250 ps Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q 1200 1200 ps ps For a given TA and VCC, any Q Device-to-device Skew PECL_CLK to any Q LVCMOS_CLK to any Q 1600 1600 ps ps For any TA, VCC and Q 60 55 % % DCREF = 50% DCREF = 50% Output Duty Cycle PECL_CLK to any Q LVCMOS_CLK to any Q 125 125 Condition 45 45 50 50 tr, tf Output Rise/Fall Time 0.2 1.0 ns 0.6 to 1.6V a. AC characteristics apply for parallel output termination of 50Ω to VTT. b. AC characteristics are guaranteed up to fmax. Please refer to the applications section for information on power consumption versus operating frequency and thermal management. c. Fast input signal transition times are required to maintain part-to-part skew specification. If part-to-part skew is not critical to the application, signal transition times smaller than 3 ns can be applied to the MPC941. MOTOROLA For More Information On This Product, 4 Go to: www.freescale.com TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC941 APPLICATIONS INFORMATION Freescale Semiconductor, Inc... The MPC941 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to application note AN1091 in the Timing Solutions data book (DL207/D). In most high performance clock networks point–to–point distribution of signals is the method of choice. In a point–to–point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC941 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 1 “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line vs two series terminated lines in parallel. When taken to its extreme the fanout of the MPC941 clock driver is effectively doubled due to its capability to drive multiple lines. MPC941 OUTPUT BUFFER IN 14Ω MPC941 OUTPUT BUFFER IN VL = VS ( Zo / (Rs + Ro +Zo)) Zo = 50Ω || 50Ω Rs = 36Ω || 36Ω Ro = 14Ω VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.5V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). 3.0 2.5 OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 0.5 RS = 36Ω ZO = 50Ω 0 OutA 2 4 6 8 TIME (nS) 10 12 14 Figure 2. Single versus Dual Waveforms RS = 36Ω ZO = 50Ω OutB0 14Ω RS = 36Ω ZO = 50Ω OutB1 Figure 1. Single versus Dual Transmission Lines The waveform plots of Figure 2 “Single versus Dual Waveforms” show the simulation results of an output driving a single line vs two lines. In both cases the drive capability of the MPC941 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output–to–output skew of the MPC941. The output waveform in Figure 2 shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not TIMING SOLUTIONS DL207 — Rev 0 match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VOLTAGE (V) Driving Transmission Lines Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 3 “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC941 OUTPUT BUFFER RS = 22Ω ZO = 50Ω RS = 22Ω ZO = 50Ω 14Ω 14Ω + 22Ω k 22Ω = 50Ω k 50Ω 25Ω = 25Ω Figure 3. Optimized Dual Line Termination For More Information On This Product, 5 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC941 Freescale Semiconductor, Inc... Power Consumption of the MPC941 and Thermal Management In equation 2, P stands for the number of outputs with a parallel or thevenin termination, VOL, IOL, VOH and IOH are a function of the output termination technique and DCQ is the clock signal duty cyle. If transmission lines are used ΣCL is zero in equation 2 and can be eliminated. In general, the use of controlled transmission line techniques eliminates the impact of the lumped capacitive loads at the end lines and greatly reduces the power dissipation of the device. Equation 3 describes the die junction temperature TJ as a function of the power consumption. The MPC941 AC specification is guaranteed for the entire operating frequency range up to 250 MHz. The MPC941 power consumption and the associated long-term reliability may decrease the maximum frequency limit, depending on operating conditions such as clock frequency, supply voltage, output loading, ambient temperture, vertical convection and thermal conductivity of package and board. This section describes the impact of these parameters on the junction temperature and gives a guideline to estimate the MPC941 die junction temperature and the associated device reliability. For a complete analysis of power consumption as a function of operating conditions and associated long term device reliability please refer to the application note AN1545. According the AN1545, the long-term device reliability is a function of the die junction temperature: Where Rthja is the thermal impedance of the package (junction to ambient) and TA is the ambient temperature. According to Table 7, the junction temperature can be used to estimate the long-term device reliability. Further, combining equation 1 and equation 2 results in a maximum operating frequency for the MPC941 in a series terminated transmission line system. TJ,MAX should be selected according to the MTBF system requirements and Table 7. Rthja can be derived from Table 8. The Rthja represent data based on 1S2P boards, using 2S2P boards will result in a lower thermal impedance than indicated below. Table 7: Die junction temperature and MTBF Junction temperature (°C) MTBF (Years) 100 20.4 110 9.1 120 4.2 130 2.0 Table 8: Thermal package impedance of the 48ld LQFP Convection, LFPM Rthja (1P2S board), K/W Increased power consumption will increase the die junction temperature and impact the device reliability (MTBF). According to the system-defined tolerable MTBF, the die junction temperature of the MPC941 needs to be controlled and the thermal impedance of the board/package should be optimized. The power dissipated in the MPC941 is represented in equation 1. Where ICCQ is the static current consumption of the MPC941, CPD is the power dissipation capacitance per output, (Μ)ΣCL represents the external capacitive output load, N is the number of active outputs (N is always 27 in case of the MPC941). The MPC941 supports driving transmission lines to maintain high signal integrity and tight timing parameters. Any transmission line will hide the lumped capacitive load at the end of the board trace, therefore, ΣCL is zero for controlled transmission line systems and can be eliminated from equation 1. Using parallel termination output termination results in equation 2 for power dissipation. P TOT +V @ CC ƪ P TOT I CCQ + ƪ )V @f CC I CCQ CLOCK )V @f ǒ CC @ N@C TJ f CLOCK,MAX MOTOROLA ȍ )ȍ ) ȍƪ PD CL M Ǔƫ +T )P @R A + C @ N1 @ V @ PD ǒ 2 CC ƪ TOT PD CL M DC Q P Ǔƫ 68 200 lfpm 59 300 lfpm 56 400 lfpm 54 500 lfpm 53 @V OH * * ǒI @ V CCQ Equation 1 CC @ I @ ǒV * V Ǔ ) ǒ1 * DC Ǔ @ I @ V thja T J,MAX T A R thja 78 If the calculated maximum frequency is below 250 MHz, it becomes the upper clock speed limit for the given application conditions. The following eight derating charts describe the safe frequency operation range for the MPC941. The charts were calculated for a maximum tolerable die junction temperature of 110°C (120°C), corresponding to a estimated MTBF of 9.1 years (4 years), a supply voltage of either 3.3V or 2.5V and series terminated transmission line or capacitive loading. Depending on a given set of these operating conditions and the available device convection a decision on the maximum operating frequency can be made. @ N@C ) CLOCK Still air 100 lfpm CC CC OH ƫ Ǔ For More Information On This Product, 6 Go to: www.freescale.com Q OL OL ƫ Equation 2 Equation 3 Equation 4 TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC941 300 300 fMAX (AC) 250 OPERATING FREQUENCY (MHz) OPERATING FREQUENCY (MHz) TA = 55°C TA = 65°C 200 TA = 75°C 150 TA = 85°C 100 Safe operation 50 0 400 300 200 IFPM, CONVECTION 100 250 fMAX (AC) TA = 55°C 200 TA = 65°C 150 TA = 75°C 100 TA = 85°C Safe operation 50 0 0 Figure 4. Maximum MPC941 frequency, VCC = 3.3V, MTBF 9.1 years, driving series terminated transmission lines 500 400 300 200 IFPM, CONVECTION 100 0 Figure 5. Maximum MPC941 frequency, VCC = 3.3V, MTBF 9.1 years, 4 pF load per line 300 300 TA = 65°C fMAX (AC) 250 OPERATING FREQUENCY (MHz) OPERATING FREQUENCY (MHz) Freescale Semiconductor, Inc... 500 TA = 35°C TA = 45°C TA = 75°C 200 TA = 85°C 150 100 Safe operation 50 0 500 400 300 200 IFPM, CONVECTION 100 0 Figure 6. Maximum MPC941 frequency, VCC = 3.3V, MTBF 4 years, driving series terminated transmission lines TIMING SOLUTIONS DL207 — Rev 0 TA = 45°C TA = 55°C 250 fMAX (AC) TA = 65°C 200 150 TA = 75°C TA = 85°C 100 Safe operation 50 0 500 400 300 200 IFPM, CONVECTION 100 0 Figure 7. Maximum MPC941 frequency, VCC = 3.3V, MTBF 4 years, 4 pF load per line For More Information On This Product, 7 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC941 300 TA = 65°C TA = 75°C OPERATING FREQUENCY (MHz) OPERATING FREQUENCY (MHz) 300 fMAX (AC) 250 TA = 85°C 200 150 100 Safe operation 50 0 400 300 200 IFPM, CONVECTION 100 0 TA = 85°C 150 100 Safe operation 50 500 Figure 8. Maximum MPC941 frequency, VCC = 2.5V, MTBF 9.1 years, driving series terminated transmission lines 400 300 200 IFPM, CONVECTION 100 0 Figure 9. Maximum MPC941 frequency, VCC = 2.5V, MTBF 9.1 years, 4 pF load per line 300 300 250 OPERATING FREQUENCY (MHz) OPERATING FREQUENCY (MHz) TA = 75°C 200 0 500 Freescale Semiconductor, Inc... fMAX (AC) 250 TA = 85°C fMAX (AC) 200 150 100 Safe operation 50 250 TA = 75°C fMAX (AC) TA = 85°C 200 150 100 Safe operation 50 0 0 500 400 300 200 IFPM, CONVECTION 100 0 Figure 10. Maximum MPC941 frequency, VCC = 2.5V, MTBF 4 years, driving series terminated transmission lines MOTOROLA 500 400 300 200 IFPM, CONVECTION 100 0 Figure 11. Maximum MPC941 frequency, VCC = 2.5V, MTBF 4 years, 4 pF load per line For More Information On This Product, 8 Go to: www.freescale.com TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC941 DUT MPC941 Pulse Generator Z = 50 ZO = 50Ω ZO = 50Ω W RT = 50Ω RT = 50Ω VTT VTT Figure 12. LVCMOS_CLK MPC941 AC test reference for Vcc = 3.3V and Vcc = 2.5V DUT MPC941 ZO = 50Ω Differential Pulse Generator Z = 50 ZO = 50Ω Freescale Semiconductor, Inc... W RT = 50Ω RT = 50Ω VTT VTT Figure 13. PECL_CLK MPC941 AC test reference for Vcc = 3.3V and Vcc = 2.5V PECL_CLK VCC VCC 2 B LVCMOS_CLK VCMR VPP PECL_CLK GND VCC VCC 2 B Q VCC VCC 2 B Q GND GND tPD tPD Figure 14. LVPECL Propagation delay (tPD) test reference Figure 15. LVCMOS Propagation delay (tPD) test reference VCC VCC 2 VCC VCC 2 GND GND B B tP VOH VCC 2 B T0 GND DC = tP /T0 x 100% tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage The pin–to–pin skew is defined as the worst case difference in propagation delay between any two similar delay paths within a single device Figure 16. Output Duty Cycle (DC) tF Figure 17. Output–to–output Skew tSK(O) VCC=3.3V 2.4 VCC=2.5V 1.8V VCC=3.3V 2.0 VCC=2.5V 1.7V 0.55 0.6V 0.8 0.7V tR Figure 18. Output Transition Time Test Reference TIMING SOLUTIONS DL207 — Rev 0 tF tR Figure 19. Input Transition Time Test Reference For More Information On This Product, 9 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC941 OUTLINE DIMENSIONS FA SUFFIX PLASTIC QFP PACKAGE CASE 932–02 ISSUE E 4X 0.200 AB T–U Z DETAIL Y A P A1 37 1 36 T U V B AE B1 12 25 13 AE V1 24 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA Z S1 T, U, Z S DETAIL Y 4X 0.200 AC T–U Z 0.080 AC G AB AD AC ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 1_ 5_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF M_ BASE METAL TOP & BOTTOM N R J 0.250 Freescale Semiconductor, Inc... 48 C E GAUGE PLANE 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL. F D 0.080 M AC T–U Z SECTION AE–AE W H L_ K DETAIL AD AA MOTOROLA For More Information On This Product, 10 Go to: www.freescale.com TIMING SOLUTIONS DL207 — Rev 0 Freescale Semiconductor, Inc. MPC941 Freescale Semiconductor, Inc... NOTES TIMING SOLUTIONS DL207 — Rev 0 For More Information On This Product, 11 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... MPC941 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. 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