MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3.3V/2.5V LVCMOS 1:12 Clock
Fanout Buffer
The MPC9448 is a 3.3V or 2.5V compatible, 1:12 clock fanout buffer
targeted for high performance clock tree applications. With output
frequencies up to 350 MHz and output skews less than 150 ps, the device
meets the needs of most demanding clock applications.
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12 LVCMOS compatible clock outputs
Selectable LVCMOS and differential LVPECL compatible clock inputs
Order Number: MPC9448/D
Rev 3, 04/2003
MPC9448
LOW VOLTAGE
3.3V/2.5V LVCMOS 1:12
CLOCK FANOUT BUFFER
Maximum clock frequency of 350 MHz
Maximum clock skew of 150 ps
Synchronous output stop in logic low state eliminates output runt pulses
High–impedance output control
3.3V or 2.5V power supply
Drives up to 24 series terminated clock lines
Ambient temperature range –40°C to +85°C
32–Lead LQFP packaging
Supports clock distribution in networking, telecommunication and
computing applications
• Pin and function compatible to MPC948
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A
Functional Description
The MPC9448 is specifically designed to distribute LVCMOS
compatible clock signals up to a frequency of 350 MHz. Each output
provides a precise copy of the input signal with a near zero skew. The
outputs buffers support driving of 50Ω terminated transmission lines on
the incident edge: each output is capable of driving either one parallel
terminated or two series terminated transmission lines.
Two selectable, independent clock inputs are available, providing support of LVCMOS and differential LVPECL clock
distribution systems. The MPC9448 CLK_STOP control is synchronous to the falling edge of the input clock. It allows the start
and stop of the output clock signal only in a logic low state, thus eliminating potential output runt pulses. Applying the OE control
will force the outputs into high–impedance mode.
All inputs have an internal pull–up or pull–down resistor preventing unused and open inputs from floating. The device supports
a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9448 is pin and function compatible
but performance–enhanced to the MPC948.
Motorola, Inc. 2003
1
MPC9448
Q6
VCC
Q7
CLK
STOP
GND
1
Q5
CCLK
VCC
0
Q4
Q1
PCLK
PCLK
GND
Q0
VCC
24
23
22
21
20
19
18
17
16
Q2
VCC
Q3
Q3
25
Q4
VCC
26
15
Q8
Q2
27
14
VCC
13
Q9
GND
Q5
CLK_SEL
VCC
CLK_STOP
SYNC
GND
28
Q6
Q1
29
12
GND
Q7
VCC
30
11
Q10
Q0
31
10
VCC
9
Q11
MPC9448
4
5
6
CLK_STOP
OE
7
8
GND
3
VCC
2
PCLK
32
1
PCLK
GND
CCLK
Q8
Q10
VCC
Q11
W
CLK_SEL
Q9
(all input resistors have a value of 25k )
OE
Figure 1. Logic Diagram
Figure 2. 32–Lead Package Pinout
(Top View)
Table 1. FUNCTION TABLE
Control
CLK_SEL
Default
0
1
1
PECL differential input selected
CCLK input selected
OE
1
Outputs disabled (high-impedance state)1
Outputs enabled
CLK_STOP
1
Outputs synchronously stopped in logic low state
Outputs active
1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.
Table 2. PIN CONFIGURATION
Pin
I/O
Type
Function
PCLK, PCLK
Input
LVPECL
Clock signal input
CCLK
Input
LVCMOS
Alternative clock signal input
CLK_SEL
Input
LVCMOS
Clock input select
CLK_STOP
Input
LVCMOS
Clock output enable/disable
OE
Input
LVCMOS
Output enable/disable (high–impedance tristate)
Q0–11
Output
LVCMOS
Clock outputs
GND
Supply
Ground
Negative power supply (GND)
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to
the positive power supply for correct operation
MOTOROLA
2
TIMING SOLUTIONS
MPC9448
Table 3. ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
Max
Unit
VCC
Supply Voltage
–0.3
3.9
V
VIN
DC Input Voltage
–0.3
VCC + 0.3
V
VOUT
DC Output Voltage
–0.3
VCC + 0.3
V
IIN
DC Input Current
±20
mA
IOUT
DC Output Current
±50
mA
TStor
Storage Temperature Range
–65
125
°C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
Table 4. GENERAL SPECIFICATIONS
Symbol
Characteristic
Min
Typ
Max
2
Unit
Condition
VTT
Output Termination Voltage
MM
ESD Protection (Machine Model)
200
V
HBM
ESD Protection (Human Body Model)
2000
V
LU
Latch–up Immunity
200
mA
CPD
Power Dissipation Capacitance
10
pF
Per Output
CIN
Input Capacitance
4.0
pF
Inputs
VCC
V
Table 5. DC CHARACTERISTICS (VCC = 3.3V ±5%, TA = –40°C to +85°C)
Symbol
Characteristic
Min
Max
Unit
2.0
VCC + 0.3
V
LVCMOS
–0.3
0.8
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
VPP
Peak–to–Peak Input Voltage
PCLK
250
VCMRa
Common Mode Range
PCLK
1.1
IIN
Input Currentb
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
ZOUT
ICCQd
Output Impedance
Typ
V
LVCMOS
mV
LVPECL
VCC – 0.6
V
LVPECL
300
µA
V
VIN = VCC or GND
IOH = –24mAc
V
V
IOL = 24mAc
IOL = 12mA
2.4
0.55
0.30
17
Condition
Ω
Maximum Quiescent Supply Current
2.0
mA
All VCC Pins
a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (DC) specification.
b. Input pull-up / pull-down resistors influence input current.
c. The MPC9448 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for
VCC=3.3V) or one 50Ω series terminated transmission line (for VCC=2.5V).
d. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
TIMING SOLUTIONS
3
MOTOROLA
MPC9448
Table 6. AC CHARACTERISTICS (VCC = 3.3V ±5%, TA = –40°C to +85°C)a
Symbol
Characteristics
fref
fMAX
VPP
VCMRb
tP, REF
Max
Unit
Input Frequency
Min
0
350
MHz
Maximum Output Frequency
0
350
MHz
PCLK
400
1000
mV
LVPECL
Common Mode Range
PCLK
1.3
VCC-0.8
V
LVPECL
1.4
ns
CCLK Input Rise/Fall Time
PCLK to any Q
CCLK to any Q
1.6
1.3
1.0c
ns
3.6
3.3
ns
ns
tPLH/HL
tPLH/HL
tPLZ, HZ
Propagation delay
Output Disable Time
11
ns
tPZL, LZ
Output Enable Time
11
ns
tS
Setup time
CCLK to CLK_STOP
PCLK to CLK_STOP
0.0
0.0
ns
ns
tH
Hold time
CCLK to CLK_STOP
PCLK to CLK_STOP
1.0
1.5
ns
ns
tsk(O)
tsk(PP)
tSK(P)
Condition
Peak-to-peak input voltage
Reference Input Pulse Width
tr, tf
Typ
Output-to-output Skew
Device-to-device Skew
Output pulse skewd
150
ps
PCLK or CCLK to any Q
2.0
ns
Using CCLK
Using PCLK
300
400
ps
ps
0.8 to 2.0V
DCQ
a.
b.
c.
d.
Output Duty Cycle
fQ
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