MPC9449AC

MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications. Features • 15 LVCMOS compatible clock outputs • Two selectable LVCMOS and one differential LVPECL compatible clock • • • • • • • • • Order Number: MPC9449/D Rev 1, 08/2002 MPC9449 3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER inputs Selectable output frequency divider (divide-by-one and divide-by-two) Maximum clock frequency of 200 MHz Maximum clock skew of 200 ps High-impedance output control 3.3V or 2.5V power supply Drives up to 30 series terminated clock lines Ambient temperature range –40°C to +85°C 52 lead LQFP packaging Supports clock distribution in networking, telecommunication and FA SUFFIX computing applications 52 LEAD LQFP PACKAGE CASE 848D • Pin and function compatible to MPC949 Functional Description The MPC9449 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in 4 output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of 50Ω terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of –40°C to +85°C. The MPC9449 is pin and function compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.  Motorola, Inc. 2002 1 MPC9449 DSELA 0 QA0 1 QA1 VCC VCC NC QD5 GND GND QC3 VCC QB1 QC2 1 GND ÷2 1 CCLK_SEL QC1 0 VCC ÷1 QC0 QB0 0 GND QB2 39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 NC VCC 41 25 VCC QB2 42 24 QD4 GND 43 23 GND QB1 44 22 QD3 VCC 45 21 VCC 20 QD2 QC0 NC 0 QC1 1 QC2 QD1 0 QD2 1 QD3 DSELD QD4 MPC9449 QB0 GND 47 19 GND GND 48 18 QD1 QA1 49 17 VCC VCC 50 16 QD0 QA0 51 15 GND GND 52 14 NC 1 2 3 4 5 6 7 8 PCLK_SEL QD0 DSELC 46 PCLK DSELB PCLK QC3 CCLK1 PCLK_SEL VCC PCLK PCLK CCLK0 1 NC CCLK1 MR/OE 0 CCLK_SEL CCLK0 9 10 11 12 13 Figure 1. MPC9449 Logic Diagram GND DSELD DSELC DSELB MR/OE DSELA QD5 Figure 2. MPC9449 52–Lead Package Pinout (Top View) Table 1: FUNCTION TABLE Control Default 0 1 PCLK_SEL 0 LVCMOS clock input selected (CCLK0 or CCLK1) PCLK differential input selected CCLK_SEL 0 CCLK0 selected CCLK1 selected 00 00 ÷1 ÷2 1 Outputs enabled Outputs disabled (high impedance) DSELA, DSELB, DSELC, DSELD MR/OE Table 2: PIN CONFIGURATION Pin I/O Type Function PCLK, PCLK Input LVPECL Differential LVPECL clock input CCLK0, CCLK1 Input LVCMOS LVCMOS clock inputs PCLK_SEL Input LVCMOS LVPECL clock input select CCLK_SEL Input LVCMOS LVCMOS clock input select DSELA, DSELB, DSELC, DSELD Input LVCMOS Clock divider selection MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) QA0-1, QB0-2, QC0-3, QD0-5 Output LVCMOS Clock outputs GND Supply Ground Negative power supply (GND) VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation MOTOROLA 2 MPC9449 Table 3: GENERAL SPECIFICATIONS Symbol Characteristics Min Typ Max Unit Output Termination Voltage ESD Protection (Machine Model) 200 HBM ESD Protection (Human Body Model) 2000 V Latch–Up Immunity 200 mA LU VCC B2 VTT MM Condition V V CPD Power Dissipation Capacitance 12 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 4: ABSOLUTE MAXIMUM RATINGSa Symbol Characteristics Min Max Unit VCC Supply Voltage -0.3 3.8 V VIN DC Input Voltage -0.3 VCC+0.3 V DC Output Voltage -0.3 VOUT IIN IOUT VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA Condition TS Storage Temperature -65 125 °C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. 3 MOTOROLA MPC9449 Table 5: DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40°C to 85°C) Symbol Characteristics VIH VIL Input high voltage VOH Output High Voltage VPP Peak-to-peak input voltage Common Mode Range VCMRb VOL ZOUT IIN Min Typ Max Unit VCC + 0.3 0.8 V LVCMOS V LVCMOS 2.4 V IOH=-24 mAa PCLK, PCLK 250 mV LVPECL PCLK, PCLK 1.0 V LVPECL V V IOL= 24 mA IOL= 12 mA 2.0 Input low voltage VCC-0.6 0.55 0.30 Output Low Voltage Output impedance 14 - 17 Condition W Input Current ±200 µA VIN=VCC or GND ICCQ Maximum Quiescent Supply Current 10 mA All VCC Pins a The MPC9449 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. b VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. Table 6: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = –40°C to 85°C)a Symbol VPP VCMRc fmax fref tP, REF tr, tf tsk(O) Characteristics Max Unit Condition PCLK, PCLK 400 1000 mV LVPECL Common Mode Range PCLK, PCLK 1.0 V LVPECL MHz MHz Output frequency 0 VCC-0.6 200 Input Frequency 0 200 Reference Input Pulse Width 1.5 ns CCLK0, CCLK1 Input Rise/Fall Time Output-to-output Skew Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs Device-to-device Skew Propagation delay tPLZ, HZ tPZL, LZ Output Disable Time Output Enable Time 1.0 ns 50 50 50 100 200 300 ps ps ps ps ps ps 2.5 Output Pulse Skew tPLH, HL tr, tf Typ Peak-to-peak input voltage same frequency different frequencies tsk(PP) tsk(P) Min ns 250 ps 5.0 5.0 ns ns OE to any Q 11 ns OE to any Q 11 ns 1.0 ns CCLK0 or CCLK1 to any Q PCLK to any Q 1.0 1.0 Output Rise/Fall Timec 0.1 3.0 3.0 0.8 to 2.0V DCREF = 50% 0.55 to 2.4V tJIT(CC) Cycle-to-cycle jitter RMS (1 σ) TBD ps a AC characteristics apply for parallel output termination of 50Ω to VTT. b VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. c An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition. MOTOROLA 4 MPC9449 Table 7: DC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to 85°C) Symbol b c Min Input high voltage 1.7 Input low voltage -0.3 VPP Peak-to-peak input voltage PCLK, PCLK 250 Common Mode Range PCLK, PCLK 1.0 VCMRa a Characteristics VIH VIL VOH VOL Output High Voltage ZOUT IIN Output impedance Input Currentc Typ Max Unit VCC + 0.3 0.7 V LVCMOS V LVCMOS mV LVPECL V LVPECL V IOH=-15 mAb IOL= 15 mA VCC-0.6 1.8 Output Low Voltage 0.6 Condition V W 17 - 20 ±200 µA VIN=VCC or GND ICC Maximum Quiescent Supply Current 10 mA All VCC Pins VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. The MPC9449 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Inputs have pull-down or pull-up resistors affecting the input current. Table 8: AC CHARACTERISTICS (VCC = 2.5V ± 5%, TA = –40°C to 85°C)a Symbol VPP VCMRb fmax fref tP, REF tr, tf tsk(O) Max Unit Peak-to-peak input voltage Characteristics PCLK, PCLK 400 1000 mV LVPECL Common Mode Range PCLK, PCLK 1.2 Typ V LVPECL MHz MHz Output frequency 0 VCC-0.6 200 Input Frequency 0 200 Reference Input Pulse Width 1.5 Output-to-output Skew Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs Device-to-device Skew 1.0 ns 50 50 50 100 200 300 ps ps ps ps ps ps 5.0 Output Pulse Skew 1.0 1.0 ps 7.0 7.0 ns ns Propagation delay tPLZ, HZ tPZL, LZ Output Disable Time OE to any Q 11 ns Output Enable Time OE to any Q 11 ns 1.0 ns Output Rise/Fall Timec 0.1 3.5 3.5 0.7 to 1.7V ns 350 tPLH, HL tr, tf CCLK0 or CCLK1 to any Q PCLK to any Q Condition ns CCLK Input Rise/Fall Time same frequency different frequencies tsk(PP) tSK(P) Min DCREF = 50% 0.6 to 1.8V tJIT(CC) Cycle-to-cycle jitter RMS (1 σ) TBD ps a AC characteristics apply for parallel output termination of 50Ω to VTT. b VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. c An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition. 5 MOTOROLA MPC9449 APPLICATIONS INFORMATION impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: Driving Transmission Lines The MPC9449 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. = VS ( Z0 ÷ (RS+R0 +Z0)) = 50Ω || 50Ω = 36Ω || 36Ω = 14Ω = 3.0 ( 25 ÷ (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). VL Z0 RS R0 VL 1. Final skew data pending specification. 3.0 This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9449 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9449 clock driver is effectively doubled due to its capability to drive multiple lines. VOLTAGE (V) 2.5 14Ω 2.0 In 1.5 0.5 RS = 36Ω ZO = 50Ω 0 OutA 2 MPC9449 OUTPUT BUFFER IN 4 6 8 TIME (nS) 10 12 14 Figure 4. Single versus Dual Waveforms RS = 36Ω ZO = 50Ω Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. OutB0 14Ω RS = 36Ω ZO = 50Ω OutB1 Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9449 output buffer is more than sufficient to drive 50Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9449. The output waveform in Figure 4. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output MOTOROLA OutB tD = 3.9386 1.0 MPC9449 OUTPUT BUFFER IN OutA tD = 3.8956 MPC9449 OUTPUT BUFFER RS = 22Ω ZO = 50Ω RS = 22Ω ZO = 50Ω 14Ω 14Ω + 22Ω k 22Ω = 50Ω k 50Ω 25Ω = 25Ω Figure 5. Optimized Dual Line Termination 6 MPC9449 MPC9449 DUT Pulse Generator Z = 50 ZO = 50Ω ZO = 50Ω W RT = 50Ω RT = 50Ω VTT VTT Figure 6. CCLK MPC9449 AC test reference for Vcc = 3.3V and Vcc = 2.5V Differential Pulse Generator Z = 50 ZO = 50 Ω MPC9449 DUT ZO = 50 Ω W RT = 50 Ω RT = 50 Ω VTT VTT Figure 7. PCLK MPC9449 AC test reference 7 MOTOROLA MPC9449 VCC VCC 2 B VCC VCC 2 B CCLK GND GND VCC VCC 2 B VCC VCC 2 B QX GND GND tSK(O) t(LH) t(HL) The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 8. Output–to–output Skew tSK(O) Figure 9. Propagation delay (tPD) test reference PCLK PCLK VCC VCC 2 B CCLK VCMR VPP GND VCC VCC 2 B QX VCC VCC 2 B QX GND GND t(LH) t(HL) t(HL) t(LH) tSK(P) = | tPLH – tPHL | Figure 11. Output Pulse Skew tSK(P) test reference Figure 10. Propagation delay (tPD) test reference tF VCC=3.3V 2.4 VCC=2.5V 1.8V 0.55 0.6V TN tR TJIT(CC) = |TN –TN+1 | The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs Figure 12. Output Transition Time Test Reference MOTOROLA TN+1 Figure 13. Cycle–to–cycle Jitter 8 MPC9449 OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 848D-03 ISSUE C 4X –X– X=L, M, N 4X TIPS 0.20 (0.008) H L–M N 0.20 (0.008) T L–M N CL 52 AB 40 1 G 39 AB 3X VIEW Y –L– VIEW Y –M– B B1 13 V J V1 27 14 26 S θ2 0.10 (0.004) T –H– –T– SEATING PLANE 4X θ3 VIEW AA 0.05 (0.002) D T L–M S N S SECTION AB–AB A 4X M U ROTATED 90_ CLOCKWISE S1 C ÇÇÇÇ ÉÉÉÉ ÉÉÉÉ ÇÇÇÇ 0.13 (0.005) –N– A1 BASE METAL F PLATING S W θ1 2XR R1 0.25 (0.010) C2 θ GAGE PLANE K C1 E Z VIEW AA 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z θ θ1 θ2 θ3 MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC ––– 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC ––– 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ ––– 0_ 12 _ REF 5_ 13 _ MOTOROLA MPC9449 NOTES MOTOROLA 10 MPC9449 NOTES 11 MOTOROLA MPC9449 Motorola reserves the right to make changes without further notice to any products herein. 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All other product or service names are the property of their respective owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. E Motorola, Inc. 2002. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T. Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ 12 MPC9449/D