MPC9600AE

MOTOROLA Freescale Semiconductor, Inc. Order Number: MPC9600/D Rev. 2, 11/2001 SEMICONDUCTOR TECHNICAL DATA Low Voltage 2.5 V and 3.3 V CMOS PLL Clock Driver The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications. Features: • Multiplication of input frequency by 2, 3, 4 and 6 • Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable Freescale Semiconductor, Inc... • Fully integrated PLL • Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz MPC9600 3.3 V OR 2.5 V LOW VOLTAGE CMOS PLL CLOCK DRIVER • Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz • LVCMOS outputs • Outputs disable to high impedance (except QFB) • LVCMOS or LVPECL reference clock options • 48 lead QFP packaging • ±50 ps cycle-to-cycle jitter • 150 ps maximum output-to-output skew • 200 ps maximum static phase offset window FA SUFFIX The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock 48–LEAD LQFP PACKAGE driver. The MPC9600 has the capability to generate clock signals of 50 to CASE 932–03 200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedback path to the feedback input FB_IN. The QFB divider ratio is configurable and determines the PLL frequency multiplication factor when QFB is directly connected to FB_IN. The MPC9600 is optimized for minimizing the propagation delay between the clock input and FB_IN. Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and 6. The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels. The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 Ω transmission to VTT=VCC/2. For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements of the most demanding systems. The VCCA analog power pin doubles as a PLL bypass select line for test purpose. When the VCCA is driven to GND the reference clock will bypass the PLL. The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.  Motorola, Inc. 2001 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. VCCA CCLK PCLK (pulldown) FB_IN FSELA Ref /2 PLL 1 1 PCLK REF_SEL 0 0 (pulldn) VCC 7 /4 Bank A QA0 D QA1 Q 1 FB Vcc/2 (pullup) 0 /8 200 - 400 MHz QA2 /12 QA3 (pulldown) QA4 (pullup) Freescale Semiconductor, Inc... QA5 0 D 7 (pullup) 0 Bank C D QC0–6 Q 7 1 FSELC QB0–6 Q 1 FSELB QA6 Bank B (pullup) 0 Feedback D Q QFB 1 FSEL_FB OE (pullup) (pulldown) 8 GND Figure 1. MPC9600 Logic Diagram MOTOROLA For More Information On This Product, 2 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. PIN CONFIGURATION I/O Type Description QAn Output LVCMOS Bank A outputs QBn Output LVCMOS Bank B outputs QCn Output LVCMOS Bank C outputs QFB Output LVCMOS Differential feedback output REF_SEL Input LVCMOS Reference clock input select FSELA Input LVCMOS Selection of bank A output frequency FSELB Input LVCMOS Selection of bank B output frequency FSELC Input LVCMOS Selection of bank C output frequency FSEL_FB Input LVCMOS Selection of feedback frequency OE Input LVCMOS Output enable VCCA Power supply Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA VCC Power supply Core power supply GND Ground Ground VCC PLL feedback clock input QB6 LVCMOS QB5 Input QB4 FB_IN GND Reference clock input QB3 LVCMOS QB2 Input VCC CCLK QB1 Differential reference clock frequency input QB0 PECL QFB Input GND PCLK, PCLK 36 35 34 33 32 31 30 29 28 27 26 25 VCC 37 24 GND QA6 38 23 QC0 QA5 39 22 QC1 QA4 40 21 QC2 GND 41 20 VCC QA3 42 19 QC3 MPC9600 QC5 QA0 46 15 QC6 FB_IN 47 14 OE GND 48 13 VCC 1 2 3 4 5 6 7 8 9 10 11 12 GND 16 FSELC 45 FSELB QA1 FSELA GND VCCA 17 FSEL_FB 44 REF_SEL VCC VCC QC4 PCLK 18 PCLK 43 CCLK QA2 GND Freescale Semiconductor, Inc... Pin Figure 2. 48 Lead Package Pinout (Top View) TIMING SOLUTIONS For More Information On This Product, 3 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. FUNCTION TABLE (CONTROLS) Control Pin 0 1 REF_SEL CCLK PCLK VCCA PLL Bypass1 PLL Power OE Outputs Enabled Outputs Disabled (except QFB) FSELA Output Bank A at VCO/2 Output Bank A at VCO/4 FSELB Output Bank B at VCO/2 Output Bank B at VCO/4 FSELC Output Bank C at VCO/2 Output Bank C at VCO/4 FSEL_FB Feedback Output at VCO/8 Feedback Output at VCO/12 1..VCCA = GND, PLL off and bypassed for static test and diagnosis Table 1: ABSOLUTE MAXIMUM RATINGS* Symbol Freescale Semiconductor, Inc... Min Max Unit VCC Supply Voltage Parameter –0.3 4.6 V VIN DC Input Voltage –0.3 VCC + 0.3 V VOUT DC Output Voltage –0.3 VCC + 0.3 V IIN DC Input Current ±20 mA IOUT DC Output Current ±50 mA TStor Storage Temperature Range –40 125 °C * Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied. Table 2: GENERAL SPECIFICATIONS Symbol Characteristics VTT Output Termination Voltage Min Typ VCC Max B2 Unit MM ESD Protection (Machine Model) 400 V HBM ESD Protection (Human Body Model) 4000 V CDM ESD Protection (Charged Device Model) 1500 V Latch–Up Immunity 200 mA LU Condition V CPD Power Dissipation Capacitance 10 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 3: DC CHARACTERISTICS (VCC = 3.3 V ±5%, TA = –40° to +85°C) Symbol Characteristics Min VIH Input High Voltage VIL Input Low Voltage VPP Peak-to-peak Input Voltage (DC) PCLK, PCLK 250 VCMRa Common Mode Range (DC) PCLK, PCLK 1.0 VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN Input Leakage Current ICCA Maximum PLL Supply Current Typ 2.0 Max Unit VCC + 0.3 V LVCMOS 0.8 V LVCMOS mV LVPECL V LVPECL V IOH=-24 mAb V V IOL= 24mA IOL= 12mA VCC-0.6 2.4 0.55 0.30 W 14 – 17 2.0 Condition ±150 µA VIN = VCC or GND 5.0 mA VCCA Pin ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. The MPC9600 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. MOTOROLA For More Information On This Product, 4 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. Table 4: DC CHARACTERISTICS (VCC = 2.5 V ±5%, TA = –40° to +85°C) Freescale Semiconductor, Inc... Symbol Characteristics Min VIH Input High Voltage VIL Input Low Voltage VPP Peak-to-peak input voltage (DC) PCLK, PCLK 250 VCMRa Common Mode Range (DC) PCLK, PCLK 1.0 VOH Output High Voltage VOL Output Low Voltage ZOUT Output Impedance IIN Input Leakage Current ICCA Maximum PLL Supply Current Typ 1.7 Max Unit VCC + 0.3 V LVCMOS 0.7 V LVCMOS mV LVPECL V LVPECL V IOH=-15 mAb V IOL= 15 mA VCC-0.6 1.8 0.6 W 17 – 20 3.0 Condition ±150 µA VIN = VCC or GND 5.0 mA VCCA Pin ICCQ Maximum Quiescent Supply Current 1.0 mA All VCC Pins a. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. b. The MPC9600 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines per output. Table 5: AC CHARACTERISTICS (VCC = 3.3 V ±5% or VCC = 2.5 V ±5%, TA = –40° to +85°C)a Characteristics Symbol fref Input Frequency Min B8 feedback (FSEL_FB=0) B12 feedback (FSEL_FB=1) Static test mode (VCCA = GND) fVCO VCO Frequency fMAX Maximum Output Frequency B2 outputs (FSELx=0) B4 outputs (FSELx=1) Typ Max Unit Condition 25 16.67 50 33 MHz MHz PLL locked PLL locked 0 500 MHz VCCA = GND 200 400 MHz 100 50 200 100 MHz MHz 25 75 % PLL locked PLL locked frefDC Reference Input Duty Cycle VPP Peak-to-peak Input Voltage PCLK, PCLK 500 1000 mV LVPECL VCMRb Common Mode Range PCLK, PCLK (VCC = 3.3 V ±5%) PCLK, PCLK (VCC = 2.5 V ±5%) 1.2 1.2 VCC-0.8 VCC-0.6 V V LVPECL LVPECL 1.0 ns see Figure 12 +40 +130 +140 +230 ps ps PLL locked PLL locked all outputs, single frequency all outputs, multiple frequency 70 70 150 150 ps ps Measured at coincident rising edge within QAx output bank within QBx outputs within QCx outputs 30 40 30 75 125 75 ps ps ps 50 55 % 1.0 ns tr, tf CCLK Input Rise/Fall Time t(∅) Propagation Delay (static phase offset) CCLK to FB_IN PECL_CLK to FB_IN tsk(o) –60 +30 Output-to-output Skew DC Output Duty Cycle 45 tr, tf Output Rise/Fall Time 0.1 tPLZ, HZ Output Disable Time 10 ns tPZL, ZH Output Enable Time 10 ns BW PLL Closed Loop Bandwidth 8 feedback (FSEL_FB=0) 12 feedback (FSEL_FB=1) TIMING SOLUTIONS B B 1.0 – 10 0.6 – 4.0 For More Information On This Product, 5 Go to: www.freescale.com MHz MHz see Figure 12 –3 dB point of PLL transfer characteristic MOTOROLA Freescale Semiconductor, Inc. Table 5: AC CHARACTERISTICS (VCC = 3.3 V ±5% or VCC = 2.5 V ±5%, TA = –40° to +85°C)a Symbol tJIT(CC) tJIT(PER) Freescale Semiconductor, Inc... tJIT(∅) Characteristics Cycle-to-cycle Jitterc Typ Max Unit Condition All outputs in All outputs in B2 configuration B4 configuration 40 40 130 180 ps ps See application section for other configurations All outputs in All outputs in B2 configuration B4 configuration 25 20 70 100 ps ps See application section for other configurations 17d 15c ps ps RMS value at fVCO=400MHz Period Jitterc I/O Phase Jitter (1 s) Min VCC = 3.3V VCC = 2.5V tLOCK Maximum PLL Lock Time 5.0 ms a. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC characteristics apply for parallel output termination of 50 Ω to VTT. b. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(∅). c. Cycle–to–cycle and period jitter depends on output divider configuration. d. See applications section for max I/O phase jitter versus frequency. MOTOROLA For More Information On This Product, 6 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. configurations, the table describes the outputs using the input clock frequency CLK as a reference. Programming the MPC9600 The feedback divider division settings establish the output relationship, in addition, it must be ensured that the VCO will The MPC9600 clock driver outputs can be configured into be stable given the frequency of the outputs desired. The several divider modes. Additionally the external feedback of feedback frequency should be used to situate the VCO into a the device allows for flexibility in establishing various input to frequency range in which the PLL will be stable. The design output frequency relationships. The selectable feedback of the PLL supports output frequencies from 50 MHz to 200 divider of the three output groups allows the user to configure MHz while the VCO frequency range is specified from 200 the device for 1:2, 1:3, 1:4 and 1:6 input:output frequency MHz to 400 MHz and should not be exceeded for stable ratios. The use of even dividers ensure that the output duty operation. cycle is always 50%. Table 6 illustrates the various output Table 6: Output Frequency Relationshipa for QFB connected to FB_IN APPLICATIONS INFORMATION Freescale Semiconductor, Inc... Configuration Inputs FSEL_FB FSELA FSELB FSELC 0 0 0 0 0 0 0 0 0 0 Input Frequency Range CLK [MHz] Output Frequency Ratio and Range Ratio, QAx [MHz] Ratio, QBx [MHz] 0 4SCLK (100–200) 4SCLK (100–200) 4SCLK (100–200) 1 4SCLK (100–200) 4SCLK (100–200) 2SCLK (50.0–100) 1 0 4SCLK (100–200) 2SCLK (50.0–100) 4SCLK (100–200) 0 1 1 4SCLK (100–200) 2SCLK (50.0–100) 2SCLK (50.0–100) 1 0 0 2SCLK (50.0–100) 4SCLK (100–200) 4SCLK (100–200) 0 1 0 1 2SCLK (50.0–100) 4SCLK (100–200) 2SCLK (50.0–100) 0 1 1 0 2SCLK (50.0–100) 2SCLK (50.0–100) 4SCLK (100–200) 0 1 1 1 2SCLK (50.0–100) 2SCLK (50.0–100) 2SCLK (50.0–100) 1 0 0 0 6SCLK (100–200) 6SCLK (100–200) 6SCLK (100–200) 1 0 0 1 6SCLK (100–200) 6SCLK (100–200) 3SCLK (50.0–100) 1 0 1 0 6SCLK (100–200) 3SCLK (50.0–100) 6SCLK (100–200) 1 0 1 1 6SCLK (100–200) 3SCLK (50.0–100) 3SCLK (50.0–100) 1 1 0 0 3SCLK (50.0–100) 6SCLK (100–200) 6SCLK (100–200) 1 1 0 1 3SCLK (50.0–100) 6SCLK (100–200) 3SCLK (50.0–100) 1 1 1 0 3SCLK (50.0–100) 3SCLK (50.0–100) 6SCLK (100–200) 1 1 1 1 3SCLK (50.0–100) 3SCLK (50.0–100) 3SCLK (50.0–100) 25.0–50.0 16.67–33.33 Ratio, QCx [MHz] a. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400. Typical and Maximum Period Jitter Specification QA0 to QA6 Device Configuration B B All output banks in 2 or 4 divider configurationa 2 (FSELA=0 and FESLB=0 and FSELC=0) 4 (FSELA=1 and FESLB=1 and FSELC=1) Mixed 2/ 4 divider configurationsb for output banks in 2 divider configurations for output banks in 4 divider configurations B B B B B B QB0 to QB6 QC0 to QC6 Typ Max Typ Max Typ Max 25 20 50 70 50 50 70 100 25 20 50 70 80 25 130 70 100 60 150 100 80 25 130 70 a. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 1 for an example configuration. b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately. See Figure 2 for an example. Typical and Maximum Cycle–to–cycle Jitter Specification QA0 to QA6 Device Configuration B B All output banks in 2 or 4 divider configurationa 2 (FSELA=0 and FESLB=0 and FSELC=0) 4 (FSELA=1 and FESLB=1 and FSELC=1) Mixed 2/ 4 divider configurationsb for output banks in 2 divider configurations for output banks in 4 divider configurations B B B B B B QB0 to QB6 QC0 to QC6 Typ Max Typ Max Typ Max 40 40 90 110 80 120 130 180 40 40 90 110 150 30 250 110 200 120 280 180 150 30 250 110 a. In this configuration, all MPC9600 outputs generate the same clock frequency. b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately. TIMING SOLUTIONS For More Information On This Product, 7 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Figure 3. Configuration for 125 MHz clocks fref = 20.833 MHz CCLK QA0–6 Figure 4. Configuration for 133.3/66.67 MHz clocks fref = 33.33 MHz 125 MHz CCLK QA0–6 7 QB0–6 Freescale Semiconductor, Inc... 125 MHz QB0–6 7 FB_IN 1 FSEL_FB 0 0 0 FSELA FSELB FSELC 133.3 MHz 7 QC0–6 125 MHz 7 QFB 66.67 MHz 7 FB_IN 0 FSEL_FB 0 1 1 FSELA FSELB FSELC 66.67 MHz QC0–6 7 QFB MPC9600 MPC9600 20.833 MHz (Feedback) 33.33 MHz (Feedback) Frequency range Min Max Frequency range Min Max Input 16.67 MHz 33.33 MHz Input 25 MHz 50 MHz QA outputs 100 MHz 200 MHz QA outputs 100 MHz 200 MHz QB outputs 100 MHz 200 MHz QB outputs 100 MHz 200 MHz QC outputs 100 MHz 200 MHz QC outputs 100 MHz 200 MHz Power Supply Filtering The MPC9600 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCCA (PLL) power supply impacts the device characteristics, for instance I/O jitter. The MPC9600 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCCA) of the device.The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCCA pin for the MPC9600. Figure 5. illustrates a typical power supply filter scheme. The MPC9600 frequency and phase stability is most susceptible to noise with spectral content in the 100kHz to 20MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICCA current (the current sourced through the VCCA pin) is typically 3 mA (5 mA maximum), assuming that a minimum of 2.325 V (VCC=3.3 V or VCC=2.5 V) must be maintained on the VCCA pin. The resistor RF shown in Figure 5. “VCCA Power Supply Filter” must have a resistance of 9-10 (VCC=2.5 V) to meet the voltage drop criteria. The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 5. “VCCA Power Supply Filter”, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. W MOTOROLA RF = 9–10 Ω for VCC = 2.5 V or VCC = 3.3 V CF = 22 µF for VCC = 2.5 V or VCC = 3.3 V RF VCCA VCC CF 10 nF MPC9600 VCC 33...100 nF Figure 5. VCCA Power Supply Filter As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9600 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. For More Information On This Product, 8 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. Using the MPC9600 in zero–delay applications Nested clock trees are typical applications for the MPC9600. For these applications the MPC9600 offers a differential LVPECL clock input pair as a PLL reference. This allows for the use of differential LVPECL primary clock distribution devices such as the Motorola MC100ES6111 or MC100ES6226, taking advantage of its superior low-skew performance. Clock trees using LVPECL for clock distribution and the MPC9600 as LVCMOS PLL fanout buffer with zero insertion delay will show significantly lower clock skew than clock distributions developed from CMOS fanout buffers. Freescale Semiconductor, Inc... The external feedback option of the MPC9600 PLL allows for its use as a zero delay buffer. The PLL aligns the feedback clock output edge with the clock input reference edge and virtually eliminates the propagation delay through the device. The remaining insertion delay (skew error) of the MPC9600 in zero-delay applications is measured between the reference clock input and any output. This effective delay consists of the static phase offset (SPO or t(∅)), I/O jitter (tJIT(∅), phase or long-term jitter), feedback path delay and the output-to-output skew (tSK(O) relative to the feedback output. Calculation of part-to-part skew The MPC9600 zero delay buffer supports applications where critical clock signal timing can be maintained across several devices. If the reference clock inputs (CCLK or PCLK) of two or more MPC9600 are connected together, the maximum overall timing uncertainty from the common CCLK input to any output is: tSK(PP) = t( ∅) + tSK(O) + tPD, LINE(FB) + tJIT( ∅)
CF This maximum timing uncertainty consist of 4 components: static phase offset, output skew, feedback board trace delay and I/O (phase) jitter: TCLKCommon QFBDevice 1 ± 1s 0.68268948 ± 2s 0.95449988 ± 3s 0.99730007 ± 4s 0.99993663 ± 5s 0.99999943 ± 6s 0.99999999 The feedback trace delay is determined by the board layout and can be used to fine-tune the effective delay through each device. In the following example calculation a I/O jitter confidence factor of 99.7% (± 3s) is assumed, resulting in a worst case timing uncertainty from input to any output of -261 ps to 341 ps relative to CCLK (VCC=3.3V and fVCO = 200 MHz): tSK(PP) = [–60ps...140ps] + [–150ps...150ps] + [(17ps @ –3)...(17ps @ 3)] + tPD, LINE(FB) tSK(PP) = [–261ps...341ps] + tPD, LINE(FB) Above equation uses the maximum I/O jitter number shown in the AC characteristic table for VCC=3.3V (17 ps RMS). I/O jitter is frequency dependant with a maximum at the lowest VCO frequency (200 MHz for the MPC9600). Applications using a higher VCO frequency exhibit less I/O jitter than the AC characteristic limit. The I/O jitter characteristics in Figure 7. can be used to derive a smaller I/O jitter number at the specific VCO frequency, resulting in tighter timing limits in zero-delay mode and for part-to-part skew tSK(PP). +tSK(O) QFBDevice2 Figure 7. Max. I/O Jitter versus VCO frequency for VCC=2.5V and VCC=3.3V tJIT(∅) +tSK(O) tSK(PP) Figure 6. MPC9600 max. device-to-device skew Due to the statistical nature of I/O jitter a RMS value (1 s) is specified. I/O jitter numbers for other confidence factors (CF) can be derived from Table 8. TIMING SOLUTIONS Probability of clock edge within the distribution tJIT(∅) +t(∅) Max. skew CF tPD,LINE(FB) –t(∅) Any QDevice 1 Any QDevice 2 Table 8: Confidence Facter CF Driving Transmission Lines The MPC9600 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 Ω the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel For More Information On This Product, 9 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9600 OUTPUT BUFFER IN 14Ω RS = 36 Ω ZO = 50 Ω OutA = 50 Ω || 50 Ω = 36 Ω || 36 Ω = 14 Ω = 3.0 ( 25 ÷ (18+17+25) = 1.31 V At the load end the voltage will double due to the near unity reflection coefficient, to 2.6 V. It will then increment towards the quiescent 3.0 V in steps separated by one round trip delay (in this case 4.0 ns). Z0 RS R0 VL 3.0 2.5 VOLTAGE (V) Freescale Semiconductor, Inc... terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50Ω resistance to VCC÷2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9600 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 8. “Single versus Dual Transmission Lines” illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9600 clock driver is effectively doubled due to its capability to drive multiple lines. OutA tD = 3.8956 OutB tD = 3.9386 2.0 In 1.5 1.0 MPC9600 OUTPUT BUFFER IN RS = 36 Ω 0.5 ZO = 50 Ω OutB0 0 14Ω RS = 36 Ω ZO = 50 Ω 2 4 6 OutB1 8 TIME (nS) 10 12 14 Figure 9. Single versus Dual Waveforms Figure 8. Single versus Dual Transmission Lines The waveform plots in Figure 9. “Single versus Dual Line Termination Waveforms” show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9600 output buffer is more than sufficient to drive 50 Ω transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43 ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9600. The output waveform in Figure 9. “Single versus Dual Line Termination Waveforms” shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36Ω series resistor plus the output impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: VL = VS ( Z0 ÷ (RS+R0 +Z0)) MOTOROLA Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 10. “Optimized Dual Line Termination” should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched. MPC9600 OUTPUT BUFFER RS = 22 Ω ZO = 50 Ω RS = 22 Ω ZO = 50 Ω 14Ω 14 Ω + 22 Ω k 22 Ω = 50 Ω k 50 Ω 25 Ω = 25 Ω Figure 10. Optimized Dual Line Termination For More Information On This Product, 10 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. The Following Figures Illustrate the Measurement Reference for the MPC9600 Clock Driver Circuit MPC9600 DUT ZO = 50 Ω Pulse Generator Z = 50 ZO = 50 Ω W RT = 50 Ω RT = 50 Ω VTT VTT Freescale Semiconductor, Inc... Figure 11. CCLK MPC9600 AC test reference Differential Pulse Generator Z = 50 MPC9600 DUT ZO = 50 Ω ZO = 50 Ω W RT = 50 Ω RT = 50 Ω VTT VTT Figure 12. PCLK MPC9600 AC test reference VCC VCC 2 PCLK VCMR VPP PCLK B CCLK GND VCC VCC 2 B FB_IN VCC VCC 2 B FB_IN GND GND t(∅) t(∅) Figure 13. Propagation delay t(∅), static phase offset) test reference Figure 14. Propagation delay t(∅) test reference VCC VCC 2 VCC VCC 2 GND GND B B tP VCC VCC 2 B T0 GND DC = tP /T0 x 100% tSK(O) The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage Figure 15. Output Duty Cycle (DC) TIMING SOLUTIONS The pin–to–pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device Figure 16. Output–to–output Skew tSK(O) For More Information On This Product, 11 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. TN TN+1 TJIT(CC) = |TN –TN+1 | The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs TJIT(P) = |TN –1/f0 | T0 The deviation in cycle time of a signal with respect to the ideal period over a random sample of cycles Figure 17. Cycle–to–cycle Jitter Figure 18. Period Jitter CCLK (PCLK) VCC=3.3 V 2.4 Freescale Semiconductor, Inc... FB_IN 0.55 TJIT(∅) = |T0 –T1 mean| tF VCC=2.5 V 1.8 V 0.6 V tR The deviation in t0 for a controlled edge with respect to a t0 mean in a random sample of cycles Figure 19. I/O Jitter MOTOROLA Figure 20. Output Transition Time Test Reference For More Information On This Product, 12 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. OUTLINE DIMENSIONS FA SUFFIX LQFP PACKAGE CASE 932–03 ISSUE F 4X 0.200 AB T–U Z DETAIL Y A P A1 48 37 1 36 U B V AE B1 12 25 13 AE V1 24 DIM A A1 B B1 C D E F G H J K L M N P R S S1 V V1 W AA Z S1 T, U, Z S DETAIL Y 4X 0.200 AC T–U Z 0.080 AC G AB AD AC M_ BASE METAL ÉÉÉ ÇÇÇ ÇÇÇ ÉÉÉ ÇÇÇ ÉÉÉ MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.170 0.270 1.350 1.450 0.170 0.230 0.500 BSC 0.050 0.150 0.090 0.200 0.500 0.700 0 _ 7_ 12 _REF 0.090 0.160 0.250 BSC 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF TOP & BOTTOM N R J 0.250 Freescale Semiconductor, Inc... T C E GAUGE PLANE 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETER. 3.DATUM PLANE AB IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4.DATUMS T, U, AND Z TO BE DETERMINED AT DATUM PLANE AB. 5.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE AC. 6.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE AB. 7.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.350. 8.MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076. 9.EXACT SHAPE OF EACH CORNER IS OPTIONAL. F D 0.080 M AC T–U Z SECTION AE–AE W H L_ K DETAIL AD AA TIMING SOLUTIONS For More Information On This Product, 13 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES MOTOROLA For More Information On This Product, 14 Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... NOTES TIMING SOLUTIONS For More Information On This Product, 15 Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc... Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. 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Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1, Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852–26668334 Technical Information Center: 1–800–521–6274 HOME PAGE: http://www.motorola.com/semiconductors/ MOTOROLA ◊ More Information For On This Product, 16 Go to: www.freescale.com MPC9600/D TIMING SOLUTIONS