MPC9772FAR2

Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA 3.3V 1:12 LVCMOS PLL Clock Generator The MPC9772 is a 3.3V compatible, 1:12 PLL based clock generator targeted for high performance low-skew clock distribution in mid-range to high-performance networking, computing and telecom applications. With output frequencies up to 240 MHz and output skews less than 250 ps the device meets the needs of the most demanding clock applications. Order number: MPC9772 Rev 3, 05/2004 MPC9772 3.3V 1:12 LVCMOS PLL CLOCK GENERATOR Freescale Semiconductor, Inc... Features • • • • • • • • • • • • • • 1:12 PLL based low-voltage clock generator 3.3V power supply Internal power-on reset Generates clock signals up to 240 MHz Maximum output skew of 250 ps On-chip crystal oscillator clock reference Two LVCMOS PLL reference clock inputs External PLL feedback supports zero-delay capability Various feedback and output dividers (see application section) Supports up to three individual generated output clock frequencies Synchronous output clock stop circuitry for each individual output for power down support Drives up to 24 clock lines Ambient temperature range –40°C to +85°C Pin and function compatible to the MPC972 FA SUFFIX 52 LEAD LQFP PACKAGE CASE 848D Functional Description The MPC9772 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the MPC9772 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9772 features an extensive level of frequency programmability between the 12 outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3. The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a non-binary factor. The MPC9772 also supports the 180° phase shift of one of its output banks with respect to the other output banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation of system baseline timing signals. The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the MPC9772. The MPC9772 has an internal power-on reset. The MPC9772 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines, each of the MPC9772 outputs can drive one or two traces giving the devices an effective fanout of 1:24. The device is pin and function compatible to the MPC972 and is packaged in a 52-lead LQFP package. © Motorola, Inc. 2004 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. MPC9772 QA0 All input resistors have a value of 25kΩ XTAL_IN XTAL_OUT XTAL 0 VCC CCLK0 0 CCLK1 1 CCLK_SEL BANK A 1 Ref VCO ÷2 0 ÷1 1 PLL ÷4, ÷6, ÷8, ÷12 1 ÷4, ÷6, ÷8, ÷10 CLK STOP QA2 QB0 BANK B SYNC PULSE CLK STOP FB QB1 QB2 QB3 VCO_SEL PLL_EN BANK C QC0 VCC CLK STOP 2 2 2 3 FSEL_A[0:1] FSEL_B[0:1] FSEL_C[0:1] FSEL_FB[0:2] VCC 0 1 CLK STOP POWER-ON RESET CLK STOP STOP_DATA STOP_CLK MR/OE CLOCK STOP QC1 QC2 QC3 QFB INV_CLK QSYNC 12 GND QB0 VCC QB1 GND QB2 VCC QB3 FB_IN GND QFB VCC FSEL_FB0 Figure 1. MPC9772 Logic Diagram 39 38 37 36 35 34 33 32 31 30 29 28 27 26 40 25 41 24 42 23 43 22 44 21 45 20 46 MPC9772 19 47 18 48 17 49 16 50 15 51 14 52 1 2 3 4 5 6 7 8 9 10 11 12 13 FSEL_FB1 QSYNC GND QC0 VCC QC1 FSEL_C0 FSEL_C1 QC2 VCC QC3 GND INV_CLK XTAL_IN XTAL_OUT VCC_PLL FSEL_B1 FSEL_B0 FSEL_A1 FSEL_A0 QA3 VCC QA2 GND QA1 VCC QA0 GND VCO_SEL GND MR/OE STOP_CLK STOP_DATA FSEL_FB2 PLL_EN REF_SEL CCLK_SEL CCLK0 CCLK1 Freescale Semiconductor, Inc... QA1 QA3 ÷2, ÷4, ÷6, ÷8 ÷4, ÷6, ÷8, ÷10 ÷12, ÷16, ÷20 VCC REF_SEL FB_IN 0 Figure 2. MPC9772 52-Lead Package Pinout (Top View) MOTOROLA 2 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9772 Table 1. Pin Configuration Pin I/O Function CCLK0 Input LVCMOS PLL reference clock CCLK1 Input LVCMOS Alternative PLL reference clock Analog Crystal oscillator interface XTAL_IN, XTAL_OUT Freescale Semiconductor, Inc... Type FB_IN Input LVCMOS PLL feedback signal input, connect to an QFB CCLK_SEL Input LVCMOS LVCMOS clock reference select REF_SEL Input LVCMOS LVCMOS/PECL reference clock select VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL enable/PLL bypass mode select MR/OE Input LVCMOS Output enable/disable (high-impedance tristate) and device reset FSEL_A[0:1] Input LVCMOS Frequency divider select for bank A outputs FSEL_B[0:1] Input LVCMOS Frequency divider select for bank B outputs FSEL_C[0:1] Input LVCMOS Frequency divider select for bank C outputs FSEL_FB[0:2] Input LVCMOS Frequency divider select for the QFB output INV_CLK Input LVCMOS Clock phase selection for outputs QC2 and QC3 STOP_CLK Input LVCMOS Clock input for clock stop circuitry STOP_DATA Input LVCMOS Configuration data input for clock stop circuitry QA[0-3] Output LVCMOS Clock outputs (Bank A) QB[0-3] Output LVCMOS Clock outputs (Bank B) QC[0-3] Output LVCMOS Clock outputs (Bank C) QFB Output LVCMOS PLL feedback output. Connect to FB_IN. QSYNC Output LVCMOS Synchronization pulse output GND Supply Ground Negative power supply VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details. VCC Supply VCC Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Table 2. Function Table (Configuration Controls) Control Default 0 1 REF_SEL 1 Selects CCLKx as the PLL reference clock Selects the crystal oscillator as the PLL reference clock CCLK_SEL 1 Selects CCLK0 Selects CCLK1 VCO_SEL 1 Selects VCO÷2. The VCO frequency is scaled by a factor of 2 (low VCO frequency range). Selects VCO÷1. (high VCO frequency range) PLL_EN 1 Test mode with the PLL bypassed. The reference clock is substituted for the Normal operation mode with PLL enabled. internal VCO output. MPC9772 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. INV_CLK 1 QC2 and QC3 are in phase with QC0 and QC1 MR/OE 1 Outputs disabled (high-impedance state) and device is reset. During reset/ Outputs enabled (active) output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The MPC9772 requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CCLKx). The device is reset by the internal power-on reset (POR) circuitry during power-up. QC2 and QC3 are inverted (180° phase shift) with respect to QC0 and QC1 VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency ratios. See Table 3 to Table 6 and the applications section for supported frequency ranges and output to input frequency ratios. TIMING SOLUTIONS 3 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9772 Table 3. Output Divider Bank A (NA) VCO_SEL FSEL_A1 FSEL_A0 0 0 0 0 0 0 Table 5. Output Divider Bank C (NC) QA[0:3] VCO_SEL FSEL_C1 FSEL_C0 QC[0:3] 0 VCO÷8 0 0 0 VCO÷4 1 VCO÷12 0 0 1 VCO÷8 1 0 VCO÷16 0 1 0 VCO÷12 1 1 VCO÷24 0 1 1 VCO÷16 1 0 0 VCO÷4 1 0 0 VCO÷2 1 0 1 VCO÷6 1 0 1 VCO÷4 1 1 0 VCO÷8 1 1 0 VCO÷6 1 1 1 VCO÷12 1 1 1 VCO÷8 Freescale Semiconductor, Inc... Table 4. Output Divider Bank B (NB) VCO_SEL FSEL_B1 FSEL_B0 QB[0:3] 0 0 0 VCO÷8 0 0 1 VCO÷12 0 1 0 VCO÷16 0 1 1 VCO÷20 1 0 0 VCO÷4 1 0 1 VCO÷6 1 1 0 VCO÷8 1 1 1 VCO÷10 Table 6. Output Divider PLL Feedback (M) VCO_SEL FSEL_FB2 FSEL_FB1 FSEL_FB0 QFB 0 0 0 0 VCO÷8 0 0 0 1 VCO÷12 0 0 1 0 VCO÷16 0 0 1 1 VCO÷20 0 1 0 0 VCO÷16 0 1 0 1 VCO÷24 0 1 1 0 VCO÷32 0 1 1 1 VCO÷40 1 0 0 0 VCO÷4 1 0 0 1 VCO÷6 1 0 1 0 VCO÷8 1 0 1 1 VCO÷10 1 1 0 0 VCO÷8 1 1 0 1 VCO÷12 1 1 1 0 VCO÷16 1 1 1 1 VCO÷20 MOTOROLA 4 For More Information On This Product, Go to: www.freescale.com TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9772 Table 7. General Specifications Symbol Characteristics Min Typ Max VCC ÷ 2 Unit Condition VTT Output Termination Voltage V MM ESD Protection (Machine Model) 200 V HBM ESD Protection (Human Body Model) 2000 V LU Latch-Up Immunity 200 mA CPD Power Dissipation Capacitance 12 pF Per output CIN Input Capacitance 4.0 pF Inputs Table 8. Absolute Maximum Ratings1 Freescale Semiconductor, Inc... Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC+0.3 V DC Output Voltage –0.3 VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA 125 °C VOUT IIN IOUT TS Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 9. DC Characteristics (VCC = 3.3V ± 5%, TA = –40° to 85°C) Symbol Characteristics Min Typ Max Unit Condition VCC_PLL PLL Supply Voltage 3.0 VCC V LVCMOS VIH Input High Voltage 2.0 VCC + 0.3 V LVCMOS VIL Input Low Voltage 0.8 V LVCMOS VOH Output High Voltage V IOH=–24 mA1 VOL Output Low Voltage V V IOL= 24 mA IOL= 12 mA ZOUT Output Impedance IIN ICC_PLL ICCQ 2.4 0.55 0.30 14 – 17 Input Current2 Maximum PLL Supply Current 3.0 Maximum Quiescent Supply Current W ±200 µA VIN = VCC or GND 5.0 mA VCC_PLL Pin 15 mA All VCC Pins 1. The MPC9772 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines. 2. Inputs have pull-down resistors affecting the input current. TIMING SOLUTIONS 5 For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. MPC9772 Table 10. AC Characteristics (VCC = 3.3V ± 5%, TA = –40° to +85°C)1 2 Max Symbol Freescale Semiconductor, Inc... fREF Characteristics Min ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback Input reference frequency Typ 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 6.25 5.00 Input reference frequency in PLL bypass mode3 fVCO VCO frequency range4 200 fXTAL Crystal interface frequency ranged 10 fMAX Output Frequency ÷2 output ÷4 output ÷6 output ÷8 output ÷10 output ÷12 output ÷16 output ÷20 output ÷24 output 100.0 50.0 33.3 25.0 20.0 16.6 12.5 10.0 8.33 Input Reference Pulse Width5 tR, tF CCLKx Input Rise/Fall Time6 t(∅) tSK(O) DC Output Duty Cycle9 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 15.0 12.0 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 14.37 11.50 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz PLL locked 250 250 MHz PLL bypass 480 460 MHz 240.0 120.0 80.0 60.0 48.0 40.0 30.0 24.0 20.0 MHz 230.00 115.00 76.67 57.50 46.00 38.33 28.75 23.00 19.16 20 2.0 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz ns 1.0 ns –3 –4 –166 +3 +4 +166 ° ° ps within QA outputs within QB outputs within QC outputs all outputs 100 100 100 250 ps ps ps ps (T÷2) – 200 T÷2 (T÷2) + 200 ps 1.0 ns tR, tF Output Rise/Fall Time tPLZ, HZ Output Disable Time 8 ns tPZL, LZ Output Enable Time 8 ns tJIT(CC) Cycle-to-cycle Jitter10 200 ps tJIT(PER) Period Jitter11 150 ps MOTOROLA PLL locked 0.8 to 2.0V PLL locked Propagation Delay (static phase offset)7 CCLK to FB_IN 6.25 MHz < fREF < 65.0 MHz 65.0 MHz < fREF < 125 MHz fREF=50 MHz and feedback=÷8 Output-to-output Skew8 Condition TA = 0°C TA = –40°C to +70°C to +85°C 25 fSTOP_CLK Serial interface clock frequency tPW,MIN Unit 0.1 150 6 For More Information On This Product, Go to: www.freescale.com 0.55 to 2.4V TIMING SOLUTIONS Freescale Semiconductor, Inc. MPC9772 Table 10. AC Characteristics (VCC = 3.3V ± 5%, TA = –40° to +85°C)1 2 (Continued) Max Freescale Semiconductor, Inc... Symbol Characteristics Min tJIT(∅) I/O Phase Jitter RMS (1 σ)12 ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback BW PLL closed loop bandwidth13 ÷4 feedback ÷6 feedback ÷8 feedback ÷10 feedback ÷12 feedback ÷16 feedback ÷20 feedback ÷24 feedback ÷32 feedback ÷40 feedback tLOCK Maximum PLL Lock Time 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Typ Unit Condition ps ps ps ps ps ps ps ps ps ps (VCO=400 MHz) TA = 0°C TA = –40°C to +70°C to +85°C 11 86 13 88 16 19 21 22 27 30 1.20 – 3.50 0.70 – 2.50 0.50 – 1.80 0.45 – 1.20 0.30 – 1.00 0.25 – 0.70 0.20 – 0.55 0.17 – 0.40 0.12 – 0.30 0.11 – 0.28 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 10 ms AC characteristics apply for parallel output termination of 50Ω to VTT. In bypass mode, the MPC9772 divides the input reference clock. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF= fVCO ÷ (M ⋅ VCO_SEL). The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max) ÷ (M ⋅ VCO_SEL) and 10 MHz ≤ fXTAL ≤ 25 MHz. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF, MIN. The MPC9772 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t(∅), tPW,MIN, DC and fMAX can only be guaranteed if tR, tF are within the specified range. Static phase offset depends on the reference frequency. t(∅) [s] = t(∅) [°] ÷ (fREF ⋅ 360°). Excluding QSYNC output. See application section for part-to-part skew calculation. Output duty cycle is DC = (0.5 ± 200 ps ⋅ fOUT) ⋅ 100%. E.g. the DC range at fOUT = 100 MHz is 48%