MSC8103VT1200F

Freescale Semiconductor Technical Data MSC8103 Rev. 12, 5/2008 MSC8103 Network Digital Signal Processor MII • TDMs { •• SIU MCC / UART / HDLC / Transparent / Ethernet / Fast Ethernet / ATM / SCC UTOPIA Interface Serial Interface and TSA CPM 3 × FCC 2 × MCC 64-bit System Bus Interrupt Controller MEMC Timers Parallel I/O 4 × SCC Baud Rate Generators 2 × SMC Dual Ported RAM DMA Engine 2 × SDMA I2C RISC Interrupts 64-bit Local Bus Other Peripherals Extended Core Address Register File Data ALU Register File Q2PPC Bridge 128-bit QBus SIC MEMC What’s New? PIC Rev. 12 includes the following changes: • Table 2-4 changes VIL reference for signal low input current to 0.8 V. Interrupts Boot ROM HDI16 SC140 Core Address ALU JTAG EOnCE™ Power Management Data ALU 64/32-bit System Bus SIC_EXT Bridge SPI Program Sequencer PIT System Protection Reset Control Clock Control SRAM 512 KB Clock/PLL The Freescale MSC8103 16-bit DSP is a member of the family of DSPs based on the StarCore SC140 DSP core. The MSC8103 is available in two core speed levels: 275 and 300 MHz. 8/16-bit Host Interface L1 Interface 128-bit P-Bus 64-bit XA Data Bus 64-bit XB Data Bus Figure 1. MSC8103 Block Diagram The Freescale MSC8103 DSP is a very versatile device that integrates the high-performance SC140 four-ALU (arithmetic logic unit) DSP core along with 512 KB of internal memory, a communications processor module (CPM), a 64-bit bus, a very flexible system integration unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the MSC8103 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8103 CPM is a 32-bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet, and asynchronous transfer mode (ATM) backbones. The MSC8103 60x-compatible bus interface facilitates its connection to multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data memories. The MSC8103 offers 1200 DSP MMACS performance using an internal 300 MHz clock with a 1.6 V core and independent 3.3 V input/output (I/O). © Freescale Semiconductor, Inc., 2001, 2008. All rights reserved. Table of Contents MSC8103 Features .................................................................................................................................................................................... iii Target Applications .....................................................................................................................................................................................iv Product Documentation ..............................................................................................................................................................................iv Chapter 1 Signals/Connections 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Chapter 2 Physical and Electrical Specifications 2.1 2.2 2.3 2.4 2.5 2.6 Chapter 3 Absolute Maximum Ratings .................................................................................................................................................. 2-1 Recommended Operating Conditions .................................................................................................................................... 2-2 Thermal Characteristics ......................................................................................................................................................... 2-2 DC Electrical Characteristics................................................................................................................................................. 2-3 Clock Configuration .............................................................................................................................................................. 2-4 AC Timings............................................................................................................................................................................ 2-7 Packaging 3.1 3.2 Chapter 4 Power Signals ........................................................................................................................................................................ 1-4 Clock Signals ......................................................................................................................................................................... 1-4 Reset, Configuration, and EOnCE Event Signals.................................................................................................................. 1-5 System Bus, HDI16, and Interrupt Signals............................................................................................................................ 1-6 Memory Controller Signals ................................................................................................................................................. 1-13 CPM Ports............................................................................................................................................................................ 1-15 JTAG Test Access Port Signals............................................................................................................................................ 1-36 Reserved Signals.................................................................................................................................................................. 1-36 FC-PBGA Package Description............................................................................................................................................. 3-1 Lidded FC-PBGA Package Mechanical Drawing ............................................................................................................... 3-31 Design Considerations 4.1 4.2 4.3 4.4 Thermal Design Considerations............................................................................................................................................. 4-1 Electrical Design Considerations........................................................................................................................................... 4-1 Power Considerations ............................................................................................................................................................ 4-2 Layout Practices..................................................................................................................................................................... 4-3 Ordering and Contact Information ...............................................................................................................................Back Cover Data Sheet Conventions pin and pinout Although the device package does not have pins, the term pins and pin-out are used for convenience and indicate specific signal locations within the ball-grid array. OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) “asserted” Means that a high true (active high) signal is high or that a low true (active low) signal is low “deasserted” Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. MSC8103 Network Digital Signal Processor, Rev. 12 ii Freescale Semiconductor MSC8103 Features • • • • • • • • • • • SC140 core — Architecture optimized for efficient C/C++ code compilation — Four 16-bit ALUs and two 32-bit AGUs — 1200 DSP MMACS running at 300 MHz — Very low power dissipation — Variable-length execution set (VLES) execution model — JTAG/Enhanced OnCE debug port Communications processor module (CPM) — Programmable protocol machine using a 32-bit RISC engine — 155 Mbps ATM interface (including AAL 0/1/2/5) — 10/100 Mbit Ethernet interface — Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface — HDLC support up to T3 rates, or 256 channels 64- or 32-bit wide bus interface — Support for bursts for high efficiency — Glueless interface to 60x-compatible bus systems — Multi-master support Programmable memory controller — Control for up to eight banks of external memory — User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals — Dedicated pipelined SDRAM memory interface Large internal SRAM — 256K 16-bit words (512 KB) — Unified program and data space configurable by the application — Word and byte addressable DMA controller — 16 DMA channels, FIFO based, with burst capabilities — Sophisticated addressing capabilities Small foot print package — 17 mm × 17 mm lidded FC-PBGA package with lead-bearing or lead-free spheres Very low power consumption — Separate power supply for internal logic (1.6 V) and for I/O (3.3 V) Enhanced 16-bit parallel host interface (HDI16) — Supports a variety of microcontroller, microprocessor, and DSP bus interfaces Phase-lock loops (PLLs) — System PLL — CPM DPLLs (SCC and SCM) Process technology — 0.13 micron copper interconnect process technology MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor iii Target Applications The MSC8103 targets applications requiring very high performance, very large amounts of internal memory, and such networking capabilities as: • • • • Third-generation wideband wireless infrastructure systems Packet Telephony systems Multi-channel modem banks Multi-channel xDSL Product Documentation The documents listed in Table 1 are required for a complete description of the MSC8103 and are necessary to design properly with the part. Documentation is available from the following sources (see back cover for details): • • • • A local Freescale distributor A Freescale Semiconductor sales office A Freescale Semiconductor Literature Distribution Center The world wide web (WWW) Table 1. MSC8103 Documentation Name Description Order Number MSC8103 Technical Data MSC8103 features list and physical, electrical, timing, and package specifications MSC8103/D MSC8101 User’s Guide Detailed functional description of the MSC8101 memory configuration, operation, and register programming. All details apply to the MSC8103. MSC8101UG/D MSC8103 Reference Manual Detailed description of the MSC8103 processor core and instruction set MSC8103RM/D SC140 DSP Core Reference Manual Detailed description of the SC140 family processor core and instruction set MNSC140CORE/D Application Notes Documents describing specific applications or optimized device operation including code examples See the MSC8103 product website MSC8103 Network Digital Signal Processor, Rev. 12 iv Freescale Semiconductor 1 Signals/Connections The MSC8103 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8103 external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are multiplexed. Because the parallel I/O design supported by the MSC8103 communications processor module (CPM) is a subset of the parallel I/O signals supported by the MPC8260 device, port pins are not numbered sequentially. Table 1-1. MSC8103 Functional Signal Groupings Number of Signal Connections Detailed Description Power (VCC, VDD, and GND) 80 Table 1-2 on page 1-4 Clock 6 Table 1-3 on page 1-4 Reset, configuration, and EOnCE 11 Table 1-4 on page 1-5 System bus, HDI16, and interrupts 133 Table 1-5 on page 1-7 Memory controller 27 Table 1-6 on page 1-13 Port A 26 Table 1-7 on page 1-16 Port B 14 Table 1-8 on page 1-21 Port C 18 Table 1-9 on page 1-24 Port D 8 Table 1-10 on page 1-33 JTAG test access port (TAP) 5 Table 1-11 on page 1-36 Reserved (denotes connections that are always reserved) 5 Table 1-12 on page 1-36 Functional Group CPM input/output parallel ports MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-1 Signals/Connections For the signals multiplexed on Ports A–D, see Figure 1-2 VDD VDDH VCCSYN VCCSYN1 → 14 → 25 → 1 → 1 GND GNDSYN GNDSYN1 → 37 → 1 → 1 Port A PA[31–6] ↔ 26 Port B PB[31–18] ↔ 14 Port C PC[31–22, 15–12, 7–4] ↔ 18 Port D PD[31–29, 19–16, 7] TMS TDI TCK TRST TDO EOnCE Event EED EE0 EE1 EE[2–3] EE[4–5] BNKSEL[0–2] TC[0–2] → → → → ← 8 1 1 1 1 1 C P M I / O P O R T S 6 0 x B U S J T A G RESET Configuration DBREQ HPE BTM[0–1] PORESET RSTCONF HRESET SRESET ↔ ↔ ↔ ↔ ↔ → → ↔ ↔ 1 1 1 2 2 1 1 1 1 ↔ ↔ ↔ ↔ ↔ → ↔ ↔ ↔ ↔ ↔ ← ↔ ↔ ↔ 16 4 1 ↔ D[32–47] ↔ D[48–51] ↔ D52 1 1 ↔ D53 ↔ D54 1 1 1 1 1 1 4 ↔ ↔ ↔ ↔ ↔ ↔ ↔ 1 ← Reserved DP0 Reserved 1 ↔ IRQ1 DP1 IRQ1 EXT_BG2 1 1 1 1 1 1 1 1 1 1 1 1 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ← → ↔ ↔ DP2 DP3 DP4 DP5 DP6 DP7 Reserved Reserved DREQ3 DREQ4 DACK3 DACK4 EXT_DBG2 EXT_BR3 EXT_BG3 EXT_DBG3 IRQ6 IRQ7 PSDRAS PBS[0–7] PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5 A[0–31] TT[0–4] TSIZ[0–3] TBST IRQ1 Reserved BR BG ABB TS AACK ARTRY DBG DBB D[0–31] D55 D56 D57 D58 D59 D60 D[61–63] IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 TA TEA NMI NMI_OUT PSDVAL IRQ7 CLKIN → 1 8 1 → CS[0–7] → BCTL1 MODCK[1–3] → 3 2 → BADDR[27–28] CLKOUT DLLIN ← → 1 1 1 1 8 1 1 1 1 1 1 → → → → → → → ↔ → TEST THERM[1–2] SPARE1, SPARE5 Note: ↔ P O W E R 32 5 4 1 1 3 1 1 1 1 1 1 1 1 32 → ↔ ↔ 1 2 2 M E M C ALE BCTL0 PWE[0–7] PSDA10 PSDWE POE PSDCAS PGTA PSDAMUX GBL BADDR[29–31] IRQ[2–3, 5] IRQ2 IRQ3 HDI16 Signals HD[0–15] HA[0–3] HCS1 Single DS Double DS HRW HRD/HRD HDS/HDS HWR/HWR Single HR Double HR HREQ/HREQ HTRQ/HTRQ HACK/HACK HRRQ/HRRQ HDSP HDDS H8BIT HCS2 Reserved EXT_Br2 INT_OUT PSDDQM[0–7] PUPMWAIT PPBS Refer to the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details on how to configure these pins. Figure 1-1. MSC8103 External Signals MSC8103 Network Digital Signal Processor, Rev. 12 1-2 Freescale Semiconductor FCC1 ATM/UTOPIA MPHY MPHY Master Master mux poll dir. poll or Slave FCC1 HDLC/ Ethernet transp. HDLC MII Serial Nibble COL TXENB TXCLAV TXCLAV0 CRS RTS TXSOC (master) TX_ER RXENB TX_EN RXSOC RX_DV (slave) RXCLAV RXCLAV0 RX_ER TXD0 TXD1 TXD2 TXD3 TXD4 TXD3 TXD3 TXD5 TXD2 TXD2 TXD6 TXD1 TXD1 TXD7 TXD0 TXD TXD0 RXD7 RXD0 RXD RXD0 RXD6 RXD1 RXD1 RXD5 RXD2 RXD2 RXD4 RXD3 RXD3 RXD3 RXD2 RXD1 RXD0 GPIO PA31 PA30 PA29 PA28 PA27 SDMA MSNUM0 MSNUM1 SMC2 SMTXD SMRXD FCC2 HDLC/ Ethernet transp. HDLC MII Serial Nibble TX_ER RX_DV TX_EN RX_ER RTS SMSYN SCC2 RXD TXD TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 TXD RXD MSNUM2 MSNUM3 MSNUM4 MSNUM5 SI1 TDMA1 Serial Nibble L1TXD L1TXD0 L1RXD L1RXD0 L1TSYNC SI2 PA7 L1RSYNC TDMB2 L1TXD L1RXD L1RSYNC L1TSYNC TDMC2 L1TXD L1RXD L1TSYNC L1RSYNC TDMD2 L1TXD L1RXD L1TSYNC L1RSYNC PA6 PB31 PB30 PB29 PB28 RTS/TENA COL CRS TXD3 TXD2 TXD3 TXD2 L1TXD3 L1RXD3 TXD1 L1RXD2 TXD0 RXD0 RXD1 RXD2 RXD3 L1RXD1 L1TXD2 L1TXD1 PB27 PB26 PB25 PB24 PB23 I2C SDA SCL Ext. Req. EXT1 SCC1 CTS/CLSN Ext. Req. DREQ2 EXT2 SCC1 CTS/CLSN CD/RENA DACK1 DREQ1 CD SMC1 SMTXD SMRXD RXD TXD RTS/TENA CLK7 TIN4 PC25 CLK8 TIN3/ TOUT4 PC24 BRG8O CLK9 CLK10 PC23 PC22 PC15 PC14 PC13 PC12 LIST1 PC7 LIST2 PC6 LIST3 LIST4 PC5 PC4 PD31 PD30 PD29 PD19 PD18 PD17 PD16 PD7 DRACK1/DONE1 DRACK2/DONE2 SPI BRG1O SPISEL SPICLK SPIMOSI BRG2O SPIMISO SMSYN Figure 1-2. PC29 BRG7O LIST2 LIST4 LIST3 CTS TIN2 BRG5O BRG6O SMTXD CTS/CLSN CD/RENA FCC2 CTS CD RXADDR3 RXCLAV2 TXADDR4 TXCLAV3 RXADDR4 RXCLAV3 RXPRTY TXPRTY TXADDR3 TXCLAV2 LIST1 CLK3 TIN1/ CLK4 PC28 TOUT2 CLK5 TGATE2 PC27 CLK6 TOUT3 PC26 SIU Timer Input BRG4O CLK5 TMCLK DMA DACK2 FCC1 PB22 PB21 PB20 PB19 BRGs Clocks Timers PB18 BRG1O CLK1 TGATE1 PC31 BRG2O CLK2 TOUT1 PC30 BRG3O CTS/CLSN TXADDR0 RXADDR0 TXADDR1 RXADDR1 TXADDR2/ TXADDR2 TXCLAV1 RXADDR2/ RXADDR2 RXCLAV1 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 CPM Port A–D Pin Multiplexed Functionality MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-3 Signals/Connections 1.1 Power Signals Table 1-2. Power and Ground Signal Inputs Power Name Description VDD Internal Logic Power VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VDD power rail. VDDH Input/Output Power This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors. VCCSYN System PLL Power VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCSYN1 SC140 PLL Power VCC dedicated for use with the SC140 core PLL. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. GND System Ground An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground connections, except GNDSYN and GNDSYN1. The user must provide adequate external decoupling capacitors. GNDSYN System PLL Ground Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground. GNDSYN1 SC140 PLL Ground 1 Ground dedicated for SC140 core PLL use. The connection should be provided with an extremely low-impedance path to ground. 1.2 Clock Signals Table 1-3. Signal Name Type Clock Signals Signal Description CLKIN Input Clock In Primary clock input to the MSC8103 PLL. MODCK1 Input Clock Mode Input 1 Defines the operating mode of internal clock circuits. TC0 Output Transfer Code 0 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. BNKSEL0 Output MODCK2 Input Clock Mode Input 2 Defines the operating mode of internal clock circuits. TC1 Output Transfer Code 1 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. BNKSEL1 Output MODCK3 Input Clock Mode Input 3 Defines the operating mode of internal clock circuits. TC2 Output Transfer Code 2 Supplies information that can be useful for debugging bus transactions initiated by the MSC8103. BNKSEL2 Output Bank Select 0 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. Bank Select 1 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. Bank Select 2 Selects the SDRAM bank when the MSC8103 is in 60x-compatible bus mode. MSC8103 Network Digital Signal Processor, Rev. 12 1-4 Freescale Semiconductor Reset, Configuration, and EOnCE Event Signals Table 1-3. Signal Name Clock Signals (Continued) Type Signal Description CLKOUT Output Clock Out The system bus clock. DLLIN Input DLLIN Synchronizes with an external device. Note: When the DLL is disabled, connect this signal to GND. 1.3 Reset, Configuration, and EOnCE Event Signals Table 1-4. Signal Name DBREQ Type Input EE01 Signal Description Debug Request Determines whether to go into SC140 Debug mode when PORESET is deasserted. Enhanced OnCE (EOnCE) Event 0 After PORESET is deasserted, you can configure EE0 as an input (default) or an output. Input Output HPE Reset, Configuration, and EOnCE Event Signals Input EE11 Debug request, enable Address Event Detection Channel 0, or generate an EOnCE event. Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment. Host Port Enable When this pin is asserted during PORESET, the Host port is enabled, the system data bus is 32 bits wide, and the Host must program the reset configuration word. EOnCE Event 1 After PORESET is deasserted, you can configure EE1 as an input (default) or an output. Input Output EE21 Enable Address Event Detection Channel 1 or generate an EOnCE event. Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger external debugging equipment. EOnCE Event 2 After PORESET is deasserted, you can configure EE2 as an input (default) or an output. Input Output EE31 Enable Address Event Detection Channel 2 or generate an EOnCE event or enable the Event Counter. Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment. EOnCE Event 3 After PORESET is deasserted, you can configure EE3 as an input (default) or an output. See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ERCV Register. Input Output Enable Address Event Detection Channel 3 or generate one of the EOnCE events. The DSP has read the EOnCE Receive Register (ERCV). Triggers external debugging equipment. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-5 Signals/Connections Table 1-4. Signal Name BTM[0–1] Reset, Configuration, and EOnCE Event Signals (Continued) Type Signal Description Input Boot Mode 0–1 Determines the MSC8103 boot mode when PORESET is deasserted. See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to set these pins. EE41 EOnCE Event 4 After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on the ETRSMT Register. Input Output EE51 Enable Address Event Detection Channel 4 or generate an EOnCE event. The DSP wrote the EOnCE Transmit Register (ETRSMT). Triggers external debugging equipment. EOnCE Event 5 After PORESET is deasserted, you can configure EE5 as an input (default) or an output. Input Output EED1 Enable Address Event Detection Channel 5. Detection by Address Event Detection Channel 5. Triggers external debugging equipment. Enhanced OnCE (EOnCE) Event Detection After PORESET is deasserted, you can configure EED as an input (default) or output: Input Output Enable the Data Event Detection Channel. Detection by the Data Event Detection Channel. Triggers external debugging equipment. PORESET Input Power-On Reset When asserted, this line causes the MSC8103 to enter power-on reset state. RSTCONF Input Reset Configuration Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the “Power-On Reset Flow” and “Hardware Reset Configuration” sections of the MSC8103 Reference Manual. HRESET Input Hard Reset When asserted, this open-drain line causes the MSC8103 to enter the hard reset state. SRESET Input Soft Reset When asserted, this open-drain line causes the MSC8103 to enter the soft reset state. Note: See the emulation and debug chapter in the SC140 DSP Core Reference Manual for details on how to configure these pins. 1.4 System Bus, HDI16, and Interrupt Signals The system bus, HDI16, and interrupt signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through registers in the System Interface Unit (SIU) and the Host Interface (HDI16). 1-5 describes the signals in this group. Note: To boot from the host interface, the HDI16 must be enabled by pulling up the HPE signal line during PORESET. The configuration word must then be loaded from the host. The configuration word must set the Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 functions. Never set the Host Port Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16, unless the bus size is first changed from 64 bits to 32 bits. Otherwise, unpredictable operation may occur. MSC8103 Network Digital Signal Processor, Rev. 12 1-6 Freescale Semiconductor System Bus, HDI16, and Interrupt Signals Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration includes two IRQ1 and two IRQ7 input lines. The designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Table 1-5. Signal System Bus, HDI16, and Interrupt Signals Data Flow Description A[0–31] Input/Output Address Bus When the MSC8103 is in external master bus mode, these pins function as the address bus. The MSC8103 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8103 is in Internal Master Bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8103 memory controller. TT[0–4] Input/Output Bus Transfer Type The bus master drives these pins during the address tenure to specify the type of transaction. TSIZ[0–3] Input/Output Transfer Size The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction. TBST Input/Output Bus Transfer Burst The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers four quad words). IRQ1 Input Interrupt Request 11 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. GBL Input/Output Global1 When a master within the chip initiates a bus transaction, it drives this pin. When an external master initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is global and it should be snooped by caches in the system. Reserved Output The primary configuration is reserved. BADDR29 Output Burst Address 291 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. IRQ2 Input Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Reserved Output The primary configuration is reserved. BADDR30 Output Burst Address 301 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. IRQ3 Input Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Reserved Output The primary configuration is reserved. BADDR31 Output Burst Address 311 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. IRQ5 Input Interrupt Request 51 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-7 Signals/Connections Table 1-5. Signal BR System Bus, HDI16, and Interrupt Signals (Continued) Data Flow Description 2 Input/Output Output Bus Request An output when an external arbiter is used. The MSC8103 asserts this pin to request ownership of the bus. Input An input when an internal arbiter is used. An external master should assert this pin to request bus ownership from the internal arbiter. Input/Output Output Bus Grant2 An output when an internal arbiter is used. The MSC8103 asserts this pin to grant bus ownership to an external bus master. Input An input when an external arbiter is used. The external arbiter should assert this pin to grant bus ownership to the MSC8103. Input/Output Output Address Bus Busy1 The MSC8103 asserts this pin for the duration of the address bus tenure. Following an address acknowledge (AACK) signal, which terminates the address bus tenure, the MSC8103 deasserts ABB for a fraction of a bus cycle and then stops driving this pin. Input The MSC8103 does not assume bus ownership while it this pin is asserted by an external bus master. IRQ2 Input Interrupt Request 21 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. TS Input/Output Bus Transfer Start Signals the beginning of a new address bus tenure. The MSC8103 asserts this signal when one of its internal bus masters (SC140 core or DMA controller) begins an address tenure. When the MSC8103 senses this pin being asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8103 resources, memory controller support). AACK Input/Output Address Acknowledge A bus slave asserts this signal to indicate that it identified the address tenure. Assertion of this signal terminates the address tenure. ARTRY Input Address Retry Assertion of this signal indicates that the bus transaction should be retried by the bus master. The MSC8103 asserts this signal to enforce data coherency with its internal cache and to prevent deadlock situations. DBG Input/Output Output Data Bus Grant2 An output when an internal arbiter is used. The MSC8103 asserts this pin as an output to grant data bus ownership to an external bus master. Input An input when an external arbiter is used. The external arbiter should assert this pin as an input to grant data bus ownership to the MSC8103. Input/Output Output Data Bus Busy1 The MSC8103 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MSC8103 deasserts DBB for a fraction of a bus cycle and then stops driving this pin. Input The MSC8103 does not assume data bus ownership while DBB is asserted by an external bus master. IRQ3 Input Interrupt Request 31 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. D[0–31] Input/Output Data Bus Most Significant Word In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. In Host Port Disabled mode, these 32 bits are part of the 64-bit data bus. In Host Port Enabled mode, these bits are used as the bus in 32-bit mode. BG ABB DBB MSC8103 Network Digital Signal Processor, Rev. 12 1-8 Freescale Semiconductor System Bus, HDI16, and Interrupt Signals Table 1-5. Signal Data Flow System Bus, HDI16, and Interrupt Signals (Continued) Description D[32–47] Input/Output Data Bus Bits 32–47 In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. HD[0–15] Input/Output Host Data2 When the HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional tri-state data bus. D[48–51] Input/Output Data Bus Bits 48–51 In write transactions the bus master drives the valid data on these pins. In read transactions the slave drives the valid data on these pins. HA[0–3] Input Host Address Line 0–33 When the HDI16 interface bus is enabled, these lines address internal host registers. D52 Input/Output Data Bus Bit 52 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HCS1 Input Host Chip Select3 When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1 and HCS2. D53 Input/Output Data Bus Bit 53 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HRW Input Host Read Write Select3 When the HDI16 interface is enabled in Single Strobe mode, this is the read/write input (HRW). HRD/HRD Input Host Read Strobe3 When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the read data strobe Schmitt trigger input (HRD/HRD). The polarity of the data strobe is programmable. D54 Input/Output Data Bus Bit 54 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HDS/HDS Input Host Data Strobe3 When the HDI16 is programmed to interface with a single data strobe host bus, this pin is the data strobe Schmitt trigger input (HDS/HDS). The polarity of the data strobe is programmable. HWR/HWR Input Host Write Data Strobe3 When the HDI16 is programmed to interface with a double data strobe host bus, this pin is the write data strobe Schmitt trigger input (HWR/HWR). The polarity of the data strobe is programmable. D55 Input/Output Data Bus Bit 55 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HREQ/HREQ Output Host Request3 When the HDI16 is programmed to interface with a single host request host bus, this pin is the host request output (HREQ/HREQ). The polarity of the host request is programmable. The host request may be programmed as a driven or open-drain output. HTRQ/HTRQ Output Transmit Host Request3 When the HDI16 is programmed to interface with a double host request host bus, this pin is the transmit host request output (HTRQ/HTRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-9 Signals/Connections Table 1-5. Signal System Bus, HDI16, and Interrupt Signals (Continued) Data Flow Description D56 Input/Output Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HACK/HACK Output Host Acknowledge3 When the HDI16 is programmed to interface with a single host request host bus, this pin is the host acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable. HRRQ/HRRQ Output Receive Host Request3 When the HDI16 is programmed to interface with a double host request host bus, this pin is the receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. D57 Input/Output Data Bus Bit 57 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HDSP Input Host Data Strobe Polarity3 When the HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP). D58 Input/Output Data Bus Bit 58 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HDDS Input Host Dual Data Strobe3 When the HDI16 interface is enabled, this pin is the host dual data strobe (HDDS). D59 Input/Output Data Bus Bit 59 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. H8BIT Input H8BIT3 When the HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode. D60 Input/Output Data Bus Bit 60 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HCS2 Input Host Chip Select 3 When the HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 chip select is a logical OR of HCS1 and HCS2. D[61–63] Input/Output Data Bus Bits 61–63 Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. These dedicated signals are reserved when the HDI16 is enabled.3 Reserved Reserved Input The primary configuration is reserved. DP0 Input/Output Data Parity 01 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity zero pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0–7]. EXT_BR2 Input External Bus Request 21,2 An external master asserts this pin to request bus ownership from the internal arbiter. MSC8103 Network Digital Signal Processor, Rev. 12 1-10 Freescale Semiconductor System Bus, HDI16, and Interrupt Signals Table 1-5. Signal System Bus, HDI16, and Interrupt Signals (Continued) Data Flow Description 1 IRQ1 Input Interrupt Request 1 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP1 Input/Output Data Parity 11 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity one pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8–15]. EXT_BG2 Output External Bus Grant 21,2 The MSC8103 asserts this pin to grant bus ownership to an external bus master. IRQ2 Input Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP2 Input/Output Data Parity 21 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity two pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16–23]. EXT_DBG2 Output External Data Bus Grant 21,2 The MSC8103 asserts this pin to grant data bus ownership to an external bus master. IRQ3 Input Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP3 Input/Output Data Parity 31 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity three pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24–31]. EXT_BR3 Input External Bus Request 31,2 An external master asserts this pin to request bus ownership from the internal arbiter. IRQ4 Input Interrupt Request 41 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP4 Input/Output Data Parity 41 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity four pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32–39]. DREQ3 Input DMA Request 31 An external peripheral uses this pin to request DMA service. EXT_BG3 Output External Bus Grant 31,2 The MSC8103 asserts this pin to grant bus ownership to an external bus master. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-11 Signals/Connections Table 1-5. Signal System Bus, HDI16, and Interrupt Signals (Continued) Data Flow Description 1 IRQ5 Input Interrupt Request 5 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP5 Input/Output Data Parity 51 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity five pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40–47]. DREQ4 Input DMA Request 41 An external peripheral uses this pin to request DMA service. EXT_DBG3 Output External Data Bus Grant 31,2 The MSC8103 asserts this pin to grant data bus ownership to an external bus master. IRQ6 Input Interrupt Request 61 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP6 Input/Output Data Parity 61 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity six pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48–55]. DACK3 Output DMA Acknowledge 31 The DMA controller drives this output to acknowledge the DMA transaction on the bus. IRQ7 Input Interrupt Request 71 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. DP7 Input/Output Data Parity 71 The master or slave that drives the data bus also drives the data parity signals. The value driven on the data parity seven pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56–63]. DACK4 Output DMA Acknowledge1 The DMA controller drives this output to acknowledge the DMA transaction on the bus. TA Input/Output Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer. TEA Input/Output Transfer Error Acknowledge Indicates a bus error. masters within the MSC8103 monitor the state of this pin. The MSC8103 internal bus monitor can assert this pin if it identifies a bus transfer that is hung. NMI Input Non-Maskable Interrupt When an external device asserts this line, the MSC8103 NMI input is asserted. NMI_OUT Output Non-Maskable Interrupt Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt, pending in the MSC8103 internal interrupt controller, is waiting to be handled by an external host. PSDVAL Input/Output Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL is that the TA pin is asserted to indicate data transfer terminations while the PSDVAL signal is asserted with each data beat movement. Thus, when TA is asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted three times without TA, and finally both pins are asserted to terminate the transfer. MSC8103 Network Digital Signal Processor, Rev. 12 1-12 Freescale Semiconductor Memory Controller Signals Table 1-5. Signal System Bus, HDI16, and Interrupt Signals (Continued) Data Flow Description 1 IRQ7 Input Interrupt Request 7 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. INT_OUT Output Interrupt Output1 Driven from the MSC8103 internal interrupt controller. Assertion of this output indicates that an unmasked interrupt is pending in the MSC8103 internal interrupt controller. Notes: 1. 2. 3. See the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins. When used as the bus control arbiter for the system bus, the MSC8103 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or is not a MSC8103 master device. See the Bus Configuration Register (BCR) description in the SIU chapter in the MSC8103 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the MSC8103 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8103 to obtain master control of the bus. See the host interface (HDI16) chapter in the MSC8103 Reference Manual for details on how to configure these pins. 1.5 Memory Controller Signals Refer to the memory controller chapter in the MSC8103 Reference Manual (MSC8103RM/D) for detailed information about configuring these signals. Table 1-6. Signal Data Flow Memory Controller Signals Description CS[0–7] Output Chip Select Enable specific memory devices or peripherals connected to MSC8103 buses. BCTL1 Output Buffer Control 1 Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details. BADDR[27–28] Output Burst Address 27–28 Two of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8103 memory controller. ALE Output Address Latch Enable Controls the external address latch used in external master bus configuration. BCTL0 Output Buffer Control 0 Controls buffers on the data bus. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for details. PWE[0–7] Output Bus Write Enable Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for write operations. PSDDQM[0–7] Output Bus SDRAM DQM Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. PBS[0–7] Output Bus UPM Byte Select Outputs of the User-Programmable Machine (UPM) in the memory controller. These pins select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-13 Signals/Connections Table 1-6. Signal Memory Controller Signals (Continued) Data Flow Description PSDA10 Output Bus SDRAM A10 Output from the bus SDRAM controller. This pin is part of the address when a row address is driven. It is part of the command when a column address is driven. PGPL0 Output Bus UPM General-Purpose Line 0 One of six general-purpose output lines of the UPM. The values and timing of this pin are programmed in the UPM. PSDWE Output Bus SDRAM Write Enable Output from the bus SDRAM controller. This pin should connect to the SDRAM WE input signal. PGPL1 Output Bus UPM General-Purpose Line 1 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. POE Output Bus Output Enable Output of the bus GPCM. Controls the output buffer of memory devices during read operations. PSDRAS Output Bus SDRAM RAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe (RAS) input signal. PGPL2 Output Bus UPM General-Purpose Line 2 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PSDCAS Output Bus SDRAM CAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address Strobe (CAS) input signal. PGPL3 Output Bus UPM General-Purpose Line 3 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PGTA Input GPCM TA Terminates transactions during GPCM operation. Requires an external pull up resistor for proper operation. PUPMWAIT Input Bus UPM Wait Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device is ready for the operation to continue. PPBS Output Bus Parity Byte Select In systems that store data parity in a separate chip, this output is the byte-select for that chip. PGPL4 Output Bus UPM General-Purpose Line 4 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PSDAMUX Output Bus SDRAM Address Multiplexer Controls the SDRAM address multiplexer when the MSC8103 is in External Master mode. PGPL5 Output Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. MSC8103 Network Digital Signal Processor, Rev. 12 1-14 Freescale Semiconductor CPM Ports 1.6 CPM Ports The MSC8103 CPM supports the subset of MPC8260 signals as described below. • The MSC8103 CPM includes the following set of communication controllers: • Two full-duplex fast serial communications controllers (FCCs) that support: — Asynchronous transfer mode (ATM) through a UTOPIA 8 interface (FCC1 only)—The MSC8103 can operate as one of the following: ° ° ° UTOPIA slave device UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY devices at addresses 0–30 (address 31 is reserved as a null port). — IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII) — High-level data link control (HDLC) Protocol: ° ° Serial mode—Transfers data one bit at a time Nibble mode—Transfers data four bits at a time — Transparent mode serial operation • One FCC that operates with the TSA only • Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to four TDM interfaces • Two full-duplex serial communications controllers (SCCs) that support the following protocols: — IEEE 802.3/fast Ethernet through a media-independent interface (MII) — HDLC Protocol: ° ° — — — — — — Serial mode—Transfers data one bit at a time Nibble mode—Transfers data four bits at a time Synchronous data link control (SDLC) LocalTalk (HDLC-based local area network protocol) Universal asynchronous receiver/transmitter (UART) Synchronous UART (1x clock mode) Binary synchronous (BISYNC) communication Transparent mode serial operation • Two additional SCCs that operate with the TSA only • Two full-duplex serial management controllers (SMCs) that support the following protocols: — General circuit interface (GCI)/integrated services digital network (ISDN) monitor and C/I channels (TSA only) — UART — Transparent mode serial operation • Serial peripheral interface (SPI) support for master or slave operation • Inter-integrated circuit (I2C) bus controller • Time-slot assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto four time-division multiplexed (TDM) interfaces. The TSA uses two serial interfaces (SI1 and SI2). SI1 uses TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2, TDMC2, and TDMD2, which operate only in serial mode. The individual sets of externals signals associated with a specific protocol and data transfer mode are multiplexed across any or all of the ports, as shown in Figure 1-2. The following sections describe the signals supported by Ports A–D. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-15 Signals/Connections 1.6.1 Port A Signals Table 1-7. Port A Signals Name GeneralPurpose I/O PA31 PA30 Peripheral Controller: Dedicated Signal Protocol Output FCC1: TXENB UTOPIA slave Input FCC1: UTOPIA Slave Transmit Enable Asserted by an external UTOPIA master PHY when there is valid transmit cell data (TXD[0–7]). FCC1: COL MII Input FCC1: Media Independent Interface Collision Detect Asserted by an external fast Ethernet PHY when collision is detected. Output FCC1: UTOPIA Slave Transmit Cell Available Asserted by the MSC8103 (UTOPIA slave PHY) when the MSC8103 can accept one complete ATM cell. FCC1: TXCLAV UTOPIA slave FCC1: UTOPIA Master Transmit Enable Asserted by the MSC8103 (UTOPIA master PHY) when there is valid transmit cell data (TXD[0–7]). FCC1: TXCLAV UTOPIA master, or Input FCC1: UTOPIA Master Transmit Cell Available Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. FCC1: TXCLAV0 UTOPIA master, Multi-PHY, direct polling Input FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct Polling Asserted by an external UTOPIA slave PHY using direct polling to indicate that it can accept one complete ATM cell. FCC1: CRS MII PA28 Description FCC1: TXENB UTOPIA master FCC1: RTS HDLC, Serial and Nibble PA29 Dedicated I/O Data Direction Output Input FCC1: Request To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8103 FCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: Media Independent Interface Carrier Sense Asserted by an external fast Ethernet PHY to indicate activity on the cable. FCC1: TXSOC UTOPIA master Output FCC1: UTOPIA Transmit Start of Cell Asserted by the MSC8103 (UTOPIA master PHY) when TXD[0–7] contains the first valid byte of the cell. FCC1: TX_ER MII Output FCC1: Media Independent Interface Transmit Error Asserted by the MSC8103 to force propagation of transmit errors. FCC1: RXENB UTOPIA master Output FCC1: UTOPIA Master Receive Enable Asserted by the MSC8103 (UTOPIA master PHY) to indicate that RXD[0–7] and RXSOC are to be sampled at the end of the next cycle. RXD[0–7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: RXENB UTOPIA slave Input FCC1: TX_EN MII Output FCC1: UTOPIA Master Receive Enable Asserted by an external PHY to indicate that RXD[0–7] and RXSOC is to be sampled at the end of the next cycle. RXD[0–7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: Media Independent Interface Transmit Enable Asserted by the MSC8103 when transmitting data. MSC8103 Network Digital Signal Processor, Rev. 12 1-16 Freescale Semiconductor CPM Ports Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA27 PA26 PA25 PA24 PA23 Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction FCC1: RXSOC UTOPIA slave Output FCC1: RX_DV MII Input Output FCC1: RXCLAV UTOPIA slave Description FCC1: UTOPIA Receive Start of Cell Asserted by the MSC8103 (UTOPIA slave) for an external PHY when RXD[0–7] contains the first valid byte of the cell. FCC1: Media Independent Interface Receive Data Valid Asserted by an external fast Ethernet PHY to indicate that valid data is being sent. The presence of carrier sense but not RX_DV indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. FCC1: UTOPIA Slave Receive Cell Available Asserted by the MSC8103 (UTOPIA slave PHY) when one complete ATM cell is available for transfer. FCC1: RXCLAV UTOPIA master, or Input FCC1: UTOPIA Master Receive Cell Available Asserted by an external PHY when one complete ATM cell is available for transfer. RXCLAV0 UTOPIA master, Multi-PHY, direct polling Input FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: RX_ER MII Input FCC1: Media Independent Interface Receive Error Asserted by an external fast Ethernet PHY to indicate a receive error, which often indicates bad wiring. FCC1: TXD0 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 0 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. SDMA: MSNUM0 Output Module Serial Number Bit 0 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: TXD1 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 1 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 1 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. SDMA: MSNUM1 Output Module Serial Number Bit 1 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: TXD2 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 2 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 2 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-17 Signals/Connections Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Description PA22 FCC1: TXD3 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 3 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 3 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. PA21 FCC1: TXD4 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 4 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 4 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD3 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 3 TXD[3–0] supports MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. FCC1: TXD5 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 5 The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 5 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD2 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 2 TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. This is bit 2 of the transmit data. TXD3 is the most significant bit. FCC1: TXD6 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 6 The MSC8103MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. This is bit 6 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD1 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 1 TXD[3–0] is supported by MII and HDLC transparent nibble modes in FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit. FCC1: TXD7 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 7. The MSC8103 outputs ATM cell octets (UTOPIA interface data) on TXD[0–7]. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD0 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 0 TXD[3–0] is supported by MII and HDLC nibble modes in FCC1. TXD0 is the least significant bit. FCC1: TXD HDLC serial and transparent Output FCC1: HDLC Serial and Transparent Transmit Data Bit This is the single transmit data bit in supported by HDLC serial and transparent modes. PA20 PA19 PA18 MSC8103 Network Digital Signal Processor, Rev. 12 1-18 Freescale Semiconductor CPM Ports Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA17 PA16 PA15 PA14 PA13 Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Description FCC1: RXD7 UTOPIA Input FCC1: UTOPIA Receive Data Bit 7. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: RXD0 MII and HDLC nibble Input FCC1: MII and HDLC Nibble Receive Data Bit 0 RXD[3–0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is the least significant bit. FCC1: RXD HDLC serial and transparent Input FCC1: HDLC Serial and Transparent Receive Data Bit This is the single receive data bit supported by HDLC and transparent modes. FCC1: RXD6 UTOPIA Input FCC1: UTOPIA Receive Data Bit 6. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 6 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: RXD1 MII and HDLC nibble Input FCC1: MII and HDLC Nibble Receive Data Bit 1 This is bit 1 of the receive nibble data. RXD3 is the most significant bit. FCC1: RXD5 UTOPIA Input FCC1: UTOPIA Receive Data Bit 5 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 5 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. RXD2 MII and HDLC nibble Input FCC1: MII and HDLC Nibble Receive Data Bit 2 This is bit 2 of the receive nibble data. RXD3 is the most significant bit. FCC1: RXD4 UTOPIA Input FCC1: UTOPIA Receive Data Bit 4. The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. FCC1: RXD3 MII and HDLC nibble Input FCC1: MII and HDLC Nibble Receive Data Bit 3 RXD3 is the most significant bit of the receive nibble bit. FCC1: RXD3 UTOPIA Input FCC1: UTOPIA Receive Data Bit 3 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. SDMA: MSNUM2 Output Module Serial Number Bit 2 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-19 Signals/Connections Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA12 Peripheral Controller: Dedicated Signal Protocol FCC1: RXD2 UTOPIA SDMA: MSNUM3 PA11 FCC1: RXD1 UTOPIA SDMA: MSNUM4 PA10 PA9 PA8 FCC1: RXD0 UTOPIA Dedicated I/O Data Direction Input Output Input Output Input Description FCC1: UTOPIA Receive Data Bit 2 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 2 of the receive data. RXD7 is the most significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 3 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA RX Receive Data Bit 1 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. This is bit 1 of the receive data. RXD7 is the most significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 4 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA RX Receive Data Bit 0 The MSC8103 inputs ATM cell octets (UTOPIA interface data) on RXD[0–7]. RXD0 is the least significant bit of the receive data. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0–7] is tri-stated, enabled only when RXENB is asserted. SDMA: MSNUM5 Output Module Serial Number Bit 5 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0–4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. SMC2: SMTXD Output SMC2: Serial Management Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). See also PC15. SI1 TDMA1: L1TXD0 TDM nibble Output Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0 L1TXD0 is the least significant bit of the TDM nibble data. SMC2: SMRXD Input SMC2: Serial Management Receive Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). SI1 TDMA1: L1RXD0 TDM nibble Input Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0 L1RXD0 is the least significant bit received in nibble mode. SI1 TDMA1: L1RXD TDM serial Input Time-Division Multiplexing A1: Layer 1 Serial Receive Data TDMA1 receives serial data from L1RXD. MSC8103 Network Digital Signal Processor, Rev. 12 1-20 Freescale Semiconductor CPM Ports Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA7 PA6 1.6.2 Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Description SMC2: SMSYN Input SMC2: Serial Management Synchronization The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). SI1 TDMA1: L1TSYNC TDM nibble and TDM serial Input Time-Division Multiplexing A1: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the Serial Interface with time-slot assigner chapter in the MSC8103 Reference Manual. SI1 TDMA1: L1RSYNC TDM nibble and TDM serial Input Time-Division Multiplexing A1: Layer 1 Receive Synchronization. The synchronizing signal for the receive channel. Port B Signals Table 1-8. Port B Signals Name GeneralPurpose I/O PB31 Peripheral Controller: Dedicated I/O Protocol FCC2: TX_ER MII Output SCC2: RXD PB30 PB29 Dedicated I/O Data Direction Input Description FCC2: Media Independent Interface Transmit Error Asserted by the MSC8103 to force propagation of transmit errors. SCC2: Receive Data SCC2 receives serial data from RXD. SI2 TDMB2: L1TXD TDM serial Output Time-Division Multiplexing B2: Layer 1 Transmit Data TDMB2 transmits serial data out of L1TXD. SCC2: TXD Output SCC2: Transmit Data. SCC2 transmits serial data out of TXD. FCC2: RX_DV MII Input FCC2: Media Independent Interface Receive Data Valid Asserted by an external fast Ethernet PHY to indicate that valid data is being sent. The presence of carrier sense, but not RX_DV, indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. SI2 TDMB2: L1RXD TDM serial Input Time-Division Multiplexing B2: Layer 1 Receive Data TDMB2 receives serial data from L1RXD. Output FCC2: Media Independent Interface Transmit Enable Asserted by the MSC8103 when transmitting data. FCC2: TX_EN MII SI2 TDMB2: L1RSYNC TDM serial Input Time-Division Multiplexing B2: Layer 1 Receive Synchronization The synchronizing signal for the receive channel. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-21 Signals/Connections Table 1-8. Port B Signals (Continued) Name GeneralPurpose I/O PB28 Peripheral Controller: Dedicated I/O Protocol FCC2: RTS HDLC serial, HDLC nibble, and transparent FCC2: RX_ER MII PB25 FCC2: Request to Send One of the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8103 FCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC2: Media Independent Interface Receive Error Asserted by an external fast Ethernet PHY to indicate a receive error, which often indicates bad wiring. SCC2: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8103 SCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. SI2 TDMB2: L1TSYNC TDM serial Input Time-Division Multiplexing B2: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the serial interface with time-slot assigner chapter in the MSC8103 Reference Manual. FCC2: COL MII Input FCC2: Media Independent Interface Collision Detect Asserted by an external fast Ethernet PHY when a collision is detected. Output Time-Division Multiplexing C2: Layer 1 Transmit Data TDMC2 transmits serial data out of L1TXD. FCC2: CRS MII Input FCC2: Media Independent Interface Carrier Sense Input Asserted by an external fast Ethernet PHY to indicate activity on the cable. SI2 TDMC2: L1RXD TDM serial Input Time-Division Multiplexing C2: Layer 1 Receive Data TDMC2 receives serial data from L1RXD. FCC2: TXD3 MII and HDLC nibble Output SI1 TDMA1: L1TXD3 TDM nibble Output SI2 TDMC2: L1TSYNC TDM serial PB24 Description Output SI2 TDMC2: L1TXD TDM serial PB26 Output Input SCC2: RTS, TENA PB27 Dedicated I/O Data Direction Input FCC2: MII and HDLC Nibble Transmit Data Bit 3 TXD3 is bit 3 and the most significant bit of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 3 L1TXD3 is bit 3 and the most significant bit of the transmit data nibble. Time-Division Multiplexing C2: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Reference Manual. FCC2: TXD2 MII and HDLC nibble Output SI1 TDMA1: L1RXD3 nibble Input Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 3 L1RXD3 is bit 3 and the most significant bit of the receive data nibble. SI2 TDMC2: L1RSYNC serial Input Time-Division Multiplexing C2: Layer 1 Receive Synchronization The synchronizing signal for the receive channel. FCC2: MII and HDLC Nibble: Transmit Data Bit 2 TXD2 is bit 2 of the transmit data nibble. MSC8103 Network Digital Signal Processor, Rev. 12 1-22 Freescale Semiconductor CPM Ports Table 1-8. Port B Signals (Continued) Name GeneralPurpose I/O PB23 PB22 PB21 Peripheral Controller: Dedicated I/O Protocol FCC2: TXD1 MII and HDLC nibble Output SI1 TDMA1: L1RXD2 TDM nibble Input PB19 Description FCC2: MII and HDLC Nibble: Transmit Data Bit 1 TXD1 is bit 1 of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 2 L1RXD2 is bit 2 of the receive data nibble. SI2 TDMD2: L1TXD TDM serial Output Time-Division Multiplexing D2: Layer 1 Transmit Data TDMA1 transmits serial data out of L1TXD. FCC2: TXD0 MII and HDLC nibble Output FCC2: MII and HDLC Nibble Transmit Data Bit 0 TXD0 is bit 0 and the least significant bit of the transmit data nibble. FCC2: TXD HDLC serial and transparent Output FCC2: HDLC Serial and Transparent Transmit Data Serial data is transmitted via TXD. SI1 TDMA1: L1RXD1 TDM nibble Input Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 1 L1RXD1 is bit 1 of the receive data nibble. SI2 TDMD2: L1RXD TDM serial Input Time-Division Multiplexing D2: Layer 1 Receive Data Serial data is received via L1RXD. FCC2: RXD0 MII and HDLC nibble Input FCC2: MII and HDLC Nibble Receive Data Bit 0 RXD0 is bit 0 and the least significant bit of the receive data nibble. FCC2: RXD HDLC serial and transparent Input FCC2: HDLC Serial and Transparent Receive Data Serial data is received via RXD. SI1 TDMA1: L1TXD2 TDM nibble PB20 Dedicated I/O Data Direction Output Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 2 L1TXD2 is bit 2 of the transmit data nibble. SI2 TDMD2: L1TSYNC TDM serial Input Time-Division Multiplexing D2: Layer 1 Transmit Synchronize Data The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8103 Reference Manual. FCC2: RXD1 MII and HDLC nibble Input FCC2: MII and HDLC Nibble: Receive Data Bit 1 RXD1 is bit 1 of the receive data nibble. SI1 TDMA1: L1TXD1 TDM nibble Output Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 1 L1TXD1 is bit 1 of the transmit data nibble. SI2 TDMD2: L1RSYNC TDM serial Input Time-Division Multiplexing D2: Layer 1 Receive Synchronize Data The synchronizing signal for the receive channel. FCC2: RXD2 MII and HDLC nibble Input FCC2: MII and HDLC Nibble Receive Data Bit 2 RXD2 is bit 2 of the receive data nibble. I2C: SDA Input/ Output I2C: Inter-Integrated Circuit Serial Data The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-23 Signals/Connections Table 1-8. Port B Signals (Continued) Name GeneralPurpose I/O PB18 Peripheral Controller: Dedicated I/O Protocol FCC2: RXD3 MII and HDLC nibble Input I2C: SCL 1.6.3 Dedicated I/O Data Direction Input/Output Description FCC2: MII and HDLC Nibble Receive Data Bit 3 RXD3 is bit 3 and the most significant bit of the receive data nibble. I2C: Inter-Integrated Circuit Serial Clock The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. Port C Signals Table 1-9. Port C Signals Name GeneralPurpose I/O PC31 Peripheral Controller: Dedicated I/O Protocol BRG1O Dedicated I/O Data Direction Output Description Baud-Rate Generator 1 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 below), it is the source for BRG1O which is the default input for the SIU timers. See the system interface unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. CLK1 Input Clock 1 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIMER1/2: TGATE1 Input Timer 1/2: Timer Gate 1 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. MSC8103 Network Digital Signal Processor, Rev. 12 1-24 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC30 Peripheral Controller: Dedicated I/O Protocol BRG2O CLK2 Timer1: TOUT1 EXT1 PC29 BRG3O Dedicated I/O Data Direction Description Output Baud-Rate Generator 2 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. Input Clock 2 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Output Timer 1: Timer Out 1 The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. Input External Request 1 Asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development. Output Baud-Rate Generator 3 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK3 Input Clock 3 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN2 Input Timer Input 2 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. SCC1: CTS, CLSN Input SCC1: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC15. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-25 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC28 Peripheral Controller: Dedicated I/O Protocol BRG4O Description Output Baud-Rate Generator 4 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK4 Input Clock 4 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN1 Input Timer Input 1 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. Output Timer 2: Timer Output 2 The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. Input SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC13. Timer2: TOUT2 SCC2: CTS, CLSN PC27 Dedicated I/O Data Direction BRG5O Output Baud-Rate Generator 5 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK5 Input Clock 5 When selected, CLK5 is a source for the SIU timers via BRG1O. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. TIMER3/4: TGATE2 Input Timer 3/4: Timer Gate 2 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. MSC8103 Network Digital Signal Processor, Rev. 12 1-26 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC26 Peripheral Controller: Dedicated I/O Protocol BRG6O CLK6 Timer3: TOUT3 PC25 Dedicated I/O Data Direction Description Output Baud-Rate Generator 6 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Input Clock 6 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Output Timer 3: Timer Out 3 The timers (Timer[1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. TMCLK Input BRG7O Output Baud-Rate Generator 7 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. CLK7 Input Clock 7 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN4 Input Timer Input 4 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. Output DMA: Data Acknowledge 2 DACK2, DREQ2, DRACK2 and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. DMA: DACK2 Timer Clock When selected, TMCLK is the designated input to the SIU timers. When TMCLK is configured as the input to the SIU timers, the BRG1O input is disabled. See the System Interface Unit (SIU) chapter in the MSC8103 Reference Manual for additional information. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-27 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC24 Peripheral Controller: Dedicated I/O Protocol BRG8O Output Description Baud-Rate Generator 8 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK8 Input Clock 8 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN3 Input Timer Input 3 A timer can have one of the following sources: another timer, system clock, system clock divided by 16, or a timer input. The CPM supports up to four timer inputs. The timer inputs can be captured on the rising, falling, or both edges. Output Timer 4: Timer Out 4 The timers (Timer1–4]) can output a signal on a timer output (TOUT[1–4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. DMA: DREQ2 Input DMA: Data Request 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. CLK9 Input Clock 9 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer4: TOUT4 PC23 Dedicated I/O Data Direction DMA: DACK1 EXT2 Output DMA: Data Acknowledge 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Input External Request 2 External request input line 2 asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC controller configuration register (RCCR) description in the Chapter 17 of the MSC8103 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development. MSC8103 Network Digital Signal Processor, Rev. 12 1-28 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC22 Peripheral Controller: Dedicated I/O Protocol SI1: L1ST1 CLK10 DMA: DREQ1 PC15 PC14 SMC2: SMTXD Dedicated I/O Data Direction Output Input Description Serial Interface 1: Layer 1 Strobe 1 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Clock 10 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Input/ Output DMA: Request 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Output SMC2: Serial Management Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that support three protocols or modes: UART, transparent, or general-circuit interface (GCI). See also PA9. SCC1: CTS/CLSN Input SCC1: Clear To Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC29. FCC1: TXADDR0 UTOPIA master Output FCC1: TXADDR0 UTOPIA slave Input FCC1: UTOPIA Master Transmit Address Bit 0 This is master transmit address bit 0. FCC1: UTOPIA Slave Transmit Address Bit 0 This is slave transmit address bit 0. Output Serial Interface 1: Layer 1 Strobe 2 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also be generate output wave forms for such applications as stepper-motor control. SCC1: CD, RENA Input SCC1: Carrier Detect, Receive Enable Typically used in conjunction with RTS supported by SCC1. The MSC8103MSC8103 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: RXADDR0 UTOPIA master Output FCC1: RXADDR0 UTOPIA slave Input SI1: L1ST2 FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0 This is master receive address bit 0. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0 This is slave receive address bit 0. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-29 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC13 Peripheral Controller: Dedicated I/O Protocol SI1: L1ST4 SCC2: CTS,CLSN PC12 Dedicated I/O Data Direction Output Serial Interface 1: Layer 1 Strobe 4 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Input SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8103 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC28. FCC1:TXADDR1 UTOPIA master Output FCC1: TXADDR1 UTOPIA slave Input SI1: L1ST3 Description FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1 This is master transmit address bit 1. FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 1 This is slave transmit address bit 1. Output Serial Interface 1: Layer 1 Strobe 3 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SCC2: CD, RENA Input SCC2: Carrier Detect, Request Enable Typically used in conjunction with RTS supported by SCC2. The MSC8103 SCC2 transmitter requests to the receiver that it sends data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: RXADDR1 UTOPIA master Output FCC1: RXADDR1 UTOPIA slave Input FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1 This is master receive address bit 1. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1 This is slave receive address bit 1. MSC8103 Network Digital Signal Processor, Rev. 12 1-30 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC7 Peripheral Controller: Dedicated I/O Protocol SI2: L1ST1 FCC1: CTS HDLC serial, HDLC nibble, and transparent PC6 Dedicated I/O Data Direction Description Output Serial Interface 2: Strobe 1 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Input FCC1: Clear To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CTS is asynchronous with the data. FCC1: TXADDR2 UTOPIA master Output FCC1: TXADDR2 UTOPIA slave Input FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2 This is slave transmit address bit 2. FCC1: TXCLAV1 UTOPIA multi-PHY master, direct polling Input FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct Polling Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. Output Serial Interface 2: Layer 1 Strobe 2 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Input FCC1: Carrier Detect In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CD is an input asynchronous with the data. SI2: L1ST2 FCC1: CD HDLC serial, HDLC nibble, and transparent FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2 This is master transmit address bit 2. FCC1: RXADDR2 UTOPIA master Output FCC1: RXADDR2 UTOPIA slave Input FCC1: UTOPIA Slave Receive Address Bit 2 This is slave receive address bit 2. FCC1: RXCLAV1 UTOPIA multi-PHY master, direct polling Input FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2 This is master receive address bit 2. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-31 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC5 PC4 Peripheral Controller: Dedicated I/O Protocol Dedicated I/O Data Direction Description SMC1: SMTXD Output SMC1: Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). SI2: L1ST3 Output Serial Interface 2: Layer 1 Strobe 3 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC2: CTS HDLC serial, HDLC nibble, and transparent Input FCC2: Clear To Send In the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). CTS is asynchronous with the data. SMC1: SMRXD Input SMC1: Receive Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Output Serial Interface 2: Layer 1 Strobe 4 The MSC8103 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SI2: L1ST4 FCC2: CD HDLC serial, HDLC nibble, and transparent Input FCC2: Carrier Detect In the standard modem interface signals supported by FCC2 (RTS, CTS and CD). CD is asynchronous with the data. MSC8103 Network Digital Signal Processor, Rev. 12 1-32 Freescale Semiconductor CPM Ports 1.6.4 Port D Signals Table 1-10. Port D Signals Name GeneralPurpose I/O PD31 Peripheral Controller: Dedicated I/O Protocol SCC1: RXD Input DMA: DRACK1 DMA: DONE1 PD30 Description SCC1: Receive Data SCC1 receives serial data from RXD. Output DMA: Data Request Acknowledge 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Input/ Output DMA: Done 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. SCC1: TXD Output SCC1: Transmit Data SCC1 transmits serial data out of TXD. DMA: DRACK2 Output DMA: Data Request Acknowledge 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Input/ Output DMA: Done 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. DMA: DONE2 PD29 Dedicated I/O Data Direction SCC1: RTS, TENA Output SCC1: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8103 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. FCC1: RXADDR3 UTOPIA master Output FCC1: UTOPIA Multi-PHY Master Receive Address Bit 3 This is master receive address bit 3. FCC1: RXADDR3 UTOPIA slave Input FCC1: UTOPIA Slave Receive Address Bit 3 This is slave receive address bit 3. FCC1: RXCLAV2 UTOPIA multi-PHY master, direct polling Input FCC1: UTOPIA Multi-PHY Master Receive Cell Available 2 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-33 Signals/Connections Table 1-10. Port D Signals (Continued) Name GeneralPurpose I/O PD19 Peripheral Controller: Dedicated I/O Protocol Description FCC1: TXADDR4 UTOPIA master Output FCC1: TXADDR4 UTOPIA slave Input FCC1: UTOPIA Slave Transmit Address Bit 4 This is slave transmit address bit 4. FCC1: TXCLAV3 UTOPIA multi-PHY master, direct polling Input FCC1: UTOPIA Multi-PHY master Transmit Cell Available 3 Direct Polling Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. Output Baud Rate Generator 1 Output The CPM supports up to 8 BRGs for use internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 above), it is the source for BRG1O which is the default input for the SIU timers. See the system interface unit (SIU) chapter in the MSC8103 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 above), the BRG1O input to the SIU timers is disabled. Input SPI: Select The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. SPISEL is the enable input to the SPI slave. In a multimaster environment, SPISEL (always an input) detects an error when more than one master is operating. SPI masters must output a slave select signal to enable SPI slave devices by using a separate general-purpose I/O signal. Assertion of an SPI SPISEL while it is master causes an error. BRG1O SPI: SPISEL PD18 Dedicated I/O Data Direction FCC1: Multi-PHY Master Transmit Address Bit 4 Multiplexed Polling This is master transmit address bit 4. FCC1: RXADDR4 UTOPIA master Output FCC1: RXADDR4 UTOPIA slave Input FCC1: UTOPIA Slave Receive Address Bit 4 This is slave receive address bit 4. FCC1: RXCLAV3 UTOPIA multi-PHY master, direct polling Input FCC1: UTOPIA Multi-PHY Master Receive Cell Available 3 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. Input/ Output SPI: Clock The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. SPICLK is a gated clock, active only during data transfers. Four combinations of SPICLK phase and polarity can be configured. When the SPI is a master, SPICLK is the clock output signal that shifts received data in from SPIMISO and transmitted data out to SPIMOSI. SPI: SPICLK FCC1: UTOPIA Master Receive Address Bit 4 This is master receive address bit 4. MSC8103 Network Digital Signal Processor, Rev. 12 1-34 Freescale Semiconductor CPM Ports Table 1-10. Port D Signals (Continued) Name GeneralPurpose I/O PD17 Peripheral Controller: Dedicated I/O Protocol BRG2O Output FCC1: RXPRTY UTOPIA Input SPI: SPIMOSI PD16 PD7 Dedicated I/O Data Direction Input/ Output FCC1: TXPRTY UTOPIA Output Description Baud Rate Generator 2 Output The CPM supports up to 8 BRGs for use internally to the MSC8103 and/or to provide an output to one of the 8 BRG pins. FCC1: UTOPIA Receive Parity This is the odd parity bit for RXD[0–7]. SPI: Master Output Slave Input The SPI interface comprises our signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK) and select (SPISEL). The SPI can be configured as a slave or master in single- or multiplemaster environments. When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. FCC1: UTOPIA Transmit Parity This is the odd parity bit for TXD[0–7]. SPI: SPIMISO Input/ Output SPI: Master Input Slave Output The SPI interface comprises four signals: master out slave in (SPIMOSI), master in slave out (SPIMISO), clock (SPICLK), and select (SPISEL). The SPI can be configured as a slave or master in single- or multiple-master environments. When the SPI is a slave, SPICLK is the clock input that shifts received data in from SPIMOSI and transmitted data out through SPIMISO. SMC1: SMSYN Input SMC1: Serial Management Synchronization The SMC interface consists of SMTXD, SMRXD, SMSYN and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that support three protocols or modes: UART, transparent or generalcircuit interface (GCI). FCC1: TXADDR3 UTOPIA master Output FCC1: TXADDR3 UTOPIA slave Input FCC1: UTOPIA Slave Transmit Address Bit 3 This is slave transmit address bit 3. FCC1: TXCLAV2 UTOPIA multi-PHY master, direct polling Input FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 2 Direct Polling Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. FCC1: UTOPIA Master Transmit Address Bit 3 This is master transmit address bit 3. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-35 Signals/Connections 1.7 JTAG Test Access Port Signals The MSC8103 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-11. Table 1-11. JTAG Test Access Port Signals Signal Name Type Signal Description TCK Input Test Clock A test clock signal for synchronizing JTAG test logic. TDI Input Test Data Input A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. TDO Output Test Data Output A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. TMS Input Test Mode Select Sequences the test controller’s state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. TRST Input Test Reset Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted after power up. 1.8 Reserved Signals Table 1-12. Signal Name TEST Type Input Reserved Signals Signal Description Test Used for manufacturing testing. You must connect this input to GND. THERM[1–2] — Leave disconnected. SPARE1, 5 — Spare Pins Leave disconnected for backward compatibility with future revisions of this device. MSC8103 Network Digital Signal Processor, Rev. 12 1-36 Freescale Semiconductor Physical and Electrical Specifications 2 This document contains detailed information on environmental limits, power considerations, DC/AC electrical characteristics, and AC timing specifications for the MSC8103 communications processor, mask set 2K87M. For additional information, see the MSC8103 Reference Manual. 2.1 Absolute Maximum Ratings CAUTION This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VCC). In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8103. Table 2-1. Rating Core supply voltage PLL supply voltage 3 3 3 Absolute Maximum Ratings2 Symbol Value Unit VDD –0.2 to 1.7 V VCCSYN –0.2 to 1.7 V VDDH –0.2 to 3.6 V Input voltage3 VIN (GND – 0.2) to 3.6 V Maximum operating temperature range4 TJ –40 to 120 °C TSTG –55 to +150 °C I/O supply voltage Storage temperature range Notes: 1. 2. 3. 4. Functional operating conditions are given in Table 2-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. See Section 4.2, Electrical Design Considerations, on page 4-1 for more information. Section 4.1, Thermal Design Considerations, on page 4-1 includes a formula for computing the chip junction temperature (TJ). MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-1 Physical and Electrical Specifications 2.2 Recommended Operating Conditions Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 2-2. Recommended Operating Conditions Rating Symbol Value Unit VDD 275 MHz: 1.5 to 1.7 300 MHz: 1.55 to 1.7 V V PLL supply voltage VCCSYN 275 MHz: 1.5 to 1.7 300 MHz: 1.55 to 1.7 V V I/O supply voltage VDDH 3.135 to 3.465 V SC140 core supply voltage Input voltage VIN –0.2 to VDDH + 0.2 V Operating temperature range TJ 275 MHz: –40 to 105 300 MHz: –40 to 75 °C °C 2.3 Thermal Characteristics Table 2-3 describes thermal characteristics of the MSC8103. Table 2-3. Characteristic Thermal Characteristics Lidded FC-PBGA 17 × 17 mm Symbol Unit Natural Convection 200 ft/min (1 m/s) airflow RθJA or θJA 50 37 Junction-to-ambient, four-layer board RθJA or θJA 22 18 Junction-to-board3 RθJB or θJB 15 °C/W Junction-to-case4 RθJC or θJC 0.8 °C/W Junction-to-ambient, single-layer board1, 2 1, 3 Notes: 1. 2. 3. 4. 5. °C/W °C/W Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and EIA/JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board (JESD51-9) horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface without thermal grease. TBD = to be determined. If a thin (less than 50 micron) thermal grease interface is established to a heat sink from the lid, the junction to sink thermal resistance is about 0.7 °C/W. See Section 4.1, Thermal Design Considerations, on page 4-1 for details on these characteristics. MSC8103 Network Digital Signal Processor, Rev. 12 2-2 Freescale Semiconductor DC Electrical Characteristics 2.4 DC Electrical Characteristics This section describes the DC electrical characteristics for the MSC8103. The measurements in Table 2-4 assume the following system conditions: • • • • TJ = 0 – 100 °C VDD = 1.6 V ± 5% VDC VDDH = 3.3 V ± 5% VDC GND = 0 VDC Note: The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same direction (for example, both VDDH and VDD vary by ± 5 percent). Table 2-4. Characteristic DC Electrical Characteristics Symbol 1 Min Max Unit V Input high voltage , all inputs except CLKIN VIH 2.0 3.465 Input low voltage1 VIL GND 0.8 V CLKIN input high voltage VIHC 2.5 3.465 V CLKIN input low voltage2 VILC GND 0.8 V Input leakage current, VIN = VDDH IIN — 10 µA Tri-state (high impedance off state) leakage current, VIN = VDDH IOZ — 10 µA Signal low input current3, VIL = 0.8 V IL — –4.0 mA Signal high input current3, VIH = 2.0 V IH — 4.0 mA Output high voltage, IOH = –2 mA, except open drain pins VOH 2.4 — V Output low voltage, IOL= 3.2 mA VOL — 0.4 V Symbol Typical Unit Core power dissipation at 300 MHz PCORE 450 mW CPM power dissipation at 200 MHz PCPM 320 mW SIU power dissipation at 100 MHz PSIU 80 mW Core leakage power PLCO 3 mW CPM leakage power PLCP 6 mW SIU leakage power PLSI 2 mW Notes: 1. 2. 3. See Figure 2-1 for undershoot and overshoot voltages. The optimum CLKIN duty cycle is obtained when: VILC = VDDH – VIHC. Not tested. Guaranteed by design. VIH VDDH + 20% VDDH + 10% VDDH VIL GND GND – 0.3 V GND – 0.7 V Must not exceed 10% of clock period Figure 2-1. Overshoot/Undershoot Voltage for VIH and VIL Table 2-5. Characteristic Typical Power Dissipation MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-3 Physical and Electrical Specifications 2.5 Clock Configuration The following sections provide a general description of clock configuration. 2.5.1 Valid Clock Modes Table 2-6 shows the maximum frequency values for each rated core frequency (275 or 300 MHz). The user must ensure that maximum frequency values are not exceeded. Table 2-6. Maximum Frequencies Characteristic Core Frequency CPM Frequency (CPMCLK) Maximum Frequency in MHz 275 300 183.33 200 Bus Frequency (BCLK) 91.67 100 Serial Communication Controller Clock Frequency (SCLK) 91.67 100 Baud Rate Generator Clock Frequency (BRGCLK) 91.67 100 External Clock Output Frequency (CLKOUT) 91.67 100 Six bit values map the MSC8103 clocks to one of the valid configuration mode options. Each option determines the CLKIN, SC140, system bus, SCC clock, CPM, and CLKOUT frequencies. The six bit values are derived from three dedicated input pins (MODCK[1–3]) and three bits from the hard reset configuration word (MODCK_H). To configure the SPLL pre-division factor, SPLL multiplication factor, and the frequencies for the SC140, SCC clocks, CPM parallel I/O ports, and system buses, the MODCK[1–3] pins are sampled and combined with the MODCK_H values when the internal power-on reset (internal PORESET) is deasserted. Clock configuration changes only when the internal PORESET signal is deasserted. The following factors are configured: • SPLL pre-division factor (SPLL PDF) • SPLL multiplication factor (SPLL MF) • Bus post-division factor (Bus DF) • CPM division factor (CPM DF) • Core division factor (Core DF) • CPLL pre-division factor (CPLL PDF) • CPLL multiplication factor (CPLL MF) The SCC division factor (SCC DF) is fixed at 4. The BRG division factor (BRG DF) is configured through the System Clock Control Register (SCCR) and can be 4, 16 (default after reset), 64, or 256. Note: Refer to Clock Mode Selection for MSC8101 and MSC8103 Mask Set 2K87M (AN2306) for details on clock configuration. 2.5.2 Clocks Programming Model This section describes the clock registers in detail. The registers discussed are as follows: • System Clock Control Register (SCCR) • System Clock Mode Register (SCMR) MSC8103 Network Digital Signal Processor, Rev. 12 2-4 Freescale Semiconductor Clock Configuration 2.5.2.1 System Clock Control Register Bit 0 1 2 3 4 5 6 7 8 9 10 25 26 11 12 27 28 13 14 15 29 30 31 — Type Reserved Reset — Bit 16 17 18 19 20 21 22 23 24 — CLKODIS — Type Reserved R/W Reserved Reset — 0 — Figure 2-2. DFBRG R/W 0 1 System Clock Control Register (SCCR)—0x10C80 SCCR is memory-mapped into the SIU register map of the MSC8103. Table 2-7. SCCR Bit Descriptions Defaults Name Bit No. Description PORESET Hard Reset — 0–26 — — CLKODIS 27 0 Unaffected — 28–29 — — DFBRG 30–31 01 Unaffected Settings Reserved. Write to 0 fro future compatibility. CLKOUT Disable Disables the CLKOUT signal. The value of CLKOUT when disabled is indeterminate (can be 1 or 0). 0 1 CLKOUT enabled (default) CLKOUT disabled 00 01 10 11 Divide by 4 Divide by 16 (default value) Divide by 64 Divide by 256 Reserved. Write to 0 fro future compatibility. Division Factor for the BRG Clock Defines the BRGCLK frequency. Changing this value does not result in a loss of lock condition. 2.5.2.2 System Clock Mode Register Bit 0 1 2 3 4 COREPDF 5 6 7 8 COREMF R Reset — 16 17 18 19 20 SPLLPDF 21 22 23 SPLLMF Type R Reset — Figure 2-3. 10 11 12 BUSDF Type Bit 9 24 25 — DLLDIS 13 14 15 CPMDF 26 27 — 28 29 30 31 COREDF System Clock Mode Register (SCMR)—0x10C88 SCMR is a read-only register that is updated during power-on reset (PORESET) and provides the mode control signals to the PLLs, DLL, and clock logic. This register reflects the currently defined configuration settings. For details of the available setting options, see AN2306/D. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-5 Physical and Electrical Specifications Table 2-8. Name Bit No. SCMR Field Descriptions Defaults Description Settings PORESET Hard Reset COREPDF 0–3 Configuration Pins Unaffected Core PLL Pre-Division Factor 0000 CPLL PDF = 1 0001 CPLL PDF = 2 0010 CPLL PDF = 3 0011 CPLL PDF = 4 All other combinations not used. COREMF 4–7 Configuration Pins Unaffected Core Multiplication Factor 0101 CPLL MF = 10 0110 CPLL MF = 12 0111 CPLL MF = 14 All other combinations not used. BUSDF 8–11 Configuration Pins Unaffected 60x-compatible Bus Division Factor 0001 Bus DF = 2 0010 Bus DF = 3 0011 Bus DF = 4 0100 Bus DF = 5 0101 Bus DF = 6 All other combinations not used. CPMDF 12–15 Configuration Pins Unaffected CPM Division Factor 0000 CPM DF = 1 0001 CPM DF = 2 0010 CPM DF = 3 All other combinations not used. SPLLPDF 16–19 Configuration Pins Unaffected SPLL Pre-Division Factor 0000 SPLL PDF = 1 0001 SPLL PDF = 2 0010 SPLL PDF = 3 0011 SPLL PDF = 4 0100 SPLL PDF = 5 0101 SPLL PDF = 6 All other combinations not used SPLLMF 20–23 Configuration Pins Unaffected SPLL Multiplication Factor 0101 SPLL MF = 10 0110 SPLL MF = 12 0111 SPLL MF = 14 1000 SPLL MF = 16 1001 SPLL MF = 18 1010 SPLL MF = 20 1011 SPLL MF = 22 1100 SPLL MF = 24 1101 SPLL MF = 26 1110 SPLL MF = 28 1111 SPLL MF = 30 All other combinations not used — 24 — — DLLDIS 25 Configuration Pins Unaffected — 26–27 — — COREDF 28–31 Configuration Pins Unaffected Reserved DLL Disable 0 1 DLL operation is enabled DLL is disabled Reserved Core Division Factor 0000 CORE DF = 1 0001 CORE DF = 2 0010 CORE DF = 3 0011 CORE DF = 4 0100 CORE DF = 5 0101 CORE DF = 6 All other combinations not used. MSC8103 Network Digital Signal Processor, Rev. 12 2-6 Freescale Semiconductor AC Timings 2.6 AC Timings The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. AC timings are based on a 50 pF load, except where noted otherwise, and 50 Ω transmission line. 2.6.1 Output Buffer Impedances Table 2-9. Output Buffer Impedances Output Buffers Typical Impedance (Ω) System Bus 35 Memory Controller 35 Parallel I/O 55 Note: 2.6.2 These are typical values at 65°C. The impedance may vary by ±25% depending on device process and operating temperature. Start-Up Timing Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.6.3 describes the clocking characteristics. Section 2.6.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8103 device: • • • PORESET and TRST must be asserted externally for the duration of the power-up sequence. See Table 2-14 for timing. If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDDH levels and then the VDD levels (see Figure 2-5 and Figure 2-6). CLKIN can start toggling after VDDH reaches its nominal level, but it must toggle before VDD reaches 0.5 V to guarantee correct device operation (see Figure 2-4 and Figure 2-6). The following figures show acceptable start-up sequence examples. Figure 2-4 shows a sequence in which VDD and VDDH are raised together. Figure 2-5 shows a sequence in which CLKIN starts toggling after VDDH reaches its nominal level and before VDD is applied. Figure 2-6 shows a sequence in which VDD is raised after VDDH and CLKIN begins to toggle shortly before VDD reaches the 0.5 V level. VDDH = Nominal Value VDD = Nominal Value 1 VDDH Nominal Level Voltage 3.3 V 2.2 V 1.6 V VDD Nominal Level o.5 V Time PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted VDD/VDDH Applied Figure 2-4. Start-Up Sequence with VDD and VDDH Raised Together MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-7 Physical and Electrical Specifications VDDH = Nominal VDD = Nominal 1 VDDH Nominal Voltage 3.3 V 1.6 V VDD Nominal 1.06 V Time PORESET/TRST asserted VDDH applied Figure 2-5. VDD applied PORESET/TRST Deasserted CLKIN starts toggling Start-Up Sequence with CLKIN Started After VDDH and Before VDD VDDH = Nominal VDD = Nominal 1 VDDH Nominal Voltage 3.3 V 1.6 V VDD Nominal 1.06 V o.5 V Time PORESET/TRST asserted VDDH applied PORESET/TRST deasserted VDD applied Figure 2-6. 2.6.3 CLKIN starts toggling Start-Up Sequence with VDDH Raised Before VDD with CLKIN Started Before VDD = 0.5 V Clocking and Timing Characteristics Table 2-10. Characteristic System Clock Parameters Minimum Maximum Unit — 0.5 ns 18 100 MHz CLKIN slope — 5 ns DLLIN slope — 2 ns CLKOUT frequency jitter — (0.01/CLKOUT) + CLKIN jitter ns Delay between CLKOUT and DLLIN — 5 ns Phase Jitter between BCLK and DLLIN CLKIN frequency Notes: 1. 2. 1,2 Low CLKIN frequency causes poor PLL performance. Choose a CLKIN frequency high enough to keep the frequency after the predivider (SPLLMFCLK) higher than 18 MHz. CLKIN should have a 50% ± 5% duty cycle. MSC8103 Network Digital Signal Processor, Rev. 12 2-8 Freescale Semiconductor AC Timings Table 2-11. Clock Ranges Maximum Rated Core Frequency Clock Symbol All Max. Values for SC140 Clock Rating of: Min 275 MHz 300 MHz CLKIN 18 MHz 91.67 MHz 100 MHz SPLLMFCLK 18 MHz 34.38 MHz 37.5 MHz BCLK CLKOUT 18 MHz 91.67 MHz 100 MHz SCLK 35 MHz 91.67 MHz 100 MHz Communications Processor Module CPMCLK 70 MHz 183.3 MHz 200 MHz SC140 Core DSPCLK 72 MHz 275 MHz 300 MHz Baud Rate Generator • For BRG DF = 4 • For BRG DF = 16 (default) • For BRG DF = 64 • For BRG DF = 256 BRGCLK 36 MHz 9 MHz 2.25 MHz 562.5 KHz 91.67 MHz 22.91 MHz 5.73 MHz 1.43 MHz 100 MHz 25 MHz 6.25 MHz 1.56 MHz Input Clock SPLL MF Clock Bus/Output Serial Communications Controller 2.6.4 Reset Timing The MSC8103 has several inputs to the reset logic: • Power-on reset (PORESET) • External hard reset (HRESET) • External soft reset (SRESET) Asserting an external PORESET causes concurrent assertion of an internal PORESET signal, HRESET, and SRESET. When the external PORESET signal is deasserted, the MSC8103 samples several configuration pins: • RSTCONF—determines whether the MSC8103 is a master (0) or slave (1) device • DBREQ—determines whether to operate in normal mode (0) or invoke the SC140 debug mode (1) • HPE—disable (0) or enable (1) the host port (HDI16) • BTM[0–1]—boot from external memory (00) or the HDI16 (01) All these reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the last sources to cause a reset. Table 2-12 describes reset causes. Table 2-12. Name Power-on reset (PORESET) Direction Input Reset Causes Description PORESET initiates the power-on reset flow that resets all the MSC8103s and configures various attributes of the MSC8103, including its clock mode. Hard reset (HRESET) Input/Output The MSC8103 can detect an external assertion of HRESET only if it occurs while the MSC8103 is not asserting reset. During HRESET, SRESET is asserted. HRESET is an opendrain pin. Soft reset (SRESET) Input/Output The MSC8103 can detect an external assertion of SRESET only if it occurs while the MSC8103 is not asserting reset. SRESET is an open-drain pin. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-9 Physical and Electrical Specifications 2.6.4.1 Reset Operation The reset control logic determines the cause of a reset, synchronizes it if necessary, and resets the appropriate logic modules. The memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only on hard reset. Soft reset initializes the internal logic while maintaining the system configuration. The MSC8103 has three mechanisms for reset configuration: host reset configuration, hardware reset configuration, and reduced reset configuration. 2.6.4.2 Power-On Reset Flow Asserting the PORESET external pin initiates the power-on reset flow. PORESET should be asserted externally for at least 16 input clock cycles after external power to the MSC8103 reaches at least 2/3 VCC. As Table 2-13 shows, the MSC8103 has five configuration pins, four of which are multiplexed with the SC140 EONCE Event (EE[0–1], EE[4–5]) pins and the fifth of which is the RSTCONF pin. These pins are sampled at the rising edge of PORESET. In addition to these configuration pins, three (MODCK[1–3]) pins are sampled by the MSC8103. The signals on these pins and the MODCK_H value in the Hard Reset Configuration Word determine the PLL locking mode, by defining the ratio between the DSP clock, the bus clocks, and the CPM clock frequencies. Table 2-13. Pin External Configuration Signals Description Settings RSTCONF Reset Configuration Input line sampled by the MSC8103 at the rising edge of PORESET. 0 1 Reset Configuration Master. Reset Configuration Slave. DBREQ/ EE0 EONCE Event Bit 0 Input line sampled after SC140 core PLL locks. Holding EE0 high when PORESET is deasserted puts the SC140 into Debug mode. 0 SC140 starts the normal processing mode after reset. SC140 enters Debug mode immediately after reset. Host Port Enable Input line sampled at the rising edge of PORESET. If asserted, the Host port is enabled, the system data bus is 32-bit wide, and the Host must program the reset configuration word. 0 1 Host port disabled (hardware reset configuration enabled). Host port enabled. Boot Mode Input lines sampled at the rising edge of PORESET, which determine the MSC8103 Boot mode. 00 01 10 11 MSC8103 boots from external memory. MSC8103 boots from HDI16. Reserved. Reserved. HPE/EE1 BTM[0–1]/ EE[4–5] Table 2-14. No. 1 2 3 Reset Timing Characteristics Required external PORESET duration minimum • CLKIN = 18 MHz • CLKIN = 75 MHz Delay from deassertion of external PORESET to deassertion of internal PORESET • CLKIN = 18 MHz • CLKIN = 75 MHz Delay from deassertion of internal PORESET to SPLL lock • SPLLMFCLK = 18 MHz • SPLLMFCLK = 25 MHz 1 Expression Min Max Unit 888.8 213.3 — — ns ns 16 / CLKIN 1024 / CLKIN 56.89 13.65 μs μs 44.4 32.0 μs μs 800 / SPLLMFCLK MSC8103 Network Digital Signal Processor, Rev. 12 2-10 Freescale Semiconductor AC Timings Table 2-14. No. 4 5 6 Note: Characteristics Delay from SPLL lock to DLL lock • DLL enabled — BCLK = 18 MHz — BCLK = 75 MHz • DLL disabled Delay from SPLL lock to HRESET deassertion • DLL enabled — BCLK = 18 MHz — BCLK = 75 MHz • DLL disabled — BCLK = 18 MHz — BCLK = 75 MHz Delay from SPLL lock to SRESET deassertion • DLL enabled — BCLK = 18 MHz — BCLK = 75 MHz • DLL disabled — BCLK = 18 MHz — BCLK = 75 MHz Reset Timing (Continued) Expression Min Max 3073 / BLCK — Unit 170.72 40.97 0.0 μs μs ns 199.17 47.5 μs μs 28.4 6.83 μs μs 199.33 47.84 μs μs 28.61 6.87 μs μs 3585 / BLCK 512 / BLCK 3588 / BLCK 515 / BLCK Value given for lowest possible CLKIN frequency 18 MHz to ensure proper initialization of reset sequence. 2.6.4.3 Host Reset Configuration Host reset configuration allows the host to program the reset configuration word via the Host port after PORESET is deasserted, as described in the MSC8103 Reference Manual. The MSC8103 samples the signals described in Table 2-13 one the rising edge of PORESET when the signal is deasserted. If HPE is sampled high, the host port is enabled. In this mode the RSTCONF pin must be pulled up. The device extends the internal PORESET until the host programs the reset configuration word register. The host must write four 8-bit half-words to the Host Reset Configuration Register address to program the reset configuration word, which is 32 bits wide. For more information, see the MSC8103 Reference Manual. The reset configuration word is programmed before the internal PLL and DLL in the MSC8103 are locked. The host must program it after the rising edge of the PORESET input. In this mode, the host must have its own clock that does not depend on the MSC8103 clock. After the PLL and DLL are locked, HRESET remains asserted for another 512 bus clocks and is then released. The SRESET is released three bus clocks later (see Figure 2-7). MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-11 Physical and Electrical Specifications 1 PORESET Input PORESET Internal asserted for min 16 CLKIN. RSTCONF, HPE HRM, BTM pins are sampled Any time HRESET Output (I/O) Host programs Reset Configuration Word MODCK[1–3] pins are sampled. MODCK_H bits are ready for PLL. PLL locked DLL locked SRESET Output (I/O) 2 3 4 PLL locks after 800 SPLLMFCLKs and DLL locks 3073 BUS clocks after PLL is locked. When DLL is disabled, reset period is shortened by DLL lock time. Figure 2-7. 5 6 HRESET/SRESET are extended for 512/515 BUS clocks, respectively, from PLL and DLL lock Host Reset Configuration Timing MSC8103 Network Digital Signal Processor, Rev. 12 2-12 Freescale Semiconductor AC Timings 2.6.4.4 Hardware Reset Configuration Hardware reset configuration is enabled if HPE is sampled low at the rising edge of PORESET. The value driven on RSTCONF while PORESET changes from assertion to deassertion determines the MSC8103 configuration. If RSTCONF is deasserted (driven high) while PORESET changes, the MSC8103 acts as a configuration slave. If RSTCONF is asserted (driven low) while PORESET changes, the MSC8103 acts as a configuration master. Section 2.6.4.4, Hardware Reset Configuration, explains the configuration sequence and the terms “configuration master” and “configuration slave.” Directly after the deassertion of PORESET and choice of the reset operation mode as configuration master or configuration slave, the MSC8103 starts the configuration process. The MSC8103 asserts HRESET and SRESET throughout the power-on reset process, including configuration. Configuration takes 1024 CLOCKIN cycles, after which MODCK[1–3] are sampled to determine the MSC8103’s working mode. Next, the MSC8103 halts until the SPLL locks. The SPLL locks according to MODCK[1–3], which are sampled, and to MODCK_H taken from the Reset Configuration Word. SPLL locking time is 800 reference clocks, which is the clock at the output of the SPLL Pre-divider. After the SPLL is locked, all the clocks to the MSC8103 are enabled. If the DLLDIS bit in the reset configuration word is reset, the DLL starts the locking process after the SPLL is locked. During PLL and DLL locking, HRESET and SRESET are asserted. HRESET remains asserted for another 512 BUS clocks and is then released. The SRESET is released three bus clocks later. If the DLLDIS bit in the reset configuration word is set, the DLL is bypassed and there is no locking process, thus saving the DLL locking time. Figure 2-8 shows the power-on reset flow. 1 PORESET Input PORESET Internal asserted for min 16 CLKIN. RSTCONF is sampled for master/slave determination MODCK[1–3] are sampled. MODCK_H bits are ready for PLL. HRESET Output (I/O) PLL locked SRESET Output (I/O) 2 3 In reset configuration mode: reset configuration sequence occurs in this period. Figure 2-8. DLL locked 4 PLL locks after 800 SPLLMFCLKs. DLL locks 3073 bus clocks after PLL is locked. When DLL is disabled, reset period is shortened by 3073 bus clocks. 5 6 HRESET/SRESET are extended for 512/515 bus clocks, respectively, from PLL and DLL Lock time. Hardware Reset Configuration Timing MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-13 Physical and Electrical Specifications 2.6.5 System Bus Access Timing 2.6.5.1 Core Data Transfers Generally, all MSC8103 bus and system output signals are driven from the rising edge of the reference clock (REFCLK), which is DLLIN. Memory controller signals, however, trigger on four points within a DLLIN cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of DLLIN (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL clock ratio selected, as Table 2-15 shows. Table 2-15. Tick Spacing for Memory Controller Signals Tick Spacing (T1 Occurs at the Rising Edge of DLLIN) PLL Clock Ratio T2 T3 T4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 DLLIN 1/2 DLLIN 3/4 DLLIN 1:2.5 3/10 DLLIN 1/2 DLLIN 8/10 DLLIN 1:3.5 4/14 DLLIN 1/2 DLLIN 11/14 DLLIN Figure 2-9 is a graphical representation of Table 2-15. DLLIN for 1:2, 1:3, 1:4, 1:5, 1:6 T1 T2 T3 T4 DLLIN for 1:2.5 T1 T2 T3 T4 for 1:3.5 DLLIN T1 T2 Figure 2-9. T3 T4 Internal Tick Spacing for Memory Controller Signals Note: The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. SDRAM machine outputs change only on the DLLIN rising edge. MSC8103 Network Digital Signal Processor, Rev. 12 2-14 Freescale Semiconductor AC Timings Table 2-16. No. AC Timing for SIU Inputs Characteristic Value2 Units 10 Hold time for all signals after the 50% level of the DLLIN rising edge 0.5 ns 11a ABB/AACK set-up time before the 50% level of the DLLIN rising edge 3.5 ns 11b DBG/DBB/BR/TC set-up time before the 50% level of the DLLIN rising edge 5.0 ns 11c ARTRY set-up time before the 50% level of the DLLIN rising edge 4.0 ns 11d TA set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 3.5 4.0 ns ns TEA set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 4.0 3.0 ns ns PSDVAL set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 3.5 3.5 ns ns 11g TS set-up time before the 50% level of the DLLIN rising edge 5.0 ns 11h BG set-up time before the 50% level of the DLLIN rising edge 4.5 ns 12 Data bus set-up time before the 50% level of the DLLIN rising edge in Normal • Pipeline mode • Non-pipeline mode 2.5 5.0 ns ns 2.5 8.0 ns ns DP set-up time before the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 4.0 9.0 ns ns Address bus set-up time before the 50% level of the DLLIN rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • Non-extra cycle mode (SIUBCR[EXDD] = 1) 5.0 8.0 ns ns 5.0 5.5 ns ns 3.0 ns 11e 11f 13 Data bus set-up time before the 50% level of the DLLIN rising edge in ECC and PARITY modes • Pipeline mode • Non-pipeline mode 14 15a Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the DLLIN rising edge • Extra cycle mode (SIUBCR[EXDD] = 0) • Non-extra cycle mode (SIUBCR[EXDD] = 1) 15b PUPMWAIT/IRQ signals set-up time before the 50% level of the DLLIN rising edge 161 Notes: 1. 2. The set-up time for these signals is for synchronous operation. Any set-up time can be used for asynchronous operation. Input specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are measured at the pin. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-15 Physical and Electrical Specifications Table 2-17. AC Timing for SIU Outputs Maximum2 No. 31a Characteristic Min. Units 30 pF 50 pF TA delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 1.0 1.0 5.0 4.0 6.5 5.5 ns ns TEA delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 1.0 1.0 3.0 3.5 4.5 5.0 ns ns PSDVAL delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 1.0 1.0 4.0 3.5 5.5 5.0 ns ns Address bus delay from the 50% level of the DLLIN rising edge • Multi master mode (SIUBCR[EBM] = 1) • Single master mode (SIUBCR[EBM] = 0) 1.0 1.0 6.3 5.5 7.8 7.0 ns ns Address attributes: TT/TBST/TSIZ/GBL delay from the 50% level of the DLLIN rising edge 1.0 5.5 7.0 ns 32c BADDR delay from the 50% level of the DLLIN rising edge 1.0 3.5 5.0 ns 33a Data bus delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 1.0 1.0 5.0 6.0 6.5 7.5 ns ns DP delay from the 50% level of the DLLIN rising edge • Pipeline mode • Non-pipeline mode 1.0 1.0 4.0 6.5 5.5 8.0 ns ns Memory controller signals/ALE delay from the 50% level of the DLLIN rising edge 1.0 5.5 7.0 ns 31b 31c 32a 32b 33b 34 35a DBG/BR/DBB delay from the 50% level of the DLLIN rising edge 1.0 4.0 5.5 ns 35b AACK/ABB/CS delay from the 50% level of the DLLIN rising edge 1.0 4.5 6.0 ns 35c BG delay from the 50% level of the DLLIN rising edge 1.0 4.0 5.5 ns 35d TS delay from the 50% level of the DLLIN rising edge 1.0 3.5 5.0 ns 36 Delay from the 50% level of the DLLIN rising edge for all other signals 1.0 4.5 6.0 ns Notes: 1. 2. The maximum bus frequency depends on the mode: • In 60x-compatible mode connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. In multi-master mode when connected to another MSC8103 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. • Certain bus modes, such as non-extra cycle (EXDD = 1), non-pipelined, and ECC/Parity modes, result in slower bus frequencies. • In single-master mode, the frequency depends on the timing of the devices connected to the MSC8103. Output specifications are measured from the 50% level of the rising edge of DLLIN to the 50% level of the signal. Timings are measured at the pin. MSC8103 Network Digital Signal Processor, Rev. 12 2-16 Freescale Semiconductor AC Timings DLLIN 10 AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB/TS inputs 11 10 12 Data bus inputs—normal mode 10 Data bus inputs—ECC and parity modes 13 DP inputs 14 Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL inputs 15 PUPMWAIT/IRQn input 10 16 31 PSDVAL/TEA/TA outputs 32 Address bus/TT[0–4]/TC[0–2]/TBST/TSIZ[0–3]/GBL/BADDR[27–31] outputs Data bus outputs DP outputs 33a 33b Memory controller/ALE signals 34 35 AACK/ARTRY/ABB/TS/DBG/BG/BR/DBB/CS signals 36 All other normal mode outputs Figure 2-10. Bus Signal Timing MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-17 Physical and Electrical Specifications 2.6.5.2 DMA Data Transfers Table 2-18 describes the DMA signal timing. Table 2-18. Number DMA Signals Characteristic Minimum Maximum Units 6 — ns 0.5 — ns 9 — ns 72 DREQ set-up time before DLLIN falling edge 73 DREQ hold time after DLLIN falling edge 74 DONE set-up time before DLLIN rising edge 75 DONE hold time after DLLIN rising edge 0.5 — ns 76 DACK/DRACK/DONE delay after DLLIN rising edge 0.5 9 ns The DREQ signal is synchronized with the falling edge of DLLIN. DONE timing is relative to the rising edge of DLLIN. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-18. Figure 2-11 shows synchronous peripheral interaction. DLLIN 73 72 DREQ 75 74 DONE Input 76 DACK/DONE/DRACK Outputs Figure 2-11. 2.6.6 HDI16 Signals Host Interface (HDI16) Timing1, 2 Table 2-19. Number DMA Signals Characteristics3 4 Expression Value Unit (1.5 × TC) + 5.0 Note 11 ns TC + 5.0 Note 11 ns 44a Read data strobe minimum assertion width HACK read minimum assertion width 44b Read data strobe minimum deassertion width4 HACK read minimum deassertion width 44c Read data strobe minimum deassertion width4 after “Last Data Register” reads5,6, or between two consecutive CVR, ICR, or ISR reads7 HACK minimum deassertion width after “Last Data Register” reads5,6 (2.5 × TC) + 5.0 Note 11 ns 45 Write data strobe minimum assertion width8 HACK write minimum assertion width (1.5 × TC) + 5.0 Note 11 ns 46 Write data strobe minimum deassertion width8 HACK write minimum deassertion width after ICR, CVR and Data Register writes5 (2.5 × TC) + 5.0 Note 11 ns 47 Host data input minimum set-up time before write data strobe deassertion8 Host data input minimum set-up time before HACK write deassertion — 5.0 ns MSC8103 Network Digital Signal Processor, Rev. 12 2-18 Freescale Semiconductor AC Timings Table 2-19. Host Interface (HDI16) Timing1, 2 (Continued) Characteristics3 Number Expression Value Unit — 5.0 ns — 5.0 ns (2.0 × TC) + 5.0 Note 11 ns — 5.0 ns 8 48 Host data input minimum hold time after write data strobe deassertion Host data input minimum hold time after HACK write deassertion 49 Read data strobe minimum assertion to output data active from high impedance4 HACK read minimum assertion to output data active from high impedance valid4 50 Read data strobe maximum assertion to output data HACK read maximum assertion to output data valid 51 Read data strobe maximum deassertion to output data high impedance4 HACK read maximum deassertion to output data high impedance 52 Output data minimum hold time after read data strobe deassertion4 Output data minimum hold time after HACK read deassertion — 5.0 ns 53 HCS[1–2] minimum assertion to read data strobe assertion4 — 5.0 ns 54 HCS[1–2] minimum assertion to write data strobe assertion8 55 HCS[1–2] maximum assertion to output data valid 56 57 — 5.0 ns TC + 5.0 Note 11 ns HCS[1–2] minimum hold time after data strobe deassertion9 — 0.0 ns HA[0–3], HRW minimum set-up time before data strobe assertion9 • Read • Write — 0 5.0 ns ns 58 HA[0–3], HRW minimum hold time after data strobe deassertion9 — 5.0 ns 61 Maximum delay from read data strobe deassertion to host request deassertion for “Last Data Register” read4, 5, 10 (3.5 × TC) + 5.0 Note 11 ns 62 Maximum delay from write data strobe deassertion to host request deassertion for “Last Data Register” write5,8,10 (3.0 × TC) + 5 Note 11 ns 63 Minimum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) deassertion to HREQ assertion. (5.0 × TC) + 5.0 Note 11 ns Maximum delay from DMA HACK (OAD=0) or Read/Write data strobe(OAD=1) assertion to HREQ deassertion (3.5 × TC) + 5.0 Note 11 ns 64 Notes: 1. 2. 3. 4. 5. TC = 1/ DSPCLK. At 300 MHz, TC = 3.3 ns In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable. VCC = 3.3 V ± 0.3 V; TJ = –40°C to +100 °C, CL = 50 pF The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode. In 64-bit mode, The “last data register” is the register at address $7, which is the last location to be read or written in data transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1). 6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal. 7. This timing is applicable only if two consecutive reads from one of these registers are executed. 8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode. 9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe (HDS/HDS) in the single data strobe mode. 10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full (treat as level Host Request). 11. Compute the value using the expression. Figure 2-12 and Figure 2-13 show HDI16 read signal timing. Figure 2-14 and Figure 2-15 show HDI16 write signal timing. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-19 Physical and Electrical Specifications HA[0–3] 57 58 56 53 HCS[1–2] 57 58 HRW 44a HDS 44b 51 55 44c 50 52 49 HD[0–15] 61 HREQ (single host request) HRRQ (double host request) Figure 2-12. Read Timing Diagram, Single Data Strobe HA[0–3] 57 58 56 53 HCS[1–2] 44a HRD 44b 51 55 44a 50 52 49 HD[0–15] 61 HREQ (single host request) HRRQ (double host request) Figure 2-13. Read Timing Diagram, Double Data Strobe MSC8103 Network Digital Signal Processor, Rev. 12 2-20 Freescale Semiconductor AC Timings HA[0–3] 57 58 56 54 HCS[1–2] 57 58 HRW 45 HDS 46 47 48 HD[0–15] 62 HREQ (single host request) HTRQ (double host request) Figure 2-14. Write Timing Diagram, Single Data Strobe HA[0–3] 57 58 56 54 HCS[1–2] 45 HWR 46 48 47 HD[0–15] HREQ (single host request) HTRQ (double host request) Figure 2-15. 62 Write Timing Diagram, Double Data Strobe MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-21 Physical and Electrical Specifications Figure 2-16 shows Host DMA read timing. HREQ (Output) 63 64 44a HACK 44b RX[0–3] Read 51 50 49 52 Data Valid HD[0–15] (Output) Figure 2-16. Host DMA Read Timing Diagram, HPCR[OAD] = 0 Figure 2-17 shows Host DMA write timing. HREQ (Output) 63 64 46 45 HACK TX[0–3] Write 47 48 HD[0–15] (Output) Figure 2-17. Data Valid Host DMA Write Timing Diagram, HPCR[OAD] = 0 MSC8103 Network Digital Signal Processor, Rev. 12 2-22 Freescale Semiconductor AC Timings 2.6.7 CPM Timings Table 2-20. No. CPM Input Characteristics Typical Unit FCC input set-up time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 10 5 ns ns FCC input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 0 3 ns ns SCC/SMC/SPI/I2C input set-up time before low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 20 5 ns ns SCC/SMC/SPI/I2C input hold time after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial clock input) 0 5 ns ns 20 TDM input set-up time before low-to-high serial clock transition 5 ns 21 TDM input hold time after low-to-high serial transition 5 ns 22 PIO/TIMER/DMA input set-up time before low-to-high serial clock transition 10 ns 23 PIO/TIMER/DMA input hold time after low-to-high serial clock transition 3 ns Min Max Unit FCC output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) 0 2 6 18 ns ns SCC/SMC/SPI/I2C output delay after low-to-high clock transition a. internal clock (BRGxO) b. external clock (serial input clock) 0 0 20 30 ns ns 40 TDM output delay after low-to-high serial clock transition 5 15 ns 42 PIO/TIMER/DMA output delay after low-to-high serial clock transition 1 14 ns 39 17 18 19 Note: Characteristic FCC, SCC, SMC, SPI, I2C are non-multiplexed serial interface signals. Table 2-21. No. 41 38 Note: CPM Output Characteristics Characteristic 2 FCC, SCC, SMC, SPI, I C are Non-Multiplexed Serial Interface signals. BRGxO 17a 29a FCC inputs 41a FCC outputs Figure 2-18. FCC Internal Clock Diagram MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-23 Physical and Electrical Specifications Serial input clock 17b 39b FCC inputs 41b FCC outputs Figure 2-19. FCC External Clock Diagram BRGxO 19a 18a SCC/SMC/SPI/I2C inputs 38a SCC/SMC/SPI/I2C outputs Figure 2-20. SCC/SMC/SPI/I2C Internal Clock Diagram Serial input clock 19b 18b SCC/SMC/SPI/I2C inputs 38b SCC/SMCSPI/I2C outputs Figure 2-21. SCC/SMC/SPI/I2C External Clock Diagram Serial input clock 20 21 TDM inputs 40 TDM outputs Figure 2-22. TDM Signal Diagram MSC8103 Network Digital Signal Processor, Rev. 12 2-24 Freescale Semiconductor AC Timings DLLIN 23 22 PIO/TIMER/DMA inputs 42 PIO/TIMER/DMA outputs Figure 2-23. PIO, Timer, and DMA Signal Diagram Note: The timing values refer to minimum system timing requirements. Actual implementation requires conformance to the specific protocol requirements. Refer to Chapter 1 to identify the specific input and output signals associated with the referenced internal controllers and supported communication protocols. For example, FCC1 supports ATM/Utopia operation in slave mode, multi-PHY master direct polling mode, and multi-PHY master multiplexed polling mode and each of these modes supports its own set of signals; the direction (input or output) of some of the shared signal names depends on the selected mode. 2.6.8 JTAG Signals Table 2-22. JTAG Timing All frequencies No. Characteristics Unit Min Max 0.0 40.0 500 TCK frequency of operation MHz 501 TCK cycle time 25.0 — ns 502 TCK clock pulse width measured at 1.6 V 12.5 — ns 503 TCK rise and fall times 0.0 3.0 ns 508 TMS, TDI data set-up time 6.0 — ns 509 TMS, TDI data hold time 3.0 — ns 510 TCK low to TDO data valid 0.0 15.0 ns 511 TCK low to TDO high impedance 0.0 20.0 ns 512 TRST assert time 100.0 — ns 513 TRST set-up time to TCK low 40.0 — ns 501 TCK (Input) VIH 502 502 VM VM VIL 503 Figure 2-24. 503 Test Clock Input Timing Diagram MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-25 Physical and Electrical Specifications TCK (Input) VIH VIL 508 TDI TMS (Input) 509 Input Data Valid 510 TDO (Output) Output Data Valid 511 TDO (Output) 510 TDO (Output) Output Data Valid Figure 2-25. Test Access Port Timing Diagram TCK (Input) 513 TRST (Input) 512 Figure 2-26. TRST Timing Diagram MSC8103 Network Digital Signal Processor, Rev. 12 2-26 Freescale Semiconductor 3 Packaging This chapter provides information about the MSC8103 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8103 is available in a 332-pin lidded flip chip-plastic ball grid array (FC-PBGA). 3.1 FC-PBGA Package Description Figure 3-1 and Figure 3-2 show top and bottom views of the FC-PBGA package, including pinouts. Table 3-1 lists the MSC8103 signals alphabetically by signal name. Connections with multiple names are listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low). Note: The package description in this chapter applies to packages with lead-bearing and lead-free spheres. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-1 Packaging Top View 1 A B IRQ1 C THERM 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 IRQ5 D1 D4 D7 D11 D17 D22 D27 D32 D37 D42 D46 D51 D55 D60 D62 D63 IRQ3 D0 D3 D6 D10 D16 D21 D26 D31 D36 D41 D45 D50 D54 D59 PWE6 DBG BADDR 28 B DP0 IRQ4 D2 D5 D9 D15 D20 D25 D30 D35 D40 D44 D49 D53 D58 D61 DBB BADDR 29 C BADDR D 27 A D EE1 EE0 THERM 2 IRQ2 IRQ6 D8 D14 D19 D24 D29 D34 D39 D43 D48 D52 D57 PWE5 GBL E EE4 EE3 EE2 VDDH VDD VDDH D13 VDDH VDD VDDH VDDH VDD VDDH D47 VDDH D56 PSDA 10 MOD CK1 PSD CAS E F TDO EED EE5 VDD GND IRQ7 GND D18 GND D28 GND D38 GND PSD WE GND VDD PWE7 MOD CK2 BCTL0 F G PA31 TMS TRST TCK VDDH GND D12 GND D23 GND D33 GND PSD VAL GND VDDH VDDH TEA MOD CK3 POE G H PB30 PD31 PC31 PB31 GND TDI GND GND VDD BR ALE PWE4 H J PA29 PD30 PC30 VDD GND GND PA30 K PA28 PD29 PC29 PB29 VDDH GND GND L PA27 PB28 PC28 VDD GND GND PC27 M PB27 PC26 PB26 VDDH GND PA26 PA16 N PC25 PA25 PB25 VDD PC23 GND PD17 CLKIN GND PC6 TSIZ3 P PC24 PA24 PB24 PA23 PB20 GND GND DLL_IN GND PC4 R PC22 SPARE 1 PA22 PB18 PA19 VDDH VDDH VDD VDDH T PB21 PB22 PA20 PA17 PC13 PC14 VCC SYN1 CLK OUT U PA21 PB19 PD18 PD16 NMI RST CONF GND SYN1 V PB23 PD19 PC15 PC12 NMI_ HRESET OUT PA18 PA15 2 3 VDDH VDDH PSDA MUX PGTA PWE3 J GND PWE2 GND VDDH PWE1 PWE0 CS2 K CS6 GND GND VDD CS1 CS3 BCTL1 L A21 A26 GND CS0 CS5 CS7 CS4 M TT1 TT0 A1 VDDH VDDH A28 A30 A31 N GND GND GND GND GND VDD A23 A27 A29 P VDDH VDD VDDH VDD VDDH VDDH A15 A19 A24 A25 R PA12 PC7 PA6 AACK TS A3 VDDH A12 A16 A20 A22 T PA13 PA10 PA8 TBST TT2 A4 A8 A11 A17 A18 U GND SYN PA11 PD7 PA7 ABB BG TSIZ0 TT3 A2 A6 A9 A13 A14 V TEST VCC SYN PA14 PA9 PC5 INT _OUT TSIZ2 TSIZ1 TT4 A0 A5 A7 A10 6 7 8 9 10 11 14 15 16 17 18 03 5 GND 81 4 TA SC 1 PO SRESET RESET M W BADDR BADDR 31 30 SPARE ARTRY 5 12 13 W 19 Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name. Figure 3-1. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Top View MSC8103 Network Digital Signal Processor, Rev. 12 3-2 Freescale Semiconductor FC-PBGA Package Description Bottom View 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 A D63 D62 D60 D55 D51 D46 D42 D37 D32 D27 D22 D17 D11 D7 D4 D1 IRQ5 B BADDR 28 DBG PWE6 D59 D54 D50 D45 D41 D36 D31 D26 D21 D16 D10 D6 D3 D0 IRQ3 C BADDR 29 DBB D61 D58 D53 D49 D44 D40 D35 D30 D25 D20 D15 D9 D5 D2 IRQ4 DP0 D BADDR 27 GBL PWE5 D57 D52 D48 D43 D39 D34 D29 D24 D19 D14 D8 IRQ6 IRQ2 THERM 2 EE0 EE1 D MOD CK1 PSDA 10 D56 VDDH D47 VDDH VDD VDDH VDDH VDD VDDH D13 VDDH VDD VDDH EE2 EE3 EE4 E E PSD CAS 1 A IRQ1 B THERM C 1 F BCTL0 MOD CK2 PWE7 VDD GND PSD WE GND D38 GND D28 GND D18 GND IRQ7 GND VDD EE5 EED TDO F G POE MOD CK3 TEA VDDH VDDH GND PSD VAL GND D33 GND D23 GND D12 GND VDDH TCK TRST TMS PA31 G H PWE4 ALE BR VDD GND GND TDI GND PB31 PC31 PD31 PB30 H J PWE3 PGTA PSDA MUX VDDH VDDH GND TA PA30 GND GND VDD PC30 PD30 PA29 J K CS2 PWE0 PWE1 VDDH GND PWE2 GND GND GND VDDH PB29 PC29 PD29 PA28 K L BCTL1 CS3 CS1 VDD GND GND CS6 PC27 GND GND VDD PC28 PB28 PA27 L M CS4 CS7 CS5 CS0 GND A26 A21 PA16 PA26 GND VDDH PB26 PC26 PB27 M N A31 A30 A28 VDDH VDDH A1 TT0 TT1 TSIZ3 PC6 GND CLKIN PD17 GND PC23 VDD PB25 PA25 PC25 N P A29 A27 A23 VDD GND GND GND GND GND PC4 GND DLL_IN GND GND PB20 PA23 PB24 PA24 PC24 P R A25 A24 A19 A15 VDDH VDDH VDD VDDH VDD VDDH VDDH VDD VDDH VDDH PA19 PB18 PA22 SPARE 1 PC22 R T A22 A20 A16 A12 VDDH A3 TS AACK PA6 PC7 PA12 CLK OUT VCC SYN1 PC14 PC13 PA17 PA20 PB22 PB21 T U A18 A17 A11 A8 A4 TT2 TBST PA8 PA10 PA13 GND SYN1 RST CONF NMI PD16 PD18 PB19 PA21 U V A14 A13 A9 A6 A2 TT3 TSIZ0 BG ABB PA7 PD7 PA11 GND SYN HRESET NMI_ OUT PC12 PC15 PD19 PB23 V A10 A7 A5 A0 TT4 TSIZ1 TSIZ2 INT _OUT PC5 PA9 PA14 VCC SYN TEST PO RESET SRESET PA15 PA18 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 W 19 M SC 81 03 BADDR BADDR 30 31 ARTRY SPARE 5 W 1 Note: Signal names in this figure are the default signals after reset, except for signals C2, C19, D1, D2, D18, E1, F3, H13, H14, and W11 which show the second configuration signal name. Figure 3-2. MSC8103 Flip Chip Plastic Ball Grid Array (FC-PBGA), Bottom Vie MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-3 Packaging Table 3-1. MSC8103 Signal Listing By Name Signal Name Number A0 W15 A1 N14 A2 V15 A3 T14 A4 U15 A5 W16 A6 V16 A7 W17 A8 U16 A9 V17 A10 W18 A11 U17 A12 T16 A13 V18 A14 V19 A15 R16 A16 T17 A17 U18 A18 U19 A19 R17 A20 T18 A21 M13 A22 T19 A23 P17 A24 R18 A25 R19 A26 M14 A27 P18 A28 N17 A29 P19 A30 N18 A31 N19 AACK T12 ABB V11 MSC8103 Network Digital Signal Processor, Rev. 12 3-4 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number ALE H18 ARTRY U12 BADDR27 D19 BADDR28 B19 BADDR29 C19 BADDR30 H14 BADDR31 H13 BCTL0 F19 BCTL1 L19 BG V12 BNKSEL0 E18 BNKSEL1 F18 BNKSEL2 G18 BR H17 BRG1O H3 BRG1O V2 BRG2O J3 BRG2O N7 BRG3O K3 BRG4O L3 BRG5O L7 BRG6O M2 BRG7O N1 BRG8O P1 BTM0 E1 BTM1 F3 CD for FCC1 N10 CD for FCC2 P10 CD/RENA for SCC1 T6 CD/RENA for SCC2 V4 CLK1 H3 CLK2 J3 CLK3 K3 CLK4 L3 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-5 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number CLK5 L7 CLK6 M2 CLK7 N1 CLK8 P1 CLK9 N5 CLK10 R1 CLKIN N8 CLKOUT T8 COL for FCC1 G1 COL for FCC2 M1 CRS for FCC1 J7 CRS for FCC2 M3 CS0 M16 CS1 L17 CS2 K19 CS3 L18 CS4 M19 CS5 M17 CS6 L13 CS7 M18 CTS for FCC1 T10 CTS for FCC2 W10 CTS/CLSN for SCC1 K3 CTS/CLSN for SCC1 V3 CTS/CLSN for SCC2 L3 CTS/CLSN for SCC2 T5 D0 B3 D1 A3 D2 C4 D3 B4 D4 A4 D5 C5 D6 B5 D7 A5 MSC8103 Network Digital Signal Processor, Rev. 12 3-6 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number D8 D6 D9 C6 D10 B6 D11 A6 D12 G7 D13 E7 D14 D7 D15 C7 D16 B7 D17 A7 D18 F8 D19 D8 D20 C8 D21 B8 D22 A8 D23 G9 D24 D9 D25 C9 D26 B9 D27 A9 D28 F10 D29 D10 D30 C10 D31 B10 D32 A10 D33 G11 D34 D11 D35 C11 D36 B11 D37 A11 D38 F12 D39 D12 D40 C12 D41 B12 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-7 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number D42 A12 D43 D13 D44 C13 D45 B13 D46 A13 D47 E14 D48 D14 D49 C14 D50 B14 D51 A14 D52 D15 D53 C15 D54 B15 D55 A15 D56 E16 D57 D16 D58 C16 D59 B16 D60 A16 D61 C17 D62 A17 D63 A18 DACK1 N5 DACK2 N1 DACK3 D5 DACK4 F6 DBB C18 DBG B18 DBREQ D2 DLLIN P8 DP0 C2 DP1 B1 DP2 D4 DP3 B2 MSC8103 Network Digital Signal Processor, Rev. 12 3-8 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number DP4 C3 DP5 A2 DP6 D5 DP7 F6 DRACK1/DONE1 H2 DRACK2/DONE2 J2 DREQ1 R1 DREQ2 P1 DREQ3 C3 DREQ4 A2 EE0 D2 EE1 D1 EE2 E3 EE3 E2 EE4 E1 EE5 F3 EED F2 EXT_BG2 B1 EXT_BG3 C3 EXT_BR2 C2 EXT_BR3 B2 EXT_DBG2 D4 EXT_DBG3 A2 EXT1 H3 EXT2 N5 GBL D18 GND F11 GND F13 GND F15 GND F5 GND F7 GND F9 GND G10 GND G12 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-9 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number GND G14 GND G6 GND G8 GND H15 GND H5 GND H7 GND J14 GND J5 GND J6 GND K13 GND K15 GND K6 GND K7 GND L14 GND L15 GND L5 GND L6 GND M15 GND M5 GND N6 GND N9 GND P11 GND P12 GND P13 GND P14 GND P15 GND P6 GND P7 GND P9 GNDSYN V7 GNDSYN1 U7 H8BIT B16 HA0 D14 HA1 C14 MSC8103 Network Digital Signal Processor, Rev. 12 3-10 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number HA2 B14 HA3 A14 HACK/HACK E16 HCS1/HCS1 D15 HCS2/HCS2 A16 HD0 A10 HD1 G11 HD2 D11 HD3 C11 HD4 B11 HD5 A11 HD6 F12 HD7 D12 HD8 C12 HD9 B12 HD10 A12 HD11 D13 HD12 C13 HD13 B13 HD14 A13 HD15 E14 HDDS C16 HDS/HDS B15 HDSP D16 HPE D1 HRD/HRD C15 HREQ/HREQ A15 HRESET V6 HRRQ/HRRQ E16 HRW C15 HTRQ/HTRQ A15 HWR/HWR B15 INT_OUT W11 IRQ1 B1 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-11 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number IRQ1 D18 IRQ2 C19 IRQ2 D4 IRQ2 V11 IRQ3 B2 IRQ3 C18 IRQ3 H14 IRQ4 C3 IRQ5 A2 IRQ5 H13 IRQ6 D5 IRQ7 F6 IRQ7 W11 L1RSYNC for SI1 TDMA1 T11 L1RSYNC for SI2 TDMB2 K4 L1RSYNC for SI2 TDMC2 P3 L1RSYNC for SI2 TDMD2 P5 L1RXD for SI1 TDMA1 Serial U10 L1RXD for SI2 TDMB2 H1 L1RXD for SI2 TDMC2 M3 L1RXD for SI2 TDMD2 T2 L1RXD0 for SI1 TDMA1 Nibble U10 L1RXD1 for SI1 TDMA1 Nibble T2 L1RXD2 for SI1 TDMA1 Nibble V1 L1RXD3 for SI1 TDMA1 Nibble P3 L1TSYNC for SI1 TDMA1 V10 L1TSYNC for SI2 TDMB2 L2 L1TSYNC for SI2 TDMC2 N3 L1TSYNC for SI2 TDMD2 T1 L1TXD for SI1 TDMA1 Serial W9 L1TXD for SI2 TDMB2 H4 L1TXD for SI2 TDMC2 M1 L1TXD for SI2 TDMD2 V1 L1TXD0 for SI1 TDMA1 Nibble W9 MSC8103 Network Digital Signal Processor, Rev. 12 3-12 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number L1TXD1 for SI1 TDMA1 Nibble P5 L1TXD2 for SI1 TDMA1 Nibble T1 L1TXD3 for SI1 TDMA1 Nibble N3 LIST1 for SI1 R1 LIST1 for SI2 T10 LIST2 for SI1 T6 LIST2 for SI2 N10 LIST3 for SI1 V4 LIST3 for SI2 W10 LIST4 for SI1 T5 LIST4 for SI2 P10 MODCK1 E18 MODCK2 F18 MODCK3 G18 MSNUM0 N2 MSNUM1 P2 MSNUM2 U8 MSNUM3 T9 MSNUM4 V8 MSNUM5 U9 NMI U5 NMI_OUT V5 PA6 T11 PA7 V10 PA8 U10 PA9 W9 PA10 U9 PA11 V8 PA12 T9 PA13 U8 PA14 W8 PA15 W3 PA16 M7 PA17 T4 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-13 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number PA18 W2 PA19 R5 PA20 T3 PA21 U1 PA22 R3 PA23 P4 PA24 P2 PA25 N2 PA26 M6 PA27 L1 PA28 K1 PA29 J1 PA30 J7 PA31 G1 PB18 R4 PB19 U2 PB20 P5 PB21 T1 PB22 T2 PB23 V1 PB24 P3 PB25 N3 PB26 M3 PB27 M1 PB28 L2 PB29 K4 PB30 H1 PB31 H4 PBS0 K18 PBS1 K17 PBS2 K14 PBS3 J19 PBS4 H19 PBS5 D17 MSC8103 Network Digital Signal Processor, Rev. 12 3-14 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number PBS6 B17 PBS7 F17 PC4 P10 PC5 W10 PC6 N10 PC7 T10 PC12 V4 PC13 T5 PC14 T6 PC15 V3 PC22 R1 PC23 N5 PC24 P1 PC25 N1 PC26 M2 PC27 L7 PC28 L3 PC29 K3 PC30 J3 PC31 H3 PD7 V9 PD16 U4 PD17 N7 PD18 U3 PD19 V2 PD29 K2 PD30 J2 PD31 H2 PGPL0 E17 PGPL1 F14 PGPL2 G19 PGPL3 E19 PGPL4 J18 PGPL5 J17 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-15 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number PGTA J18 POE G19 PORESET W5 PPBS J18 PSDA10 E17 PSDAMUX J17 PSDCAS E19 PSDDQM0 K18 PSDDQM1 K17 PSDDQM2 K14 PSDDQM3 J19 PSDDQM4 H19 PSDDQM5 D17 PSDDQM6 B17 PSDDQM7 F17 PSDRAS G19 PSDVAL G13 PSDWE F14 PUPMWAIT J18 PWE0 K18 PWE1 K17 PWE2 K14 PWE3 J19 PWE4 H19 PWE5 D17 PWE6 B17 PWE7 F17 Reserved A17 Reserved A18 Reserved C2 Reserved C17 Reserved C19 Reserved H14 Reserved H13 MSC8103 Network Digital Signal Processor, Rev. 12 3-16 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number RSTCONF U6 RTS for FCC1 J7 RTS for FCC2 L2 RTS/TENA for SCC1 K2 RTS/TENA for SCC2 L2 RX_DV for FCC1 L1 RX_DV for FCC2 H1 RX_ER for FCC1 M6 RX_ER for FCC2 L2 RXADDR0 for FCC1 UTOPIA 8 T6 RXADDR1 for FCC1 UTOPIA 8 V4 RXADDR2 for FCC1 UTOPIA 8 N10 RXADDR2/RXCLAV1 for FCC1 UTOPIA 8 N10 RXADDR3 for FCC1 UTOPIA 8 K2 RXADDR4 for FCC1 UTOPIA 8 U3 RXCLAV for FCC1 UTOPIA 8 M6 RXCLAV0 for FCC1 UTOPIA 8 M6 RXCLAV2 for FCC1 UTOPIA 8 K2 RXCLAV3 for FCC1 UTOPIA 8 V4 RXD for FCC1 transparent/HDLC serial T4 RXD for FCC2 transparent/HDLC serial T1 RXD for SCC1 H2 RXD for SCC2 H4 RXD0 for FCC1 MII/HDLC nibble T4 RXD0 for FCC1 UTOPIA 8 U9 RXD0 for FCC2 MII/HDLC nibble T1 RXD1 for FCC1 MII/HDLC nibble M7 RXD1 for FCC1 UTOPIA 8 V8 RXD1 for FCC2 MII/HDLC nibble P5 RXD2 for FCC1 MII/HDLC nibble W3 RXD2 for FCC1 UTOPIA 8 T9 RXD2 for FCC2 MII/HDLC nibble U2 RXD3 for FCC1 MII/HDLC nibble W8 RXD3 for FCC1 UTOPIA 8 U8 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-17 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number RXD3 for FCC2 MII/HDLC nibble R4 RXD4 for FCC1 UTOPIA 8 W8 RXD5 for FCC1 UTOPIA 8 W3 RXD6 for FCC1 UTOPIA 8 M7 RXD7 for FCC1 UTOPIA 8 T4 RXENB for FCC1 K1 RXPRTY for FCC1 UTOPIA 8 N7 RXSOC for FCC1 L1 SCL R4 SDA U2 SMRXD for SMC1 P10 SMRXD for SMC2 U10 SMSYN for SMC1 V9 SMSYN for SMC2 V10 SMTXD for SMC1 W10 SMTXD for SMC2 W9 SMTXD for SMC2 V3 SPARE1 R2 SPARE5 U11 SPICLK U3 SPIMISO U4 SPIMOSI N7 SPISEL V2 SRESET W4 TA J13 TBST U13 TC0 E18 TC1 F18 TC2 G18 TCK G4 TDI H6 TDO F1 TEA G17 TEST W6 MSC8103 Network Digital Signal Processor, Rev. 12 3-18 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number TGATE1 H3 TGATE2 L7 THERM1 C1 THERM2 D3 TIN1/TOUT2 L3 TIN2 K3 TIN3/TOUT4 P1 TIN4 N1 TMCLK M2 TMS G2 TOUT1 J3 TOUT3 M2 TRST G3 TS T13 TSIZ0 V13 TSIZ1 W13 TSIZ2 W12 TSIZ3 N11 TT0 N13 TT1 N12 TT2 U14 TT3 V14 TT4 W14 TX_EN for FCC1 MII K1 TX_EN for FCC2 MII K4 TX_ER for FCC1 MII J1 TX_ER for FCC2 MII H4 TXADDR0 for FCC1 UTOPIA 8 V3 TXADDR1 for FCC1 UTOPIA 8 T5 TXADDR2 for FCC1 UTOPIA 8 T10 TXADDR2 for FCC1 UTOPIA 8 T10 TXADDR3 for FCC1 UTOPIA 8 V9 TXADDR4 for FCC1 UTOPIA 8 V2 TXCLAV for FCC1 UTOPIA 8 J7 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-19 Packaging Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number TXCLAV0 for FCC1 UTOPIA 8 J7 TXCLAV1 for FCC1 UTOPIA 8 T10 TXCLAV2 for FCC1 UTOPIA 8 V9 TXCLAV3 for FCC1 UTOPIA 8 V2 TXD for FCC1 transparent/HDLC serial W2 TXD for FCC2 transparent/HDLC serial T2 TXD for SCC1 J2 TXD for SCC2 H1 TXD0 for FCC1 MII/HDLC nibble W2 TXD0 for FCC1 UTOPIA 8 N2 TXD0 for FCC2 MII/HDLC nibble T2 TXD1 for FCC1 MII/HDLC nibble R5 TXD1 for FCC1 UTOPIA 8 P2 TXD1 for FCC2 MII/HDLC nibble V1 TXD2 for FCC1 MII/HDLC nibble T3 TXD2 for FCC1 UTOPIA 8 P4 TXD2 for FCC2 MII/HDLC nibble P3 TXD3 for FCC1 MII/HDLC nibble U1 TXD3 for FCC1 UTOPIA 8 R3 TXD3 for FCC2 MII/HDLC nibble N3 TXD4 for FCC1 UTOPIA 8 U1 TXD5 for FCC1 UTOPIA 8 T3 TXD6 for FCC1 UTOPIA 8 R5 TXD7 for FCC1 UTOPIA 8 W2 TXENB for FCC1 G1 TXPRTY for FCC1 UTOPIA 8 U4 TXSOC for FCC1 J1 VCCSYN W7 VCCSYN1 T7 VDD E12 VDD E5 VDD E9 VDD F16 VDD F4 MSC8103 Network Digital Signal Processor, Rev. 12 3-20 Freescale Semiconductor FC-PBGA Package Description Table 3-1. MSC8103 Signal Listing By Name (Continued) Signal Name Number VDD H16 VDD J4 VDD L16 VDD L4 VDD N4 VDD P16 VDD R11 VDD R13 VDD R8 VDDH E10 VDDH E11 VDDH E13 VDDH E15 VDDH E4 VDDH E6 VDDH E8 VDDH G15 VDDH G16 VDDH G5 VDDH J15 VDDH J16 VDDH K16 VDDH K5 VDDH M4 VDDH N15 VDDH N16 VDDH R10 VDDH R12 VDDH R14 VDDH R15 VDDH R6 VDDH R7 VDDH R9 VDDH T15 MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-21 Packaging Table 3-2. MSC8103 Signal Listing by Pin Designator Number Signal Name A2 IRQ5 / DP5 / DREQ4 / EXT_DBG3 A3 D1 A4 D4 A5 D7 A6 D11 A7 D17 A8 D22 A9 D27 A10 D32 / HD0 A11 D37 / HD5 A12 D42 / HD10 A13 D46 / HD14 A14 D51 / HA3 A15 D55 / HREQ / HTRQ A16 D60 / HCS2 A17 D62 / Reserved A18 D63 / Reserved B1 IRQ1 / DP1 / EXT_BG2 B2 IRQ3 / DP3 / EXT_BR3 B3 D0 B4 D3 B5 D6 B6 D10 B7 D16 B8 D21 B9 D26 B10 D31 B11 D36 / HD4 B12 D41 / HD9 B13 D45 / HD13 B14 D50 / HA2 B15 D54 / HDS / HWR B16 D59 / H8BIT B17 PWE6 / PSDDQM6 / PBS6 B18 DBG B19 BADDR28 C1 THERM1 C2 Reserved / DP0 / EXT_BR2 C3 IRQ4 / DP4 / DREQ3 / EXT_BG3 MSC8103 Network Digital Signal Processor, Rev. 12 3-22 Freescale Semiconductor FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name C4 D2 C5 D5 C6 D9 C7 D15 C8 D20 C9 D25 C10 D30 C11 D35 / HD3 C12 D40 / HD8 C13 D44 / HD12 C14 D49 / HA1 C15 D53 / HRW / HRD C16 D58 / HDDS C17 D61 C18 DBB / IRQ3 C19 BADDR29 / IRQ2 D1 HPE / EE1 D2 DBREQ / EE0 D3 THERM2 D4 IRQ2 / DP2 / EXT_DBG2 D5 IRQ6 / DP6 / DACK3 D6 D8 D7 D14 D8 D19 D9 D24 D10 D29 D11 D34 / HD2 D12 D39 / HD7 D13 D43 / HD11 D14 D48 / HA0 D15 D52 / HCS1 D16 D57 / HDSP D17 PWE5 / PSDDQM5 / PBS5 D18 IRQ1 / GBL D19 BADDR27 E1 BTM0 / EE4 E2 EE3 E3 EE2 E4 VDDH MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-23 Packaging Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name E5 VDD E6 VDDH E7 D13 E8 VDDH E9 VDD E10 VDDH E11 VDDH E12 VDD E13 VDDH E14 D47 / HD15 E15 VDDH E16 D56 / HACK / HRRQ E17 PSDA10 / PGPL0 E18 MODCK1 / TC0 / BNKSEL0 E19 PSDCAS / PGPL3 F1 TDO F2 EED F3 BTM1 / EE5 F4 VDD F5 GND F6 IRQ7 / DP7 / DACK4 F7 GND F8 D18 F9 GND F10 D28 F11 GND F12 D38 / HD6 F13 GND F14 PSDWE / PGPL1 F15 GND F16 VDD F17 PWE7 / PSDDQM7 / PBS7 F18 MODCK2 / TC1 / BNKSEL1 F19 BCTL0 G1 PA31 / FCC1:UTOPIA8:TXENB / FCC1:MII:COL G2 TMS G3 TRST G4 TCK G5 VDDH MSC8103 Network Digital Signal Processor, Rev. 12 3-24 Freescale Semiconductor FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name G6 GND G7 D12 G8 GND G9 D23 G10 GND G11 D33 / HD1 G12 GND G13 PSDVAL G14 GND G15 VDDH G16 VDDH G17 TEA G18 MODCK3 / TC2 / BNKSEL2 G19 POE / PSDRAS / PGPL2 H1 PB30 / FCC2:MII:RX_DV / SCC2:TXD / TDBM2:L1RXD H2 PD31 / SCC1:RXD / DRACK1 / DONE1 H3 PC31 / BRG1O / CLK1 / TGATE1 H4 PB31 / FCC2:MII:TX_ER / SCC2:RXD / TDMB2:L1TXD H5 GND H6 TDI H7 GND H13 Reserved / BADDR31 / IRQ5 H14 Reserved / BADDR30 / IRQ3 H15 GND H16 VDD H17 BR H18 ALE H19 PWE4 / PSDDQM4 / PBS4 J1 PA29 / FCC1:UTOPIA8:TXSOC / FCC1:MII:TX_ER J2 PD30 / SCC1:TXD / DMA:DRACK2/DONE2 J3 PC30 / EXT1 / BRG2O / CLK2 / TOUT1 J4 VDD J5 GND J6 GND J7 PA30 / FCC1:UTOPIA8:TXCLAV / FCC1:UTOPIA8:TXCLAV0 / FCC1:MII:CRS / FCC1:HDLC and transparent:RTS J13 TA J14 GND J15 VDDH MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-25 Packaging Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name J16 VDDH J17 PSDAMUX / PGPL5 J18 PGTA / PUPMWAIT / PPBS / PGPL4 J19 PWE3 / PSDDQM3 / PBS3 K1 PA28 / FCC1:UTOPIA8:RXENB / FCC1:MII:TX_EN K2 PD29 / FCC1:UTOPIA8:RXADDR3 / FCC1:UTOPIA8:RXCLAV2 / SCC1:RTS/TENA K3 PC29 / SCC1:CTS / SCC1:CLSN / BRG3O / CLK3 / TIN2 K4 PB29 / FCC2:MII:TX_EN / TDMB2:L1RSYNC K5 VDDH K6 GND K7 GND K13 GND K14 PWE2 / PSDDQM2 / PBS2 K15 GND K16 VDDH K17 PWE1 / PSDDQM1 / PBS1 K18 PWE0 / PSDDQM0 / PBS0 K19 CS2 L1 PA27 / FCC1:UTOPIA8:RXSOC / FCC1:MII:RX_DV L2 PB28 / FCC2:RX_ER / FCC2:HDLC:RTS / SCC2:RTS/TENA / TDMB2:L1TSYNC L3 PC28 / SCC2:CTS/CLSN / BRG4O / CLK4 / TIN1/TOUT2 L4 VDD L5 GND L6 GND L7 PC27 / CLK5 / BRG5O / TGATE2 L13 CS6 L14 GND L15 GND L16 VDD L17 CS1 L18 CS3 L19 BCTL1 M1 PB27 / FCC2:MII:COL / TDMC2:L1TXD M2 PC26 / TMCLK / BRG6O / CLK6 / TOUT3 M3 PB26 / FCC2:MII:CRS / TDMC2:L1RXD M4 VDDH M5 GND M6 PA26 / FCC1:UTOPIA8:RXCLAV / FCC1:UTOPIA8:RXCLAV0 / FCC1:MII:RX_ER MSC8103 Network Digital Signal Processor, Rev. 12 3-26 Freescale Semiconductor FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name M7 PA16 / FCC1:UTOPIA8:RXD6 / FCC1:MII and HDLC nibble:RXD1 M13 A21 M14 A26 M15 GND M16 CS0 M17 CS5 M18 CS7 M19 CS4 N1 PC25 / DMA:DACK2 / BRG7O / CLK7 / TIN4 N2 PA25 / FCC1:UTOPIA8:TXD0 / SDMA:MSNUM0 N3 PB25 / FCC2:MII and HDLC nibble:TXD3 / TDMA1:nibble:L1TXD3 / TDMC2:L1TSYNC N4 VDD N5 PC23 / EXT2 / DMA:DACK1 / CLK9 N6 GND N7 PD17 / FCC1:UTOPIA8:RXPRTY / SPI:SPIMOSI / BRG2O N8 CLKIN N9 GND N10 PC6 / FCC1:UTOPIA8:RXADDR2 / FCC1:UTOPIA8:RXADDR2/RXCLAV1 / FCC1:CD / SI2:LIST2 N11 TSIZ3 N12 TT1 N13 TT0 N14 A1 N15 VDDH N16 VDDH N17 A28 N18 A30 N19 A31 P1 PC24 / DMA:DREQ2 / BRG8O / CLK8 / TIN3/TOUT4 P2 PA24 / FCC1:UTOPIA8:TXD1 / SDMA:MSNUM1 P3 PB24 / FCC2:MII and HDLC nibble:TXD2 / TDMA1:nibble:L1RXD3 / TDMC2:L1RSYNC P4 PA23 / FCC1:UTOPIA8:TXD2 P5 PB20 / FCC2:MII and HDLC nibble:RXD1 / TDMA1:nibble:L1TXD1 / TDMD2:L1RSYNC P6 GND P7 GND P8 DLLIN P9 GND MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-27 Packaging Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name P10 PC4 / FCC2:CD / SMC1:SMRXD / SI2:LIST4 P11 GND P12 GND P13 GND P14 GND P15 GND P16 VDD P17 A23 P18 A27 P19 A29 R1 PC22 / SI1:LIST1 / DREQ1 / CLK10 R2 SPARE1 R3 PA22 / FCC1:UTOPIA8:TXD3 R4 PB18 / FCC2:MII and HDLC nibble:RXD3 / I2C:SCL R5 PA19 / FCC1:UTOPIA8:TXD6 / FCC1:MII and HDLC nibble:TXD1 R6 VDDH R7 VDDH R8 VDD R9 VDDH R10 VDDH R11 VDD R12 VDDH R13 VDD R14 VDDH R15 VDDH R16 A15 R17 A19 R18 A24 R19 A25 T1 PB21 / FCC2:MII and HDLC nibble:RXD0 / FCC2:transparent and HDLC serial:RXD /TDMA1:nibble:L1TXD2 / TDMD2:L1TSYNC T2 PB22 / FCC2:MII and HDLC nibble TXD0 / FCC2:transparent and HDLC serial TXD /TDMA1:nibble L1RXD1 / TDMD2:L1RXD T3 PA20 / FCC1:UTOPIA8 TXD5 / FCC1:MII and HDLC nibble TXD2 T4 PA17 / FCC1:UTOPIA8 RXD7 / FCC1:MII and HDLC nibble RXD0 / FCC1:transparent and HDLC serial RXD T5 PC13 / FCC1:UTOPIA8:TXADDR1 / SCC2:CTS/CLSN / SI1:LIST4 T6 PC14 / FCC1:UTOPIA8:RXADDR0 / SCC1:CD/RENA / SI1:LIST2 T7 VCCSYN1 MSC8103 Network Digital Signal Processor, Rev. 12 3-28 Freescale Semiconductor FC-PBGA Package Description Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name T8 CLKOUT T9 PA12 / FCC1:UTOPIA8:RXD2 / SDMA:MSNUM3 T10 PC7 / FCC1:UTOPIA8:TXADDR2 / FCC1:UTOPIA8:TXADDR2/TXCLAV1 / FCC1:CTS / SI1:LIST1 T11 PA6 / TDMA1:L1RSYNC T12 AACK T13 TS T14 A3 T15 VDDH T16 A12 T17 A16 T18 A20 T19 A22 U1 PA21 / FCC1:TXD4 / FCC1:MII and HDLC nibble TXD3 U2 PB19 / FCC2:MII and HDLC nibble RXD2 / I2C:SDA U3 PD18 / FCC1:UTOPIA8:RXADDR4 / FCC1:UTOPIA8:RXCLAV3 / SPI:SPICLK U4 PD16 / FCC1:UTOPIA8:TXPRTY / SPI:SPIMISO U5 NMI U6 RSTCONF U7 GNDSYN1 U8 PA13 / FCC1:UTOPIA8:RXD3 / SDMA:MSNUM2 U9 PA10 / FCC1:UTOPIA8:RXD0 / SDMA:MSNUM5 U10 PA8 / SMC2:SMRXD / TDMA1:serial L1RXD / TDMA1:nibble L1RXD0 U11 SPARE5 U12 ARTRY U13 TBST U14 TT2 U15 A4 U16 A8 U17 A11 U18 A17 U19 A18 V1 PB23 / FCC2:MII and HDLC nibble:TXD1 / TDMA1:nibble:L1RXD2 / TDMD2:L1TXD V2 PD19 / FCC1:UTOPIA8:TXADDR4 / FCC1:UTOPIA:TXCLAV3 / SPI:SPISEL / BRG1O V3 PC15 / FCC1:UTOPIA8:TXADDR0 / SCC1:CTS/CLSN / SMC2:SMTXD V4 PC12 / FCC1:UTOPIA8:RXADDR1 / SCC2:CD/RENA / SI1:LIST3 V5 NMI_OUT V6 HRESET MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-29 Packaging Table 3-2. MSC8103 Signal Listing by Pin Designator (Continued) Number Signal Name V7 GNDSYN V8 PA11 / FCC1:UTOPIA8:RXD1 / SDMA:MSNUM4 V9 PD7 / FCC1:UTOPIA8:TXADDR3 / FCC1:UTOPIA8:TXCLAV2 / SMC1:SMSYN V10 PA7 / SMC2:SMSYN / TDMA1:L1TSYNC V11 ABB / IRQ2 V12 BG V13 TSIZ0 V14 TT3 V15 A2 V16 A6 V17 A9 V18 A13 V19 A14 W2 PA18 / FCC1:UTOPIA8:TXD7 / FCC1:MII and HDLC nibble:TXD0 / FCC1:transparent and HDLC serial:TXD W3 PA15 / FCC1:UTOPIA8:RXD5 / FCC1:MII and HDLC nibble:RXD2 W4 SRESET W5 PORESET W6 TEST W7 VCCSYN W8 PA14 / FCC1:UTOPIA8 RXD4 / FCC1:MII and HDLC nibble:RXD3 W9 PA9 / SMC2:SMTXD / TDMA1:serial:L1TXD /TDMA1:nibble:L1TXD0 W10 PC5 / FCC2:CTS / SMC1:SMTXD / SI2:LIST3 W11 IRQ7 / INT_OUT W12 TSIZ2 W13 TSIZ1 W14 TT4 W15 A0 W16 A5 W17 A7 W18 A10 MSC8103 Network Digital Signal Processor, Rev. 12 3-30 Freescale Semiconductor Lidded FC-PBGA Package Mechanical Drawing 3.2 Lidded FC-PBGA Package Mechanical Drawing . Notes: 1. Dimensioning and tolerancing per ASME Y14.5M–1994. 2. Dimensions in millimeters. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Primary Datum A and the seating plane are defined by the spherical crowns of the solder balls. CASE 1473-01 Figure 3-3. Case 1473-01 Mechanical Information, 332-pin Lidded FC-PBGA Package MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-31 Packaging MSC8103 Network Digital Signal Processor, Rev. 12 3-32 Freescale Semiconductor 4 Design Considerations This chapter includes design and layout guidelines for manufacturing boards using the MSC8103. 4.1 Thermal Design Considerations The average chip-junction temperature, TJ, in °C can be obtained from the following: TJ = TA + (PD • θJA) Equation 1 where TA = ambient temperature °C θJA = package thermal resistance, junction to ambient, °C/W PD = PINT + PI/O in W PINT = IDD × VDD in W—chip internal power PI/O = power dissipation on output pins in W—user determined The user should set TA and PD such that TJ does not exceed the maximum operating conditions. In case TJ is too high, the user should either lower the ambient temperature or the power dissipation of the chip. 4.2 Electrical Design Considerations The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn, VDDH can exceed VDD/VCCSYN by more than 3.3 V during power-on reset, but for no more than 100 ms. VDDH should not exceed VDD/VCCSYN by more than 2.1 V during normal operation. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. Therefore the recommendation is to use “bootstrap” diodes between the power rails, as shown in Figure 4-1. 3.3 V (VDDH) I/O Power MUR420 MUR420 MUR420 Core/PLL Supply Figure 4-1. MUR420 1.6 V (VDD/VCCSYN) Bootstrap Diodes for Power-Up Sequencing MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 4-1 Design Considerations Select the bootstrap diodes such that a nominal VDD/VCCSYN is sourced from the VDDH power supply until the VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in series; each has a forward voltage (VF) of 0.6 V at high currents, so these diodes provide a 2.4 V drop, maintaining 0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be reverse biased with negligible leakage current. The VF should be effective at the current levels required by the processor. Do not use diodes with a nominal VF that drops too low at high current. 4.3 Power Considerations The internal power dissipation consists of three components: PINT = PCORE + PSIU + PCPM Power dissipation depends on the operating frequency of the different portions of the chip. Table 2-5 provides typical power values at the specified operating frequencies. To determine the typical power dissipation for a given set of frequencies, use the following equations: PCORE (f) = ((PCORE – PLCO)/fCORE) × fCOREA + PLCO PCPM (f) = ((PCPM – PLCP)/fCPM) × fCPMA + PLCP PSIU (f) = ((PSIU – PLSI)/fSIU) × fSIUA + PLSI Where: • fCORE is the core frequency, fSIU is the SIU frequency, and fCPM is the CPM frequency specified in Table 2-5 in MHz • fCOREA is the actual core frequency, FSIUA is the actual SIU frequency, and FCPMA is the actual CPM frequency in MHz • PLCO, PLSI, and PLCP are the leakage power values specified in Table 2-5 • All power numbers are in mW • Power consumption is assumed to be linear with frequency. The first part of each equation computes a mw/MHz value that is then scaled based on the actual frequency used. To determine a total power dissipation in a specific application, you must add the power values derived from the above set of equations to the value derived for I/O power consumption using the following equation for each output pin: P = C × VDDH2 × f × 10–3 Equation 2 Where: P = power in mW, C = load capacitance in pF, f = output switching frequency in MHz. For an application in which external data memory is used in a 32-bit single bus mode and no other outputs are active, the core runs at 200 MHz, the CPM runs at 100 MHz and the SIU runs at 50 MHz, power dissipation is calculated as follows: Assumptions: • External data memory is accessed every second cycle with 10% of address pins switching. • External data memory writes occurs once every eight cycles with 50% of data pins switching. • Each address and data pin has a 30 pF total load at the pin. • The application operates at VDDH = 3.3 V. MSC8103 Network Digital Signal Processor, Rev. 12 4-2 Freescale Semiconductor Layout Practices Since the address pins switch once at every second cycle, the address pins frequency is a quarter of the bus frequency (that is, 25 MHz). For the same reason the data pins frequency is 3.125 MHz. Table 4-1. Power Dissipation Pins Number of Pins Switching ×C × VDDH2 × f × 10–3 Power in mW Address Data, HRD, HRW CLKOUT 4 34 1 × 30 × 30 × 30 × 3.32 × 3.32 × 3.32 × 12.5 × 10–3 × 3. 125 × 10–3 × 50 × 10–3 16.25 34.75 16 67 Total PI/O Calculating internal power (from Table 2-5 values): PCORE (200) = ((PCORE – PLCO)/300) × 200 + PLCO =((450 – 3) / 300 × 200 + 3 = 301 PCPM (100) = ((PCPM – PLCP) / 200) × 100 + PLCP = ((320 – 6) / 200) × 100 + 6 = 163 PSIU (50) = ((PSIU – PLSI) / 100) × 50 + PLSI = ((80 – 2) / 100) × 50 + 2 = 41 PINT = PCORE(200) + PCPM(100) + PSIU(50) = 301 + 163 + 41 = 505 PD = PINT + PI/O = 505 + 67 = 572 Maximum allowed ambient temperature is: TA = TJ – (PD × θJA) 4.4 Layout Practices Each VCC and VDD pin on the MSC8103 should be provided with a low-impedance path to the board’s power supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MSC8103 have fast rise and fall times. Printed circuit board (PCB) trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There are 2 pairs of PLL supply pins: VCCSYN-GNDSYN and VCCSYN1-GNDSYN1. Each pair supplies one PLL. To ensure internal clock stability, filter the power to the VCCSYN and VCCSYN1 inputs with a circuit similar to the one in Figure 4-2. To filter as much noise as possible, place the circuit as close as possible to VCCSYN and VCCSYN1. The 0.01-µF capacitor should be closest to VCCSYN and VCCSYN1, followed by the 10-µF capacitor, the 10-nH inductor, and finally the 10-Ω resistor to VDD. These traces should be kept short and direct. MSC8103 Network Digital Signal Processor, Rev. 12 Freescale Semiconductor 4-3 Design Considerations GNDSYN and GNDSYN1 should be provided with an extremely low impedance path to ground and should be bypassed to VCCSYN and VCCSYN1, respectively, by a 0.01-µF capacitor located as close as possible to the chip package. The user should also bypass GNDSYN and GNDSYN1 to VCCSYN and VCCSYN1 with a 0.01-µF capacitor as closely as possible to the chip package VCCSYN VDD 10Ω 10nH 10 µF Figure 4-2. 0.01 µF VCCSYN and VCCSYN1 Bypass MSC8103 Network Digital Signal Processor, Rev. 12 4-4 Freescale Semiconductor Ordering Information For product availability, consult a Freescale Semiconductor sales office or authorized distributor. Part MSC8103 Supply Voltage Package Type 1.6 V core 3.3 V I/O Lidded Flip Chip Plastic Ball Grid Array (FC-PBGA) Pin Count Mask Set Sphere Type Core Frequency (MHz) 332 2K87M Pb-bearing 275 MSC8103M1100F Pb-free 275 MSC8103VT1100F Pb-bearing 300 MSC8103M1200F Pb-free 300 MSC8103VT1200F Order Number How to Reach Us: Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 010 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 +1-800 441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com MSC8103 Rev. 12 8/2005 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™, the Freescale logo, and StarCore are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2001, 2008.