Freescale Semiconductor
Data Sheet
Document Number: MSC8157E
Rev. 2, 12/2013
MSC8157E
Six-Core Digital Signal
Processor with Security
• Six StarCore SC3850 DSP subsystems, each with an SC3850 DSP
core, 32 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,
unified 512 Kbyte L2 cache configurable as M2 memory in
64 Kbyte increments, memory management unit (MMU),
extended programmable interrupt controller (EPIC), two
general-purpose 32-bit timers, debug and profiling support,
low-power Wait, Stop, and power-down processing modes, and
ECC/EDC support.
• Chip-level arbitration and switching system (CLASS) that
provides full fabric non-blocking arbitration between the cores
and other initiators and the M2 memory, shared M3 memory,
DDR SRAM controller, device configuration control and status
registers, MAPLE-B, and other targets.
• 3072 Kbyte 128-bit wide M3 memory, 2048 Kbytes of which can
be turned off to save power.
• 96 Kbyte boot ROM.
• Three input clocks (one global and two differential).
• Six PLLs (three global, two Serial RapidIO, one DDR PLLs).
• Second generation Multi-Accelerator Platform Engine for
Baseband (MAPLE-B2) with a second generation programmable
system interface (PSIF2); Turbo encoding and decoding; Viterbi
decoding; FFT/iFFT and DFT/iDFT processing; downlink chip
rate processing; CRC processing and insertion; equalization
processing and matrix inversion; uplink batch and fast processing.
Some MAPLE-B2 processors can be disabled when not required
to reduce overall power consumption.
• Security Engine (SEC) optimized to process all the algorithms
associated with IPSec, IKE, SSL/TLS, 3GPP, and LTE using 4
crypto-channels with multi-command descriptor chains,
integrated controller for assignment of the eight execution units
(PKEU, DEU, AESU, AFEU, MDEU, KEU, SNOW, and the
random number generator (RNG), and XOR engine to accelerate
parity checking for RAID storage applications.
• One DDR controllers with up to a 667 MHz clock (1333 MHz
data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in
up to four banks (two per controller) and support for DDR3.
• DMA controller with 32 unidirectional channels supporting 16
memory-to-memory channels with up to 1024 buffer descriptors
per channel, and programmable priority, buffer, and multiplexing
configuration. It is optimized for DDR SDRAM.
© 2011–2013 Freescale Semiconductor, Inc.
FC-PBGA–783
29 mm × 29 mm
• High-speed serial interface with a 10-lane SerDes PHY that
supports two Serial RapidIO interfaces, one PCI Express
interface, six CPRI lanes, and two SGMII interfaces
(multiplexed). The Serial RapidIO interfaces support x1/x2/x4
operation up to 5 Gbaud with an enhanced messaging unit
(eMSG) and two DMA units. The PCI Express controller supports
32- and 64-bit addressing, x1/x2/x4 link. The six CPRI controllers
can support six lanes up to 6.144 Gbaud.
• QUICC Engine technology subsystem with dual RISC
processors, 48 Kbyte multi-master RAM, 48 Kbyte instruction
RAM, supporting two communication controllers for two Gigabit
Ethernet interfaces (RGMII or SGMII), to offload scheduling
tasks from the DSP cores, and an SPI.
• I/O Interrupt Concentrator consolidates all chip maskable
interrupt and non-maskable interrupt sources and routes then to
INT_OUT/CP_TX_INT, NMI_OUT/CP_RX_INT, and the cores.
• UART that permits full-duplex operation with a bit rate of up to
6.25 Mbps.
• Two general-purpose 32-bit timers for RTOS support per SC3850
core, four timer modules with four 16-bit fully programmable
timers, two timer modules with four 32-bit fully programmable
timers; and eight software watchdog timers (SWT).
• Eight programmable hardware semaphores.
• Up to 32 virtual interrupts and a virtual NMI asserted by simple
write access.
• I2C interface.
• Up to 32 GPIO ports, sixteen of which can be configured as
external interrupts.
• Boot interface options include Ethernet, Serial RapidIO interface,
I2C, and SPI.
• Supports IEEE Std. 1149.6 JTAG interface
• Low power CMOS design, with low-power standby and
power-down modes, and optimized power-management circuitry.
• 45 nm SOI CMOS technology.
Table of Contents
1
2
3
4
5
6
Pin Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 FC-PBGA Ball Layout Diagram . . . . . . . . . . . . . . . . . . . .3
1.2 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
2.2 Recommended Operating Conditions . . . . . . . . . . . . . .40
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .41
2.4 CLKIN/MCLKIN Requirements . . . . . . . . . . . . . . . . . . .41
2.5 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .41
2.6 AC Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . .54
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .73
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
MSC8157E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 2
MSC8157E FC-PBGA Package, Top View . . . . . . . . . . . 3
Differential Voltage Definitions for Transmitter/Receiver 43
Receiver of SerDes Reference Clocks . . . . . . . . . . . . . 44
SerDes Transmitter and Receiver Reference Circuits. . 45
Differential Reference Clock Input DC Requirements
(External DC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7. Differential Reference Clock Input DC Requirements
(External AC-Coupled) . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 8. Single-Ended Reference Clock Input DC Requirements 47
Figure 9. DDR3 SDRAM Interface Input Timing Diagram . . . . . . 55
Figure 10.MCK to MDQS Timing . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 11.DDR SDRAM Output Timing . . . . . . . . . . . . . . . . . . . . . 57
Figure 12.DDR3 Controller Bus AC Test Load. . . . . . . . . . . . . . . . 57
Figure 13.DDR3 SDRAM Differential Timing Specifications . . . . . 57
Figure 14.Differential Measurement Points for Rise and Fall Time 59
Figure 15.Single-Ended Measurement Points for Rise and Fall Time
Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16.Test Measurement Load . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 17.Single Frequency Sinusoidal Jitter Limits for Data Rates for
3.125 Gbps and Below . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 18.Single Frequency Sinusoidal Jitter Limits for Data Rate 5.0
Gbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 19.SGMII AC Test/Measurement Load . . . . . . . . . . . . . . . . 66
Figure 20.Single Frequency Sinusoidal Jitter Limits for Baud Rate
Y.
SD_[A–J]_TX or
SD_[A–J]_RX
X Volts
Vcm = (X + Y)/2
SD_[A–J]_TX or
SD_[A–J]_RX
Y Volts
Differential Swing, VID or VOD = X – Y
Differential Peak Voltage, VDIFFp = |X – Y|
Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)
Figure 3. Differential Voltage Definitions for Transmitter/Receiver
Using this waveform, the definitions are listed in Table 10. To simplify the illustration, the definitions assume that the SerDes
transmitter and receiver operate in a fully symmetrical differential signaling environment.
Table 10. Differential Signal Definitions
Term
Definition
Single-Ended Swing
The transmitter output signals and the receiver input signals SD[A–J]_TX, SD_[A–J]_TX,
SD_[A–J]_RX and SD_[A–J]_RX each have a peak-to-peak swing of X – Y volts. This is also referred
to as each signal wire’s single-ended swing.
Differential Output Voltage, VOD (or
Differential Output Swing):
The differential output voltage (or swing) of the transmitter, VOD, is defined as the difference of the two
complimentary output voltages: VSD_[A–J]_TX – VSD[A–J]_TX. The VOD value can be either positive or
negative.
Differential Input Voltage, VID (or
Differential Input Swing)
The differential input voltage (or swing) of the receiver, VID, is defined as the difference of the two
complimentary input voltages: VSD_[A–J]_RX – VSD_[A–J]_RX. The VID value can be either positive or
negative.
Differential Peak Voltage, VDIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal is
defined as the differential peak voltage, VDIFFp = |X– Y| volts.
Differential Peak-to-Peak, VDIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter output
signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
VDIFFp-p = 2 × VDIFFp = 2 × |(A – B)| volts, which is twice the differential swing in amplitude, or twice
of the differential peak. For example, the output differential peak-peak voltage can also be calculated
as VTX-DIFFp-p = 2 × |VOD|.
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Electrical Characteristics
Table 10. Differential Signal Definitions (continued)
Term
Definition
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SD_[A–J]_TX, for
example) from the non-inverting signal (SD_[A–J]_TX, for example) within a differential pair. There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
waveform is not referenced to ground. Refer to Figure 3 as an example for differential waveform.
Common Mode Voltage, Vcm
The common mode voltage is equal to half of the sum of the voltages between each conductor of a
balanced interchange circuit and ground. In this example, for SerDes output,
Vcm_out = (VSD_[A–J]_TX + VSD_[A–J]_TX) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
complimentary output voltages within a differential pair. In a system, the common mode voltage may
often differ from one component’s output to the other’s input. It may be different between the receiver
input and driver output circuits within the same component. It is also referred to as the DC offset on
some occasions.
To illustrate these definitions using real values, consider the example of a current mode logic (CML) transmitter that has a
common mode voltage of 2.25 V and outputs, TD and TD. If these outputs have a swing from 2.0 V to 2.5 V, the peak-to-peak
voltage swing of each signal (TD or TD) is 500 mV p-p, which is referred to as the single-ended swing for each signal. Because
the differential signaling environment is fully symmetrical in this example, the transmitter output differential swing (VOD) has
the same amplitude as each signal single-ended swing. The differential output signal ranges between 500 mV and –500 mV. In
other words, VOD is 500 mV in one phase and –500 mV in the other phase. The peak differential voltage (VDIFFp) is 500 mV.
The peak-to-peak differential voltage (VDIFFp-p) is 1000 mV p-p.
2.5.2.2
SerDes Reference Clock Receiver Characteristics
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by the corresponding
SerDes lanes. The SerDes reference clock inputs are SD_REF_CLK1/SD_REF_CLK1 or SD_REF_CLK2/SD_REF_CLK2.
Figure 4 shows a receiver reference diagram of the SerDes reference clocks.
50 Ω
SD_REF_CLK[1–2]
Input
Amp
SD_REF_CLK[1–2]
50 Ω
Figure 4. Receiver of SerDes Reference Clocks
The characteristics of the clock signals are as follows:
•
•
•
The supply voltage requirements for VDDSXC are as specified in Table 4.
The SerDes reference clock receiver reference circuit structure is as follows:
— The SD_REF_CLK[1–2] and SD_REF_CLK[1–2] are internally AC-coupled differential inputs as shown in
Figure 4. Each differential clock input (SD_REF_CLK[1–2] or SD_REF_CLK[1–2] has on-chip 50-Ω
termination to SXCVSS followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
— The SerDes reference clock input can be either differential or single-ended. Refer to the differential mode and
single-ended mode descriptions below for detailed requirements.
The maximum average current requirement also determines the common mode voltage range.
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Electrical Characteristics
•
— When the SerDes reference clock differential inputs are DC coupled externally with the clock driver chip, the
maximum average current allowed for each input pin is 8 mA. In this case, the exact common mode input voltage
is not critical as long as it is within the range allowed by the maximum average current of 8 mA because the input
is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V (0.4 V / 50 = 8 mA)
while the minimum common mode input level is 0.1 V above GNDSXC. For example, a clock with a 50/50 duty
cycle can be produced by a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V),
such that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the common mode
voltage at 400 mV.
— If the device driving the SD_REF_CLK[1–2] and SD_REF_CLK[1–2] inputs cannot drive 50 Ω to GNDSXC DC
or the drive strength of the clock driver chip exceeds the maximum input current limitations, it must be
AC-coupled externally.
The input amplitude requirement is described in detail in the following sections.
2.5.2.3
SerDes Transmitter and Receiver Reference Circuits
Figure 5 shows the reference circuits for SerDes data lane transmitter and receiver.
50 Ω SD_[A–J]_TX
SD_[A–J]_RX
50 Ω
Transmitter
Receiver
50 Ω
SD_[A–J]_TX
SD_[A–J]_RX
50 Ω
Note: The [A–J] indicates the specific SerDes lane. Each lane can be assigned to a specific
protocol by the RCW assignments at reset (see Chapter 5, Reset in the reference manual
for details). External AC coupling capacitors are required for all protocols for all lanes.
Figure 5. SerDes Transmitter and Receiver Reference Circuits
2.5.2.4
Equalization
With the use of high-speed serial links, the interconnect media causes degradation of the signal at the receiver and produces
effects such as inter-symbol interference (ISI) or data-dependent jitter. This loss can be large enough to degrade the eye opening
at the receiver beyond that allowed by the specification. To offset a portion of these effects, equalization can be used. The
following is a list of the most commonly used equalization techniques:
•
•
•
2.5.3
Pre-emphasis on the transmitter.
A passive high-pass filter network placed at the receiver, often referred to as passive equalization.
The use of active circuits in the receiver, often referred to as adaptive equalization.
DC-Level Requirements for SerDes Interfaces
The following subsections define the DC-level requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, the CPRI data lines, and the SGMII data lines.
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Electrical Characteristics
2.5.3.1
DC-Level Requirements for SerDes Reference Clocks
The DC-level requirement for the SerDes reference clock inputs is different depending on the signaling mode used to connect
the clock driver chip and SerDes reference clock inputs, as described below:
•
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV differential peak-peak (or
between 200 mV and 800 mV differential peak). In other words, each signal wire of the differential pair must have
a single-ended swing of less than 800 mV and greater than 200 mV. This requirement is the same for both external
DC-coupled or AC-coupled connection.
— For an external DC-coupled connection, the maximum average current requirements sets the requirement for
average voltage (common mode voltage) as between 100 mV and 400 mV. Figure 6 shows the SerDes reference
clock input requirement for DC-coupled connection scheme.
SD_REF_CLK[1–2]
200 mV < Input Amplitude or Differential Peak < 800 mV
Vmax < 800 mV
100 mV < Vcm < 400 mV
Vmin > 0 V
SD_REF_CLK[1–2]
Figure 6. Differential Reference Clock Input DC Requirements (External DC-Coupled)
— For an external AC-coupled connection, there is no common mode voltage requirement for the clock driver.
Because the external AC-coupling capacitor blocks the DC-level, the clock driver and the SerDes reference clock
receiver operate in different command mode voltages. The SerDes reference clock receiver in this connection
scheme has its common mode voltage set to GNDSXC. Each signal wire of the differential inputs is allowed to
swing below and above the command mode voltage GNDSXC. Figure 7 shows the SerDes reference clock input
requirement for AC-coupled connection scheme.
200 mV < Input Amplitude or Differential Peak < 800 mV
SD_REF_CLK[1–2]
Vmax < Vcm + 400 mV
Vcm
SD_REF_CLK[1–2]
Vmin > Vcm – 400 mV
Figure 7. Differential Reference Clock Input DC Requirements (External AC-Coupled)
•
Single-Ended Mode
— The reference clock can also be single-ended. The SD_REF_CLK[1–2] input amplitude (single-ended swing)
must be between 400 mV and 800 mV peak-peak (from VMIN to VMAX) with SD_REF_CLK[1–2] either left
unconnected or tied to ground.
— The SD_REF_CLK[1–2] input average voltage must be between 200 and 400 mV. Figure 8 shows the SerDes
reference clock input requirement for single-ended signaling mode.
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Electrical Characteristics
— To meet the input amplitude requirement, the reference clock inputs may need to be DC- or AC-coupled
externally. For the best noise performance, the reference of the clock could be DC- or AC-coupled into the unused
phase (SD_REF_CLK[1–2]) through the same source impedance as the clock input (SD_REF_CLK[1–2]) in use.
400 mV < SD_REF_CLK[1–2] Input Amplitude < 800 mV
SD_REF_CLK[1–2]
0V
SD_REF_CLK[1–2]
Figure 8. Single-Ended Reference Clock Input DC Requirements
2.5.3.2
DC-Level Requirements for PCI Express Configurations
The DC-level requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The
MSC8157E supports a 2.5 Gbps and a 5 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision
2.0. The transmitter specifications for 2.5 Gbps are defined in Table 11 and the receiver specifications are defined in Table 12.
For 5 Gbps, the transmitter specifications are defined in Table 13 and the receiver specifications are defined in Table 14.
Note:
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 11. PCI Express (2.5 Gbps) Differential Transmitter (Tx) Output DC Specifications
Parameter
Symbol
Min
Nom
Max
Units
Condition
Differential peak-to-peak output voltage
swing
VTX-DIFFp-p
800
1000
1200
mV
VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|,
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
De-emphasized differential output
voltage (ratio)
VTX-DE-RATIO
3.0
3.5
4.0
dB
Ratio of the VTX-DIFFp-p of the second
and following bits after a transition
divided by the VTX-DIFFp-p of the first bit
after a transition.
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
DC differential Tx impedance
ZTX-DIFF-DC
80
100
120
Ω
Tx DC differential mode low Impedance
ZTX-DC
40
50
60
Ω
Required Tx D+ as well as D– DC
Impedance during all states
DC single-ended TX impedance
Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications
Parameter
Symbol
Min
Nom
Max
Units
Notes
Differential input peak-to-peak voltage
VRX-DIFFp-p
120
1000
1200
mV
1
DC differential Input Impedance
ZRX-DIFF-DC
80
100
120
Ω
2
ZRX-DC
40
50
60
Ω
3
ZRX-HIGH-IMP-DC
50
—
—
ΚΩ
4
VRX-IDLE-DET-DIFFp-p
65
—
175
mV
5
DC input impedance
Powered down DC input impedance
Electrical idle detect threshold
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Electrical Characteristics
Table 12. PCI Express (2.5 Gbps) Differential Receiver (Rx) Input DC Specifications (continued)
Parameter
Notes:
1.
2.
3.
4.
5.
Symbol
Min
Nom
Max
Units
Notes
VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to
detect (the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all
unconfigured lanes of a port.
Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50 Ω to
GND on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state
of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of
a port.
Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode
impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect
circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx
ground.
VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. Measured at the package pins of the receiver
Table 13. PCI Express (5 Gbps) Differential Transmitter (Tx) Output DC Specifications
Parameter
Symbol
Min
Nom
Max
Units
Differential peak-to-peak output voltage
swing
VTX-DIFFp-p
800
1000
1200
mV
VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|,
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
VTX-DIFFp-p_low
400
500
1200
mV
VTX-DIFFp-p = 2 × |VTX-D+ – VTX-D–|,
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
De-emphasized differential output
voltage (ratio)
VTX-DE-RATIO-3.5dB
3.0
3.5
4.0
dB
Ratio of the VTX-DIFFp-p of the second
and following bits after a transition
divided by the VTX-DIFFp-p of the first bit
after a transition.
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
De-emphasized differential output
voltage (ratio)
VTX-DE-RATIO-6.0dB
5.5
6.0
6.5
dB
Ratio of the VTX-DIFFp-p of the second
and following bits after a transition
divided by the VTX-DIFFp-p of the first bit
after a transition.
Measured at the package pins with a
test load of 50 Ω to GND on each pin.
ZTX-DIFF-DC
80
100
120
Ω
Tx DC differential mode low impedance
ZTX-DC
40
50
60
Ω
Required Tx D+ as well as D– DC
impedance during all states
Low power differential peak-to-peak
output voltage swing
DC differential Tx impedance
Transmitter DC impedance
Condition
Table 14. PCI Express (5 Gbps) Differential Receiver (Rx) Input DC Specifications
Parameter
Symbol
Min
Nom
Max
Units
Notes
Differential input peak-to-peak voltage
VRX-DIFFp-p
120
1000
1200
mV
1
DC differential Input Impedance
ZRX-DIFF-DC
80
100
120
Ω
2
ZRX-DC
40
50
60
Ω
3
ZRX-HIGH-IMP-DC
50
—
—
ΚΩ
4
VRX-IDLE-DET-DIFFp-p
65
—
175
mV
5
DC input impedance
Powered down DC input impedance
Electrical idle detect threshold
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Electrical Characteristics
Table 14. PCI Express (5 Gbps) Differential Receiver (Rx) Input DC Specifications (continued)
Parameter
Notes:
Min
Nom
Max
Units
Notes
VRX-DIFFp-p = 2 × |VRX-D+ – VRX-D-| Measured at the package pins with a test load of 50 Ω to GND on each pin.
Rx DC differential mode impedance. Impedance during all LTSSM states. When transitioning from a fundamental reset to
detect (the initial state of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all
unconfigured lanes of a port.
Required Rx D+ as well as D– DC Impedance (50 ±20% tolerance). Measured at the package pins with a test load of 50 Ω to
GND on each pin. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state
of the LTSSM), there is a 5 ms transition time before the receiver termination values must be met on all unconfigured lanes of
a port.
Required Rx D+ as well as D– DC Impedance when the receiver terminations do not have power. The Rx DC common mode
impedance that exists when no power is present or fundamental reset is asserted. This helps ensure that the receiver detect
circuit does not falsely assume a receiver is powered on when it is not. This term must be measured at 300 mV above the Rx
ground.
VRX-IDLE-DET-DIFFp-p = 2 × |VRX-D+ – VRX-D–|. Measured at the package pins of the receiver
1.
2.
3.
4.
5.
2.5.3.3
Note:
Symbol
DC Level Requirements for Serial RapidIO Configurations
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 15. Serial RapidIO Transmitter DC Specifications for Transfer Rates ≤ 3.125 Gbaud
Parameter
Symbol
Min
Nom
Max
Units
VO
–0.40
—
2.30
V
Long run differential output voltage
VDIFFPP
800
—
1600
mVp-p
L[A–J]TECR0[AMP_RED] = 0b000000
Short run differential output voltage
VDIFFPP
500
—
1000
mVp-p
L[A–J]TECR0[AMP_RED] = 0b001000
ZTX-DIFF-DC
80
100
120
Ω
Output voltage
DC differential TX impedance
Note:
Condition
Voltage relative to COMMON of either signal comprising a differential pair.
Table 16. Serial RapidIO Receiver DC Specifications for Transfer Rates ≤ 3.125 Gbaud
Parameter
Symbol
Min
Nom
Max
Units
VIN
200
—
1600
mVp-p
ZRX-DIFF-DC
80
100
120
Ω
Differential input voltage
DC differential RX impedance
Notes:
1.
2.
Voltage relative to COMMON of either signal comprising a differential pair.
Specifications are for Long and Short Run.
Table 17. Serial RapidIO Transmitter DC Specifications for Short Run at 5 Gbaud
Parameter
Symbol
Min
Nom
Max
Units
Output differential voltage
(into floating load Rload = 100 Ω)
T_Vdiff
400
—
750
mV
T_Rd
80
100
120
Ω
Differential resistance
Condition
Amplitude setting
L[A–J]TECR0[AMP_RED] = 0b001101
Table 18. Serial RapidIO Receiver DC Specifications for Short Run at 5 Gbaud
Parameter
Symbol
Min
Nom
Max
Units
Input differential voltage
R_Vdiff
125
—
1200
mV
Differential resistance
R_Rdin
80
120
Ω
Table 19. Serial RapidIO Transmitter DC Specifications for Long Run at 5 Gbaud
Parameter
Symbol
Min
Nom
Max
Units
Output differential voltage
(into floating load Rload = 100 Ω)
T_Vdiff
800
—
1200
mV
Conditions
Amplitude setting
L[A–J]TECR0[AMP_RED] = 0b000000
(with de-emphasis disabled)
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Table 19. Serial RapidIO Transmitter DC Specifications for Long Run at 5 Gbaud (continued)
Parameter
Symbol
Min
Nom
Max
Units
De-emphasized differential output
voltage
T_VTX-DE-RATIO-3.5dB
3
3.5
4
dB
• p(n)_(y)_tx_eq_type[1:0] = 01
• p(n)_(y)_tx_ratio_post1q[3:0] = 1110
Tx De-emphasized level
T_VTX-DE-RATIO-6.0dB
5.5
6
6.5
dB
• p(n)_(y)_tx_eq_type[1:0] = 01
• p(n)_(y)_tx_ratio_post1q[3:0] = 1100
T_Rd
80
100
120
Ω
Differential resistance
Conditions
Table 20. Serial RapidIO Receiver DC Specifications for Long Run at 5 Gbaud
Parameter
Symbol
Min
Nom
Max
Units
Condition
Input differential
voltage
R_Vdiff
N/A
—
1200
mV
It is assumed that for the R_Vdiff
min specification, that the eye
can be closed at the receiver
after passing the signal through a
CEI/SRIO Level II LR compliant
channel.
Differential resistance
R_Rdin
80
—
120
Ω
2.5.3.4
DC-Level Requirements for CPRI Configurations
This section provide various DC-level requirements for CPRI Configurations.
Note:
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 21. CPRI Transmitter DC Specifications (LV: 1.2288, 2.4576 and 3.072 Gbps)
Parameter
Output voltage
Differential output voltage
Differential resistance
Note:
Symbol
Min
Nom
Max
Units
VO
–0.40
—
2.30
V
VDIFFPP
800
—
1600
mVp-p
T_Rd
80
100
120
Ω
Condition
Voltage relative to COMMON of either signal
comprising a differential pair.
L[A–J]TECR0[AMP_RED] = 0b000000.
LV is XAUI-based.
Table 22. CPRI Transmitter DC Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Parameter
Symbol
Min
Nom
Max
Units
Output differential voltage (into floating
load Rload = 100 Ω)
T_Vdiff
800
—
1200
mV
T_Rd
80
100
120
Ω
Differential resistance
Note:
Condition
L[A–J]TECR0[AMP_RED] = 0x000000
LV-II is CEI-6G-LR-based.
Table 23. CPRI Receiver DC Specifications (LV: 1.2288, 2.4576 and 3.072 Gbps)
Parameter
Differential input voltage
Difference resistance
Note:
Symbol
Min
Nom
Max
Units
Condition
VIN
200
—
1600
mVp-p
Measured at receiver.
R_Rdin
80
—
120
Ω
LV is XAUI-based.
Table 24. CPRI Receiver DC Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Parameter
Input differential voltage
Symbol
Min
Nom
Max
Units
Condition
R_Vdiff
N/A
—
1200
mV
It is assumed that for the R_Vdiff
min specification, that the eye
can be closed at the receiver
after passing the signal through a
CEI/CPRI Level II LR compliant
channel.
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Table 24. CPRI Receiver DC Specifications (continued)(LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Parameter
Symbol
Min
Nom
Max
Units
Differential resistance
R_Rdin
80
—
120
Ω
Note:
LV-II is CEI-6G-LR-based.
2.5.3.5
Note:
Condition
DC-Level Requirements for SGMII Configurations
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 25 describes the SGMII SerDes transmitter AC-coupled DC electrical characteristics.
Table 25. SGMII DC Transmitter Electrical Characteristics
Parameter
Symbol
Min
Nom
Max
Unit
Conditions
Output differential
voltage
|VOD|
0.64 × Nom
500
1.45 × Nom
mV
1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0 V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[A–J]TECR0[AMD_RED] = 0b000000
Output differential
voltage
|VOD|
0.64 × Nom
459
1.45 × Nom
mV
1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[A–J]TECR0[AMD_RED] = 0b000010
Output differential
voltage
|VOD|
0.64 × Nom
417
1.45 × Nom
mV
1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[A–J]TECR0[AMD_RED] = 0b000101
Output differential
voltage
|VOD|
0.64 × Nom
376
1.45 × Nom
mV
1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[A–J]TECR0[AMD_RED] = 0b001000
Output differential
voltage
|VOD|
0.64 × Nom
333
1.45 × Nom
mV
1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[A–J]TECR0[AMD_RED] = 0b001100
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Electrical Characteristics
Table 25. SGMII DC Transmitter Electrical Characteristics (continued)
Parameter
Symbol
Min
Nom
Max
Unit
Conditions
Output differential
voltage
|VOD|
0.64 × Nom
292
1.45 × Nom
mV
1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[A–J]TECR0[AMD_RED] = 0b001111
Output differential
voltage
|VOD|
0.64 × Nom
250
1.45 × Nom
mV
1. The |VOD| value shown in the Typ column is
based on the condition of
XVDD_SRDS2-Typ=1.0V, no common mode
offset variation (VOS =500mV), SerDes
transmitter is terminated with 100-Ω
differential load between SD_TXn and
SD_TXn.
2. Amplitude setting:
[A–J]TECR0[AMD_RED] = 0b010011
Output impedance
(single-ended)
RO
40
50
60
Ω
—
Output high
voltage
VOH
—
—
1.5 × |VOD, max|
mV
—
Output low voltage
VOL
|VOD|, min/2
—
—
mV
—
Table 26 describes the SGMII SerDes receiver AC-coupled DC electrical characteristics.
Table 26. SGMII DC Receiver Electrical Characteristics1,2
Symbol
Min
Nom
Max
Unit
Input differential voltage3
Parameter
VRX_DIFFp-p
100
—
1200
mV
175
—
1200
mV
L[A–J]GCR1[RECTL_SIGD] = 0b100
Loss of signal threshold4
VLOS
30
—
100
mV
L[A–J]GCR1[RECTL_SIGD] = 0b001
65
—
175
mV
L[A–J]GCR1[RECTL_SIGD] = 0b100
Receiver differential input
impedance
ZRX_DIFF
80
—
120
Ω
Notes:
1.
2.
3.
Condition
L[A–J]GCR1[RECTL_SIGD] = 0b001
—
Input must be externally AC-coupled.
VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage.
The concept of this parameter is equivalent to the Electrical Idle Detect Threshold parameter in the PCI Express interface.
Refer to the PCI Express Differential Receiver (RX) Input Specifications section of the PCI Express Specification document.
for details.
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Electrical Characteristics
2.5.4
RGMII and Other Interface DC Electrical Characteristics
Table 27 describes the DC electrical characteristics for the following interfaces:
•
•
•
•
•
•
•
•
•
•
•
RGMII Ethernet
SPI
GPIO
UART
TIMER
EE
I2C
Interrupts (IRQn, NMI_OUT/CP_RX_INT, INT_OUT/CP_TX_INT)
Clock and resets (CLKIN/MCLKIN, PORESET, HRESET, HRESET_IN)
DMA External Request
JTAG signals
Table 27. 2.5 V I/O DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Notes
Input high voltage
VIH
1.7
—
V
1
Input low voltage
VIL
—
0.7
V
1
Input high current (VIN = VDDIO)
IIN
—
30
μA
2
Input low current (VIN = GND)
IINL
–30
—
μA
2
Output high voltage (VDDIO = min, IOH = –1.0 mA)
VOH
2.0
VDDIO + 0.3
V
1
Output low voltage (VDDIO = min, IOL= 1.0 mA)
VOL
GND – 0.3
0.40
V
1
Notes:
1.
2.
The min VIL and max VIH values are based on the respective min and max VIN values listed in Table 4.
The symbol VIN represents the input voltage of the supply. It is referenced in Table 4.
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Electrical Characteristics
2.6
AC Timing Characteristics
This section describes the AC timing characteristics for the MSC8157E.
2.6.1
DDR SDRAM AC Timing Specifications
This section describes the AC electrical characteristics for the DDR SDRAM interface.
2.6.1.1
DDR SDRAM Input AC Timing Specifications
Table 28 provides the input AC timing specifications for the DDR SDRAM when VDDDDR (typ) = 1.5 V.
Table 28. DDR3 SDRAM Input AC Timing Specifications for 1.5 V Interface
Parameter
Symbol
Min
AC input low voltage
• > 1200 MHz data rate
• ≤ 1200 MHz data rate
VILAC
—
AC input high voltage
• > 1200 MHz data rate
• ≤ 1200 MHz data rate
VIHAC
Note:
Max
Unit
V
MVREF – 0.150
MVREF – 0.175
—
V
MVREF + 0.150
MVREF + 0.175
At recommended operating conditions with VDDDDR of 1.5 ± 5%.
Table 29 provides the input AC timing specifications for the DDR SDRAM interface.
Table 29. DDR SDRAM Input AC Timing Specifications
Parameter
Symbol
Controller Skew for MDQS—MDQ/MECC
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tCISKEW
Tolerated Skew for MDQS—MDQ/MECC
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDISKEW
Notes:
1.
2.
3.
4.
Min
Max
Unit
–125
–142
–170
–200
–240
125
142
170
200
240
ps
ps
ps
ps
ps
–250
–275
–300
–425
–510
250
275
300
425
510
ps
ps
ps
ps
ps
Notes
1, 2, 4
2, 3
tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that is
captured with MDQS[n]. Subtract this value from the total timing budget.
At recommended operating conditions with VDDDDR (1.5 V) ± 5%
The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW.This can be
determined by the following equation: tDISKEW = ±(T ÷ 4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
The tCISKEW test coverage is derived from the tDISKEW parameters.
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Figure 9 shows the DDR3 SDRAM interface input timing diagram.
MCK[n]
MCK[n]
tMCK
MDQS[n]
tDISKEW
MDQ[n]
D0
D1
tDISKEW
tDISKEW
Figure 9. DDR3 SDRAM Interface Input Timing Diagram
2.6.1.2
DDR SDRAM Output AC Timing Specifications
Table 30 provides the output AC timing specifications for the DDR SDRAM interface.
Table 30. DDR SDRAM Output AC Timing Specifications
Parameter
MCK[n] cycle time
Symbol 1
Min
Max
Unit
tMCK
1.5
3
ns
ADDR/CMD output setup with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHAS
ADDR/CMD output hold with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHAX
MCSn output setup with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHCS
MCSn output hold with respect to MCK
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHCX
MCK to MDQS Skew
• > 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHMH
Notes
2
3
0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
0.606
0.675
0.744
0.917
1.10
—
—
—
—
—
ns
ns
ns
ns
ns
–0.245
–0.375
–0.6
0.245
0.375
0.6
ns
ns
ns
3
3
3
4
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Electrical Characteristics
Table 30. DDR SDRAM Output AC Timing Specifications (continued)
Symbol 1
Parameter
Min
Max
Unit
250
275
300
375
450
—
—
—
—
—
ps
ps
ps
ps
ps
250
275
300
375
450
—
—
—
—
—
ps
ps
ps
ps
ps
Notes
5, 6
MDQ/MECC/MDM output setup with respect to MDQS
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHDS,
tDDKLDS
MDQ/MECC/MDM output hold with respect to MDQS
• 1333 MHz data rate
• 1200 MHz data rate
• 1066 MHz data rate
• 800 MHz data rate
• 667 MHz data rate
tDDKHDX,
tDDKLDX
MDQS preamble
tDDKHMP
0.9 × tMCK
—
ns
—
MDQS postamble
tDDKHME
0.4 × tMCK
0.6 × tMCK
ns
—
Notes:
1.
2.
3.
4.
5.
6.
Note:
5
The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference (K)
goes low (L) until data outputs (D) are invalid (X) or data output hold time.
All MCK/MCK referenced measurements are made from the crossing of the two signals.
ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control of
the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the
CLK_CNTL register. The timing parameters listed in the table assume that these two parameters have been set to the same
adjustment value. See the MSC8157E Reference Manual for a description and understanding of the timing modifications
enabled by use of these bits.
Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MSC8157E.
At recommended operating conditions with VDDDDR (1.5 V) ± 5%.
For the ADDR/CMD setup and hold specifications in Table 30, it is assumed that the clock control register is set to
adjust the memory clocks by ½ applied cycle.
Figure 10 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
MCK[n]
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns or 0.375 ns
MDQS
tDDKHMH(min) = –0.6 ns or –0.375 ns
MDQS
Figure 10. MCK to MDQS Timing
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Figure 11 shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS, tDDKHCS
tDDKHAX, tDDKHCX
ADDR/CMD
Write A0
NOOP
tDDKHMP
tDDKHMH
MDQS[n]
tDDKHME
tDDKHDS
tDDKLDS
MDQ[x]
D0
D1
tDDKLDX
tDDKHDX
Figure 11. DDR SDRAM Output Timing
Figure 12 provides the AC test load for the DDR3 controller bus.
Output
Z0 = 50 Ω
RL = 50 Ω
VDDDDR/2
Figure 12. DDR3 Controller Bus AC Test Load
2.6.1.3
DDR3 SDRAM Differential Timing Specifications
This section describes the DC and AC differential timing specifications for the DDR3 SDRAM controller interface. Figure 13
shows the differential timing specification.
GVDD
VTR
GVDD/2
VOX or VIX
VCP
GND
Figure 13. DDR3 SDRAM Differential Timing Specifications
Note:
VTR specifies the true input signal (such as MCK or MDQS) and VCP is the complementary input signal (such as
MCK or MDQS).
Table 31 provides the DDR3 differential specifications for the differential signals MDQS/MDQS and MCK/MCK.
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Electrical Characteristics
Table 31. DDR3 SDRAM Differential Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Input AC differential cross-point voltage
VIXAC
0.5 × VDDDDR – 0.150
0.5 × VDDDDR + 0.150
V
Output AC differential cross-point voltage
VOXAC
0.5 × VDDDDR – 0.115
0.5 × VDDDDR + 0.115
V
Note:
I/O drivers are calibrated before making measurements.
2.6.2
HSSI AC Timing Specifications
The following subsections define the AC timing requirements for the SerDes reference clocks, the PCI Express data lines, the
Serial RapidIO data lines, and the SGMII data lines.
2.6.2.1
AC Requirements for SerDes Reference Clock
Table 32 lists AC requirements for the SerDes reference clocks.
Note:
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 32. SD_REF_CLK[1–2] and SD_REF_CLK[1–2] Input Clock Requirements
Parameter
Symbol
Min
Nom
Max
Units
Notes
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] frequency
range
tCLK_REF
—
100/125
CPRI: 122.88
—
MHz
1
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] clock
frequency tolerance
• Serial RapidIO, CPRI, SGMII
• PCI Express interface
tCLK_TOL
—
–100
–300
—
—
100
300
ppm
ppm
tCLK_DUTY
40
50
60
%
4
SD_REF_CLK[1–2]/SD_REF_CLK[1–2]max
deterministic peak-peak jitter at 10-6 BER
tCLK_DJ
—
—
42
ps
—
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] total
reference clock jitter at 10-6 BER (peak-to-peak jitter
at ref_clk input)
tCLK_TJ
—
—
86
ps
2
SD_REF_CLK/SD_REF_CLK rising/falling edge rate
tCLKRR/tCLKFR
1
—
4
V/ns
3
Differential input high voltage
VIH
200
—
—
mV
4
Differential input low voltage
VIL
—
—
–200
mV
4
Rise-Fall
—
—
20
%
5, 6
SD_REF_CLK[1–2]/SD_REF_CLK[1–2] reference
clock duty cycle
Rising edge rate (SD_REF_CLKn to falling edge rate)
Notes:
1.
2.
3.
4.
5.
6.
7.
Only 100, 122.88, and 125 MHz have been tested. CPRI uses 122.88 MHz. The other interfaces use 100 or 125 MHz. Other
values will not work correctly with the rest of the system.
Limits are from PCI Express CEM Rev 2.0.
Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn minus SD_REF_CLKn). The
signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 14.
Measurement taken from differential waveform.
Measurement taken from single-ended waveform.
Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV
window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross
point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rising edge rate
of SD_RF_CLKn should be compared to the falling edge rate of SD_REF_CLKn; the maximum allowed difference should not
exceed 20% of the slowest edge rate. See Figure 15.
REF_CLK jitter must be less than 0.05 UI when measured against a Golden PLL reference. The Golden PLL must have a
maximum baud rate bandwidth greater than 1667, with a maximum 20 dB/dec rolloff down to a baud rate of 16.67 with no
peaking around the corner frequency.
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Electrical Characteristics
Rise Edge Rate
Fall Edge Rate
VIH = +200 mV
0.0 V
VIL = –200 mV
SD_REF_CLKn –
SD_REF_CLKn
Figure 14. Differential Measurement Points for Rise and Fall Time
Figure 15. Single-Ended Measurement Points for Rise and Fall Time Matching
2.6.2.2
Spread Spectrum Clock
SD_REF_CLK[1–2] and SD_REF_CLK[1–2] were designed to work with a spread spectrum clock (+0 to 0.5% spreading at
30–33 KHz rate is allowed), assuming both ends have the same reference clock and the industry protocol supports it. For better
results, use a source without significant unintended modulation.
2.6.2.3
PCI Express AC Physical Layer Specifications
The AC requirements for PCI Express implementations have separate requirements for the Tx and Rx lines. The MSC8157E
supports a 2.5 Gbps or a 5.0 Gbps PCI Express interface defined by the PCI Express Base Specification, Revision 2.0. The 2.5
Gbps transmitter specifications are defined in Table 33 and the receiver specifications are defined in Table 34. The 5.0 Gbps
transmitter specifications are defined in Table 35 and the receiver specifications are defined in Table 36. The parameters are
specified at the component pins. the AC timing specifications do not include REF_CLK jitter.
Note:
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 33. PCI Express 2.0 (2.5 Gbps) Differential Transmitter (Tx) Output AC Specifications
Parameter
Symbol
Min
Nom
Max
Units
Comments
Unit interval
UI
399.88
400.00
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See note 1.
Tx eye width
TTX-EYE
0.75
—
—
UI
The maximum transmitter jitter can be derived as
TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI. This
does not include spread spectrum or REF_CLK
jitter. It includes device random jitter at 10–12.
See notes 2 and 3.
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Electrical Characteristics
Table 33. PCI Express 2.0 (2.5 Gbps) Differential Transmitter (Tx) Output AC Specifications (continued)
Parameter
Symbol
Min
Nom
Max
Units
Comments
Time between the jitter
median and maximum
deviation from the median.
TTX-EYE-MEDIAN-
—
—
0.125
UI
Jitter is defined as the measurement variation of
the crossing points (VTX-DIFFp-p = 0 V) in relation
to a recovered Tx UI. A recovered Tx UI is
calculated over 3500 consecutive unit intervals
of sample data. Jitter is measured using all
edges of the 250 consecutive UI in the center of
the 3500 UI used for calculating the Tx UI. See
notes 2 and 3.
75
—
200
nF
All transmitters must be AC coupled. The AC
coupling is required either within the media or
within the transmitting component itself. See
note 4.
AC coupling capacitor
Notes:
1.
2.
3.
4.
to-MAX-JITTER
CTX
No test load is necessarily associated with this value.
Specified at the measurement point into a timing and voltage test load as shown in Figure 16 and measured over any 250
consecutive Tx UIs.
A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-NAX-JITTER = 0.25 UI for the
transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
The DSP device SerDes transmitter does not have a built-in CTX. An external AC coupling capacitor is required.
Table 34. PCI Express 2.0 (2.5 Gbps) Differential Receiver (Rx) Input AC Specifications
Parameter
Symbol
Min
Nom
Max
Units
UI
399.88
400.00
400.12
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See note 1.
Minimum receiver eye width
TRX-EYE
0.4
—
—
UI
The maximum interconnect media and
Transmitter jitter that can be tolerated by the
Receiver can be derived as TRX-MAX-JITTER = 1 –
TRX-EYE= 0.6 UI. See notes 2 and 3.
Maximum time between the
jitter median and maximum
deviation from the median.
TRX-EYE-MEDIAN-t
—
—
0.3
UI
Jitter is defined as the measurement variation of
the crossing points (VRX-DIFFp-p = 0 V) in relation
to a recovered Tx UI. A recovered Tx UI is
calculated over 3500 consecutive unit intervals
of sample data. Jitter is measured using all
edges of the 250 consecutive UI in the center of
the 3500 UI used for calculating the Tx UI.
See notes 2, 3, and 4.
Unit Interval
Notes:
1.
2.
3.
4.
o-MAX-JITTER
Comments
No test load is necessarily associated with this value.
Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 16 should be used
as the Rx device when taking measurements. If the clocks to the Rx and Tx are not derived from the same reference clock,
the Tx UI recovered from 3500 consecutive UI must be used as a reference for the eye diagram.
A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and
interconnect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit
algorithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental
and simulated data.
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Electrical Characteristics
Table 35. PCI Express 2.0 (5.0 Gbps) Differential Transmitter (Tx) Output AC Specifications
Parameter
Symbol
Min
Nom
Max
Units
UI
199.94
200.00
200.06
ps
Each UI is 400 ps ± 300 ppm. UI does not
account for spread spectrum clock dictated
variations. See note 1.
Minimum Tx eye width
TTX-EYE
0.75
—
—
UI
The maximum Transmitter jitter can be derived
as: TTX-MAX-JITTER = 1 – TTX-EYE = 0.25 UI.
See notes 2 and 3.
Tx RMS deterministic
jitter > 1.5 MHz
TTX-HF-DJ-DD
—
—
0.15
ps
—
Tx RMS deterministic
jitter < 1.5 MHz
TTX-LF-RMS
—
3.0
—
ps
Reference input clock RMS jitter (< 1.5 MHz) at
pin < 1 ps
AC coupling capacitor
CTX
75
—
200
nF
All transmitters must be AC coupled. The AC
coupling is required either within the media or
within the transmitting component itself.
See note 4.
Unit Interval
Notes:
1.
2.
3.
4.
Comments
No test load is necessarily associated with this value.
Specified at the measurement point into a timing and voltage test load as shown in Figure 16 and measured over any 250
consecutive Tx UIs.
A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of TTX-MAX-JITTER = 0.25 UI for the
Transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
The DSP device SerDes transmitter does not have a built-in CTX. An external AC coupling capacitor is required.
Table 36. PCI Express 2.0 (5.0 Gbps) Differential Receiver (Rx) Input AC Specifications
Parameter
Symbol
Min
Nom
Max
Units
Conditions
UI
199.40
200.00
200.06
ps
Each UI is 400 ps ±300 ppm. UI does not account
for spread spectrum clock dictated variations. See
Note 1.
Max Rx inherent timing error
TRX-TJ-CC
—
—
0.4
UI
The maximum inherent total timing error for
common REF_CLK Rx architecture
Maximum time between the
jitter median and maximum
deviation from the median
TRX-TJ-DC
—
—
0.34
UI
Max Rx inherent total timing error
Max Rx inherent
deterministic timing error
TRX-DJ-DD-CC
—
—
0.30
UI
The maximum inherent deterministic timing error
for common REF_CLK Rx architecture
Max Rx inherent
deterministic timing error
TRX-DJ-DD-DC
—
—
0.24
UI
The maximum inherent deterministic timing error
for common REF_CLK Rx architecture
Unit Interval
Note:
No test load is necessarily accosted with this value.
The AC timing and voltage parameters must be verified at the measurement point. The package pins of the device must be
connected to the test/measurement load within 0.2 inches of that load, as shown in Figure 16.
Note:
The allowance of the measurement point to be within 0.2 inches of the package pins is meant to acknowledge that
package/board routing may benefit from D+ and D– not being exactly matched in length at the package pin boundary.
If the vendor does not explicitly state where the measurement point is located, the measurement point is assumed to
be the D+ and D– package pins.
D+ Package
Pin
C = CTX
TX
Silicon
+ Package
D– Package
Pin
C = CTX
R = 50 Ω
R = 50 Ω
Figure 16. Test Measurement Load
MSC8157E Six-Core Digital Signal Processor with Security Data Sheet, Rev. 2
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Electrical Characteristics
2.6.2.4
Note:
Serial RapidIO AC Timing Specifications
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 37 defines the transmitter AC specifications for the Serial RapidIO interface at frequencies up to 3.125 Gbaud. The AC
timing specifications do not include REF_CLK jitter.
Table 37. Serial RapidIO Transmitter AC Timing Specifications Up to 3.125 Gbaud
Characteristic
Symbol
Min
Nom
Max
Unit
Deterministic Jitter
JD
—
—
0.17
UI p-p
Total Jitter
JT
—
—
0.35
UI p-p
Unit Interval: 1.25 GBaud
UI
800 – 100ppm
800
800 + 100ppm
ps
Unit Interval: 2.5 GBaud
UI
400 – 100ppm
400
400 + 100ppm
ps
Unit Interval: 3.125 GBaud
UI
320 – 100ppm
320
320 + 100ppm
ps
Table 38 defines the Receiver AC specifications for the Serial RapidIO interface at frequencies up to 3.125 Gbaud. The AC
timing specifications do not include REF_CLK jitter.
Table 38. Serial RapidIO Receiver AC Timing Specifications Up to 3.125 Gbaud
Characteristic
Symbol
Min
Nom
Max
Unit
Notes
Deterministic Jitter Tolerance
JD
—
—
0.37
UI p-p
1
Combined Deterministic and Random Jitter
Tolerance
JDR
—
—
0.55
UI p-p
1
JT
—
—
0.65
UI p-p
1, 2
BER
—
—
10–12
—
—
Unit Interval: 1.25 GBaud
UI
800 – 100ppm
800
800 + 100ppm
ps
—
Unit Interval: 2.5 GBaud
UI
400 – 100ppm
400
400 + 100ppm
ps
—
Unit Interval: 3.125 GBaud
UI
320 – 100ppm
320
320 + 100ppm
ps
—
Total Jitter Tolerance
Bit Error Rate
Notes:
1.
2.
Measured at receiver.
Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 17. The sinusoidal jitter component
is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
Table 39 defines the short run transmitter AC specifications for the Serial RapidIO interface at 5 Gbaud. The AC timing
specifications do not include REF_CLK jitter.
Table 39. Serial RapidIO Short Run Transmitter AC Timing Specifications at 5.0 Gbaud
Characteristic
Uncorrelated High Probability Jitter
Symbol
Min
Nom
Max
Unit
T_UHPJ
—
—
0.15
UI p-p
Total Jitter
T_TJ
—
—
0.30
UI p-p
Baud Rate
UI
5.000 – 100ppm
5.000
5.000 + 100ppm
Gbaud
Table 40 defines the short run Receiver AC specifications for the Serial RapidIO interface at 5 Gbaud. The AC timing
specifications do not include REF_CLK jitter.
Table 40. Serial RapidIO Short Run Receiver AC Timing Specifications at 5 Gbaud
Characteristic
Symbol
Min
Nom
Max
Unit
R_Baud
5.000 – 100ppm
5.000
5.000 + 100ppm
Gbaud
Uncorrelated Bounded High Probability Jitter
R_UBHPJ
—
—
0.15
UIp-p
Correlated Bounded High Probability Jitter
R_CBHPJ
—
—
0.3
UIp-p
R_BHPJ
—
—
0.45
UIp-p
Rx Baud Rate
Bounded High Probability Jitter
Sinusoidal Jitter maximum
Sinusoidal Jitter, High Frequency
R_SJ-max
—
—
5
UIp-p
R_SJ-hf
—
—
0.05
UIp-p
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Electrical Characteristics
Table 40. Serial RapidIO Short Run Receiver AC Timing Specifications at 5 Gbaud (continued)
Characteristic
Total jitter (without sinusoidal jitter)
Note:
Symbol
Min
Nom
Max
Unit
R_Tj
—
—
0.6
UIp-p
The AC specifications do not include REF_CLK jitter. The sinusoidal jitter may have any amplitude and frequency in the unshaded
region in Figure 18. The ISI jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PCB trace.
Table 41 defines the Transmitter AC specifications for long run Serial RapidIO interfaces using a transfer rate of 5 Gbps. The
AC timing specifications do not include REF_CLK jitter.
Table 41. Serial RapidIO Transmitter Long Run AC Timing for Transfer Rate of 5 Gbps
Characteristic
Symbol
Min
Nom
Max
Tx Baud Rate
T_Baud
5.000 – 100 ppm
5.000
5.000 + 100 ppm
Gbps
± 100 ppm
Uncorrelated high probability jitter
T_UHPJ
0.15
UI p-p
With de-emphasis
disabled.
0.30
UI p-p
With de-emphasis
disabled.
Total Jitter
T_TJ
—
—
Unit
Conditions
Table 42 defines the Receiver AC specifications for long run Serial RapidIO interfaces using a transfer rate of 5 Gbps. The AC
timing specifications do not include REF_CLK jitter.
Table 42. Serial RapidIO Receiver Long Run AC Timing for Transfer Rate of 5 Gbps
Characteristic
Symbol
Min
Nom
Max
Unit
R_Baud
5.000 – 100 ppm
5.000
5.000 + 100 ppm
Gbps
R_GJ
0.275
UI p-p
Informative jitter budget
@Rx input
Uncorrelated bounded high
probability jitter (DJ)
R_UBHPJ
0.15
UI p-p
Informative jitter budget
@Rx input
Correlated bounded high
probability jitter (ISI)
R_CBHPJ
0.525
UI p-p
Informative jitter budget
@Rx input
R_BHPJ
0.675
UI p-p
Informative jitter budget
@Rx input
R_SJ-max
5
UI p-p
Informative jitter budget
@Rx input
R_SJ-hf
0.05
UI p-p
Informative jitter budget
@Rx input
R_TJ
0.95
UI p-p
Informative jitter budget
@Rx input
Rx Baud Rate
Gaussian
Bounded high probability jitter
(DJ + ISI)
Sinusoidal jitter, maximum
Sinusoidal jitter, high frequency
Total Jitter (does not include
sinusoidal jitter).
Note:
Condition
The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and
frequency in the unshaded region of Figure 18. The ISl jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PC
trace.
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Electrical Characteristics
8.5 UI p-p
Pass
Sinusoidal
Jitter
Amplitude
20dB/dec
0.10 UI p-p
baud/14200
Frequency
baud/1667
20 MHz
Figure 17. Single Frequency Sinusoidal Jitter Limits for Data Rates for 3.125 Gbps and Below
5 UI p-p
Sinusoidal
Jitter
Amplitude
0.05 UI p-p
22.1 kHz
Frequency
2.999 MHz
20 MHz
Figure 18. Single Frequency Sinusoidal Jitter Limits for Data Rate 5.0 Gbps
2.6.2.5
Note:
CPRI AC Timing Specifications
Specifications are valid at the recommended operating conditions listed in Table 4.
Table 43 defines the transmitter AC specifications for the CPRI LV lanes. The AC timing specifications do not include
REF_CLK jitter.
Table 43. CPRI Transmitter AC Timing Specifications (LV-I: 1.2288, 2.4576, and 3.072 Gbps)
Symbol
Min
Nom
Max
Unit
Deterministic Jitter
Characteristic
JD
—
—
0.17
UI p-p
Total Jitter
JT
—
—
0.35
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 – 100ppm
1/1228.8
1/1228.8 + 100ppm
µs
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Electrical Characteristics
Table 43. CPRI Transmitter AC Timing Specifications (LV-I: 1.2288, 2.4576, and 3.072 Gbps) (continued)
Symbol
Min
Nom
Max
Unit Interval: 2.4576 GBaud
Characteristic
UI
1/2457.6 – 100ppm
1/2457.6
1/2457.6 + 100ppm
Unit
µs
Unit Interval: 3.072 GBaud
UI
1/3072.0 – 100ppm
1/3072.0
1/3072.0 + 100ppm
µs
Table 44 defines the transmitter AC specifications for the CPRI LV-II lanes. The AC timing specifications do not include
REF_CLK jitter.
Table 44. CPRI Transmitter AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Characteristic
Symbol
Min
Nom
Max
Unit
T_UHPJ
—
—
0.15
UI p-p
T_TJ
—
—
0.30
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 – 100ppm
1/1228.8
1/1228.8 + 100ppm
µs
Unit Interval: 2.4576 GBaud
UI
1/2457.6 – 100ppm
1/2457.6
1/2457.6 + 100ppm
µs
Unit Interval: 3.072 GBaud
UI
1/3072.0 – 100ppm
1/3072.0
1/3072.0 + 100ppm
µs
Uncorrelated High Probability Jitter
Total Jitter
Unit Interval: 4.9152 GBaud
UI
1/4915.2 – 100ppm
1/4915.2.8
1/4915.2 + 100ppm
µs
Unit Interval: 6.144 GBaud
UI
1/6144.0 – 100ppm
1/6144.0
1/6144.0 + 100ppm
µs
Table 45 defines the Receiver AC specifications for CPRI LV. The AC timing specifications do not include REF_CLK jitter.
Table 45. CPRI Receiver AC Timing Specifications (LV-I: 1.2288, 2.4576, and 3.072 Gbps)
Characteristic
Deterministic jitter tolerance
Combined deterministic and random
jitter tolerance
Symbol
Min
Nom
Max
Unit
JD
—
—
0.37
UI p-p
JDR
—
—
0.55
UI p-p
Total Jitter tolerance
JT
—
—
0.65
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 – 100ppm
1/1228.8
1/1228.8 + 100ppm
ps
Unit Interval: 2.4576 GBaud
UI
1/2457.6 – 100ppm
1/2457.6
1/2457.6 + 100ppm
ps
Unit Interval: 3.072 GBaud
UI
1/3072.0 – 100ppm
1/3072.0
1/3072.0 + 100ppm
ps
BER
—
—
10–12
—
Bit error ratio
Table 46 defines the Receiver AC specifications for CPRI LV-II. The AC timing specifications do not include REF_CLK jitter.
Table 46. CPRI Receiver AC Timing Specifications (LV-II: 1.2288, 2.4576, 3.072, 4.9152, and 6.144 Gbps)
Characteristic
Symbol
Min
Nom
Max
Unit
R_GJ
—
—
0.275
UI p-p
Uncorrelated bounded high probability
jitter
R_UBHPJ
—
—
0.150
UI p-p
Correlated bounded high probability
jitter
R_CBHPJ
—
—
0.525
UI p-p
Gaussian
Bounded high probability jitter
R_BHPJ
—
—
0.675
UI p-p
R_SJ-max
—
—
5.000
UI p-p
R_SJ-hf
—
—
0.050
UI p-p
R_TJ
—
—
0.950
UI p-p
Unit Interval: 1.2288 GBaud
UI
1/1228.8 – 100ppm
1/1228.8
1/1228.8 + 100ppm
µs
Unit Interval: 2.4576 GBaud
UI
1/2457.6 – 100ppm
1/2457.6
1/2457.6 + 100ppm
µs
Unit Interval: 3.072 GBaud
UI
1/3072.0 – 100ppm
1/3072.0
1/3072.0 + 100ppm
µs
Sinusoidal jitter, maximum
Sinusoidal jitter, high frequency
Total Jitter (does not include sinusoidal
jitter).
Unit Interval: 4.9152 GBaud
UI
1/4915.2 – 100ppm
1/4915.2.8
1/4915.2 + 100ppm
µs
Unit Interval: 6.144 GBaud
UI
1/6144.0 – 100ppm
1/6144.0
1/6144.0 + 100ppm
µs
Note:
The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and
frequency in the unshaded region of Figure 18. The ISl jitter (R_CBHPJ) and amplitude have to be correlated, for example, by a PC
trace.
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65
Electrical Characteristics
Note:
The intended application is a point-to-point interface up to two connectors. The maximum allowed total loss (channel
+ interconnects + other loss) is 20.4 dB @ 6.144 Gbps.
2.6.2.6
Note:
SGMII AC Timing Specifications
Specifications are valid at the recommended operating conditions listed in Table 4.
Transmitter and receiver AC characteristics are measured at the transmitter outputs (SD_[A–J]_TX and SD_[A–J]_TX) or at
the receiver inputs (SD_[A–J]_RX and SD_[A–J]_RX) as depicted in Figure 19, respectively.
D+ Package
Pin
C = CTX
TX
Silicon
+ Package
D– Package
Pin
C = CTX
R = 50 Ω
R = 50 Ω
Figure 19. SGMII AC Test/Measurement Load
Table 47 provides the SGMII transmit AC timing specifications. The AC timing specifications do not include REF_CLK jitter.
Table 47. SGMII Transmit AC Timing Specifications
Parameter
Symbol
Min
Nom
Max
Unit interval
UI
800 – 100ppm
800
Deterministic jitter
JD
—
—
Total jitter
JT
—
CTX
75
AC coupling capacitor
Note:
Unit
Condition
800 + 100ppm
pS
± 100ppm
0.17
UI p-p
—
—
0.35
UI p-p
—
200
nF
—
All transmitters must be
AC-coupled
The AC specifications do not include REF_CLK jitter.
Table 48 provides the SGMII receiver AC timing specifications. The AC timing specifications do not include REF_CLK jitter.
Table 48. SGMII Receive AC Timing Specifications
Parameter
Symbol
Min
Nom
Max
Unit interval
UI
800 – 100ppm
800
800 + 100ppm
pS
Deterministic jitter tolerance
JD
—
—
0.37
UI p-p
Measured at receiver.
JDR
—
—
0.55
UI p-p
Measured at receiver
JT
—
—
0.65
UI p-p
Measured at receiver
BER
—
—
10–12
—
Combined deterministic and random
jitter tolerance
Total jitter tolerance
Bit error ratio
Note:
Unit
Condition
± 100ppm
—
The AC specifications do not include REF_CLK jitter. The sinusoidal jitter in the total jitter tolerance may have any amplitude and
frequency in the unshaded region shown in Figure 20 or Figure 21.
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Electrical Characteristics
8.5 UIp-p
Sinusoidal
Jitter
Amplitude
20 dB/dec
0.10 UIp-p
baud/14200
Frequency
baud/1667
20 MHz
Figure 20. Single Frequency Sinusoidal Jitter Limits for Baud Rate
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