NXP Semiconductors
Data Sheet
Document Number: WCT101XADS
Rev. 0 09/2016
WCT101XADS
Overview Description
Features
The WCT101xA is a wireless power transmitter controller
that integrates all
compliant wireless power transmitter design. It is an
intelligent device that works with the NXP touch sensing
technology or uses periodically analog PING to detect a
mobile device for charging while gaining super low standby
power. Once the mobile device is detected, the WCT101xA
controls the power transfer by adjusting the rail voltage, the
phase difference, or the duty cycle of the power stage
according to message packets sent by the mobile device.
Compliant with the latest version Wireless Power
Consortium (WPC) power class 0 specification power
transmitter design
Supports wide transmitter DC input voltage range of 6V
(limited duration at Start/Stop operation) to 16V
Integrated digital demodulation
Supports two-way communication, transmitter to
receiver by FSK and receiver to transmitter by ASK
Supports Q factor detection and calibrated power loss
based Foreign Object Detection (FOD) framework
Supports low standby power
Uses rail voltage control, phase difference control or
duty cycle control with the fixed operation frequency to
alleviate EMI in automotive system
Supports key FOB avoidance function
Supports operation frequency dithering technology to
eliminate AM band interference
Supports CAN/LIN/IIC/SCI/SPI interfaces
LED for system status indication
Over-voltage/current/temperature protection
Software based solution to provide maximum design
freedom and product differentiation
AECQ-100 grade 2 certification
Applications
Automotive Extended Power Profile Power Transmitter
o WPC compliant or customer properties
Wireless Charging System Functional Diagram
To maximize the design freedom and product differentiation,
the WCT101xA supports the extended power profile
consumer power transmitter design (WPC MP-Ax types,
MP-Bx types or customization) using the fixed operation
frequency control methods such as rail voltage control,
phase difference control or duty cycle control etc. by
software based solution, which can support wireless
charging with both extended power profile power receiver
and baseline power profile power receiver. In addition, the
easy-to-use FreeMASTER GUI tool has configuration,
calibration and debugging functions to provide the
user-friendly design experience and reduce time-to-market.
The WCT101xA includes a digital demodulation module to
reduce the external components, an FSK modulation module
to support two-way communication, a protection module to
handle the over-voltage/current/temperature protection, an
FOD module to protect from overheating by misplaced
metallic foreign objects, and general CAN/IIC/SCI/SPI
interfaces for external communications. It also handles any
abnormal condition and operational status and provides
comprehensive indicator outputs for robust system design.
Contents
1
Absolute Maximum Ratings .................................................................................................................... 4
1.1
Electrical operating ratings...................................................................................................................................... 4
1.2
Thermal handling ratings ........................................................................................................................................ 5
1.3
ESD handling ratings ............................................................................................................................................... 5
1.4
Moisture handling ratings ....................................................................................................................................... 5
2
Electrical Characteristics ......................................................................................................................... 6
2.1
General characteristics ............................................................................................................................................ 6
2.2
Device characteristics .............................................................................................................................................. 8
2.3
Thermal operating characteristics ......................................................................................................................... 22
3
Typical Performance Characteristics ............................................................................................... 23
3.1
System efficiency .................................................................................................................................................. 23
3.2
Standby power ...................................................................................................................................................... 23
3.3
Digital demodulation ............................................................................................................................................ 23
3.4
Twoway communication ...................................................................................................................................... 23
3.5
Foreign object detection ....................................................................................................................................... 23
4
Device Information ................................................................................................................................. 24
4.1
Functional block diagram ...................................................................................................................................... 24
4.2
Product features overview .................................................................................................................................... 24
4.3
Pinout diagram ..................................................................................................................................................... 26
4.4
Pin function description ........................................................................................................................................ 26
WCT101XADS, Rev. 0, 09/2016
2
NXP Semiconductors
4.5
Ordering information ............................................................................................................................................ 37
4.6
Package outline drawing ....................................................................................................................................... 37
5
Software Library ...................................................................................................................................... 38
5.1
Memory map ........................................................................................................................................................ 38
5.2
Software library and API description ..................................................................................................................... 38
6
Design Considerations ........................................................................................................................... 39
6.1
Electrical design considerations ............................................................................................................................ 39
6.2
PCB layout considerations ..................................................................................................................................... 40
6.3
Thermal design considerations.............................................................................................................................. 40
7
Links ............................................................................................................................................................. 42
8
Revision History ....................................................................................................................................... 42
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
3
1 Absolute Maximum Ratings
1.1 Electrical operating ratings
Table 1. Absolute maximum electrical ratings (VSS = 0 V, VSSA = 0 V)
Characteristic
Symbol
Notes
1
Min.
Max.
Unit
Supply Voltage Range
VDD
0.3
4.0
V
Analog Supply Voltage Range
VDDA
0.3
4.0
V
ADC High Voltage Reference
VREFHx
0.3
4.0
V
Voltage difference V DD to VDDA
DD
0.3
0.3
V
Voltage difference V SS to VSSA
ss
0.3
0.3
V
VIN
Pin Group 1
0.3
5.5
V
VIN_RESET
Pin Group 2
0.3
4.0
V
Oscillator Input Voltage Range
VOSC
Pin Group 4
0.4
4.0
V
Analog Input Voltage Range
VINA
Pin Group 3
0.3
4.0
V
VIC
5.0
mA
VOC
±20.0
mA
25
25
mA
Digital Input Voltage Range
Input Voltage Range
Input clamp current, per pin (VIN < VSS
Output clamp current, per pin
0.3 V)
2, 3
4
Contiguous pin DC injection current
regional limit
sum of 16 contiguous pins
Output Voltage Range (normal push-pull mode)
Output Voltage Range (open drain mode)
Output Voltage Range
DAC Output Voltage Range
Ambient Temperature
Storage Temperature Range
1.
2.
3.
4.
IIcont
VOUT
Pin Group 1,2
0.3
4.0
V
VOUTOD
Pin Group 1
0.3
5.5
V
VOUTOD_RESET
Pin Group 2
0.3
4.0
V
VOUT_DAC
Pin Group 5
0.3
4.0
V
TA
40
105
°C
TSTG
55
150
°C
Default Mode:
Pin Group 1: GPIO, TDI, TDO, TMS, TCK
Pin Group 2:
Pin Group 3: ADC and Comparator Analog Inputs
Pin Group 4: XTAL, EXTAL
Pin Group 5: DAC analog output
Continuous clamp current.
All 5 volt tolerant digital I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD.
If VIN greater than VDIO_MIN (=VSS 0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If this
limit cannot be observed, then a current limiting resistor is required.
I/O is configured as pushpull mode.
WCT101XADS, Rev. 0, 09/2016
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NXP Semiconductors
1.2 Thermal handling ratings
Table 2. Thermal handling ratings
Symbol
1.
2.
Description
TSTG
Storage temperature
TSDR
Solder temperature, lead-free
Min.
Max.
Unit
Notes
55
150
°C
1
260
°C
2
Determined according to JEDEC Standard JESD22A103, High Temperature Storage Life.
Determined according to IPC/JEDEC Standard JSTD020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Characteristic
1.
1
Min.
Max.
Unit
ESD for Human Body Model (HBM)
-2000
+2000
V
ESD for Machine Model (MM)
-200
+200
V
ESD for Charge Device Model (CDM)
-500
+500
V
Latch-up current at TA= 85°C (ILAT)
-100
+100
mA
Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless
otherwise noted.
1.4 Moisture handling ratings
Table 4. Moisture handling ratings
Symbol
MSL
1.
Description
Min.
Moisture sensitivity level
Max.
3
Unit
Notes
1
Determined according to IPC/JEDEC Standard JSTD020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State
Surface Mount Devices.
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
5
2 Electrical Characteristics
2.1 General characteristics
Table 5. General electrical characteristics
Recommended operating conditions (VREFLx = 0 V, VSSA = 0 V, VSS = 0 V)
Characteristic
Supply Voltage
2
Symbol
VDD ,VDDA
ADC (Cyclic) Reference
VREFHA
Voltage High
VREFHB
ADC (SAR) Reference
Voltage High
Notes
VREFHC
3
Test
Min.
Typ.
Max.
Unit
2.7
3.3
3.6
V
-
3.0
VDDA
V
-
2.0
VDDA
V
conditions
Voltage difference VDD to VDDA
DD
-0.1
0
0.1
V
-
Voltage difference V SS to VSSA
ss
-0.1
0
0.1
V
-
5.5
V
-
VDD
V
-
0.35×VDD
V
-
Input Voltage High (digital
inputs)
Voltage High
Input Voltage Low (digital
inputs)
VIH
1 (Pin Group 1)
0.7×VDD
VIH_RESET
1 (Pin Group 2)
0.7×VDD
VIL
1 (Pin Group 1,2)
VIHOSC
1 (Pin Group 4)
2.0
VDD + 0.3
V
-
VILOSC
1 (Pin Group 4)
-0.3
0.8
V
-
IOH
1 (Pin Group 1)
-
-2
1 (Pin Group 1)
-
-9
-
Oscillator Input Voltage High
XTAL driven by an external
clock source
Oscillator Input Voltage Low
Output Source Current High
(at VOH min.)
4,5
drive strength
mA
drive strength
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NXP Semiconductors
Output Source Current Low
(at VOL max.)
4,5
IOL
drive strength
1 (Pin Group 1,2)
-
2
1 (Pin Group 1,2)
-
9
mA
drive strength
Output Voltage High
VOH
1 (Pin Group 1)
VDD - 0.5
-
-
V
IOH = IOHmax
Output Voltage Low
VOL
1 (Pin Group 1,2)
-
-
0.5
V
IOL = IOLmax
Digital Input Current High
pull-up enabled or disabled
Comparator Input Current
VIN = 2.4 V
to 5.5 V
1 (Pin Group 1)
IIH
-
0
+/-2.5
µA
0
+/-2
µA
VIN = VDDA
-
0
+/-2
µA
VIN = VDDA
1 (Pin Group 2)
VIN = 2.4 V
to VDD
IIHC
1 (Pin Group 3)
Oscillator Input Current High
IIHOSC
1 (Pin Group 4)
Internal Pull-Up Resistance
RPull-Up
20
-
50
-
RPull-Down
20
-
50
-
High
Internal Pull-Down Resistance
Comparator Input Current
IILC
1 (Pin Group 3)
-
0
+/-2
µA
VIN = 0V
Oscillator Input Current Low
IILOSC
1 (Pin Group 4)
-
0
+/-2
µA
VIN = 0V
DAC Output Voltage Range
VDAC
1 (Pin Group 5)
V
RLD = 3
,
CLD = 400
pF
IOZ
1 (Pin Group 1,2)
-
0
+/-1
µA
-
VHYS
1 (Pin Group 1,2)
0.06×VDD
-
-
V
-
CIN
-
10
-
pF
-
COUT
-
10
-
pF
-
Low
VSSA +
0.04
-
VDDA 0.04
1
Output Current High
Impedance State
Schmitt Trigger Input
Hysteresis
Input capacitance
Output capacitance
GPIO pin interrupt pulse
width
6
Bus
TINT_Pulse
7
1.5
-
-
TPort_H_DIS
8
5.5
-
15.1
ns
TPort_H_EN
8
1.5
-
6.8
ns
Port rise and fall time (high
drive strength). Slew
disabled.
Port rise and fall time (high
drive strength). Slew enabled.
-
clock
2.7
3.6 V
3.6 V
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
7
Port rise and fall time (low
drive strength). Slew
disabled.
TPort_L_DIS
9
8.2
-
17.8
ns
Port rise and fall time (low
drive strength). Slew enabled.
TPort_L_EN
9
3.2
-
9.2
ns
0
-
100
MHz
-
-
-
50/100
MHz
-
Device (system and core)
clock frequency
fSYSCLK
Bus clock
fBUS
10
3.6 V
3.6 V
1.
Default Mode
o Pin Group 1: GPIO, TDI, TDO, TMS, TCK
o Pin Group 2:
o Pin Group 3: ADC and Comparator Analog Inputs
o Pin Group 4: XTAL, EXTAL
o Pin Group 5: DAC analog output
2. ADC (Cyclic) specifications are not guaranteed when VDDA is below 3.0 V.
3. ADC (SAR) is only on WCT1013A device.
4. Total chip source or sink current cannot exceed 75 mA.
5. Contiguous pin DC injection current of regional limit including sum of negative injection currents or sum of positive injection
currents of 16 contiguous pins is 25 mA.
6. Applies to a pin only when it is configured as GPIO and configured to cause an interrupt by appropriately programming GPIOn_IPOLR
and GPIOn_IENR.
7. The greater synchronous and asynchronous timing must be met.
8. 75 pF load
9. 15 pF load
10. WCT1011A only supports the maximum bus clock of 50 MHz, and WCT1013A supports 100 MHz maximum bus clock.
2.2 Device characteristics
Table 6. General device characteristics
Power mode transition Behavior
Symbol
Description
Min.
Max.
Unit
199
225
µs
Notes
After a POR event, the amount of delay
TPOR
from when VDD reaches 2.7 V to when the
first instruction executes (over the
operating temperature range).
TS2R
STOP mode to RUN mode
6.79
7.27
µs
1
TLPS2LPR
LPS mode to LPRUN mode
240.9
551
µs
2
VLPS mode to VLPRUN mode
1424
1459
µs
4
WAIT mode to RUN mode
0.57
0.62
µs
3
LPWAIT mode to LPRUN mode
237.2
554
µs
2
VLPWAIT mode to VLPRUN mode
1413
1500
µs
4
TVLPS2VLPR
TW2R
TLPW2LPR
TVLPW2VLPR
Power consumption operating behaviors
WCT101XADS, Rev. 0, 09/2016
8
NXP Semiconductors
Typical at 3.3 V, 25 °C
Mode
Conditions
Max. frequency
Notes
IDD
IDDA
100 MHz
38.1 mA/-
9.9 mA/-
50 MHz/100
27.6 mA/63.7
100 MHz core clock, 50 MHz peripheral
clock, regulators are in full regulation,
relaxation oscillator on, PLL powered on,
continuous MAC instructions with fetches
from program Flash, all peripheral modules
enabled, TMRs and SCIs using 1×
RUN1
peripheral clock, NanoEdge within
5
eFlexPWM using 2× peripheral clock,
ADC/DAC (only one 12-bit DAC and all
6-bit DACs) powered on and clocked,
comparator powered on, all ports
configured as inputs with input low and no
DC loads
5
50 MHz/100 MHz core and peripheral
clock, regulators are in full regulation,
relaxation oscillator on, PLL powered on,
continuous MAC instructions with fetches
from program Flash, all peripheral modules
enabled, TMRs and SCIs using 1×
RUN2
peripheral clock, NanoEdge within
eFlexPWM using 2× peripheral clock,
5
MHz
mA
50 MHz/100
24.0 mA/43.5
9.9
mA/16.7
5
mA
ADC/DAC (only one 12-bit DAC and all
6-bit DACs) powered on and clocked,
comparator powered on, all ports
configured as inputs with input low and no
DC loads
5
WAIT
50 MHz/100 MHz core and peripheral
clock, regulators are in full regulation,
relaxation oscillator on, PLL powered on,
core in WAIT state, all peripheral modules
enabled, TMRs and SCIs using 1× clock,
NanoEdge within eFlexPWM using 2×
clock, ADC/DAC (one 12-bit DAC, all 6-bit
DACs)/comparator powered off, all ports
configured as inputs with input low and no
DC loads
STOP
4 MHz core and peripheral clock,
regulators are in full regulation, relaxation
oscillator on, PLL powered off, core in
STOP state, all peripheral module and
core clocks are off, ADC/DAC/Comparator
powered off, all ports configured as inputs
with input low and no DC loads
5
MHz
mA
4 MHz
6.3 mA/10.1 mA
-/-
5
-/-
5
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
9
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby, PLL disabled,
repeat NOP instructions, all peripheral
modules enabled, except NanoEdge within
eFlexPWM and cyclic ADCs, one 12-bit
DAC and all 6-bit DACs enabled, simple
loop with running from platform instruction
buffer, all ports configured as inputs with
input low and no DC loads
2 MHz
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby, PLL disabled, all
peripheral modules enabled, except
NanoEdge within eFlexPWM and cyclic
ADCs, one 12-bit DAC and all 6-bit DACs
enabled, core in WAIT mode, all ports
configured as inputs with input low and no
DC loads
2 MHz
LPSTOP
200 kHz core and peripheral clock from
relaxation oscillator's low speed clock,
relaxation oscillator in standby mode,
regulators are in standby, PLL disabled,
only PITs and COP enabled, other
peripheral modules disabled and clocks
gated off, core in STOP mode, all ports
configured as inputs with input low and no
DC loads
2 MHz
1.2 mA/1.55 mA
-
5
VLPRUN
32 kHz core and peripheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby,
small regulator is disabled, PLL disabled,
repeat NOP instructions, all peripheral
modules, except COP and EWM, disabled
and clocks gated off, simple loop running
from platform instruction buffer, all ports
configured as inputs with input low and no
DC loads
200 kHz
0.7 mA/1.18 mA
-/-
5
VLPWAIT
32 kHz core and peripheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby,
small regulator is disabled, PLL disabled,
all peripheral modules, except COP,
disabled and clocks gated off, core in
WAIT mode, all ports configured as inputs
with input low and no DC loads
200 kHz
0.7 mA/1.1 mA
-/-
5
LPRUN
LPWAIT
3.1
2.8 mA/2.3 mA
mA/2.73
5
mA
3.1
2.7 mA/2.29 mA
mA/2.73
5
mA
WCT101XADS, Rev. 0, 09/2016
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NXP Semiconductors
VLPSTOP
32 kHz core and peripheral clock from a 64
kHz external clock source, oscillator in
power down, all relaxation oscillators
disabled, large regulator is in standby,
small regulator is disabled, PLL disabled,
all peripheral modules, except COP,
disabled and clocks gated off, core in
STOP mode, all ports configured as inputs
with input low and no DC loads
200 kHz
0.7 mA/1.03 mA
-/-
5
Min.
Max.
Unit
Notes
16
-
ns
6
-
ns
7
570.9
ns
Min.
Typ.
Max.
Unit
-
2.0
-
V
-
2.7
-
V
Reset and interrupt timing
Symbol
tRA
Characteristic
Minimum
desertion to First Address Fetch
tRDA
tIF
Assertion Duration
Delay from Interrupt Assertion to Fetch of
first instruction (exiting STOP mode)
865 × TOSC + 8 ×
TSYSCLK
361.3
PMC Low-Voltage Detection (LVD) and Power-On Reset (POR) parameters
Symbol
Characteristic
8
VPOR_A
POR Assert Voltage
VPOR_R
POR Release Voltage
VLVI_2p7
LVI_2p7 Threshold Voltage
-
2.73
-
V
VLVI_2p2
LVI_2p2 Threshold Voltage
-
2.23
-
V
Description
Min.
Max.
Unit
Notes
fOP
TCK frequency of operation
DC
fSYSCLK/8 (16)
MHz
10
tPW
TCK clock pulse width
50
-
ns
tDS
TMS, TDI data set-up time
5
-
ns
tDH
TMS, TDI data hold time
5
-
ns
tDV
TCK low to TDO data valid
-
30
ns
tTS
TCK low to TDO tri-state
-
30
ns
Min.
Typ.
Max.
Unit
-
1.22
-
V
-
600
-
mA
-
-
30
Mins
9
JTAG timing
Symbol
Regulator 1.2 V parameters
Symbol
VCAP
ISS
TRSC
Characteristic
Output Voltage
11
Short Circuit Current
12
Short Circuit Tolerance (VCAP shorted to
ground)
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
11
VREF
Reference Voltage (after trim)
-
1.21
-
V
Min.
Typ.
Max.
Unit
-
-
50
MHz
External clock timing
Symbol
Characteristic
fOSC
Frequency of operation (external clock
driver)
tPW
Clock pulse width
trise
13
8
14
External clock input rise time
15
ns
-
-
1
ns
-
-
1
ns
tfall
External clock input fall time
Vih
Input high voltage overdrive by an external
clock
0.85×VDD
-
-
V
Vil
Input low voltage overdrive by an external
clock
-
-
0.3×VDD
V
Min.
Typ.
Max.
Unit
8
8
16
MHz
200/240
-
400
MHz
35.5
-
73.2
µs
40
50
60
%
Min.
Typ.
Max.
Unit
4
8
16
MHz
Min.
Typ.
Max.
Unit
7.84
8
8.16
MHz
7.76
8
8.24
MHz
-
405
-
kHz
-
+/-1.5
+/-1.5
+/-2
+/-3
%
%
194/30.1
200/32
206/33.9
kHz
Phase-Locked Loop (PLL) timing
Symbol
Characteristic
fRef_PLL
PLL input reference frequency
fOP_PLL
PLL output frequency
16
17
18
tLock_PLL
PLL lock time
tDC_PLL
Allowed Duty Cycle of input reference
External crystal or resonator specifications
Symbol
Characteristic
fXOSC
Frequency of operation
Relaxation oscillator electrical specifications
Symbol
Characteristic
20
8 MHz Output Frequency
RUN Mode
°C to 105 °C
-40 °C to 105 °C
Standby Mode (IRC trimmed @ 8 MHz)
-40 °C to 105 °C
fROSC_8M
fROSC_8M_Delta
fROSC_200k/32k
20
19,
8 MHz Frequency Variation over 25 °C
RUN Mode
Due to temperature
°C to 105 °C
-40 °C to 105 °C
200 kHz/32 kHz Output Frequency
RUN Mode
-40 °C to 105 °C
19,21
WCT101XADS, Rev. 0, 09/2016
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NXP Semiconductors
fROSC_200k/32k_D
19,20
elta
200 kHz/32 kHz Output Frequency
19,21
Variation over 25 °C
RUN Mode
Due to temperature
°C to 85 °C
22
-40 °C to 105 °C
-
+/-1.5
+/-1.5 (2.5)
+/-2
+/-3 (4)
%
%
-
0.12
10/14.4
-
µs
µs
48
50
52
%
Min.
Typ.
Max.
Unit
-
7.5
18
µs
-
13
113
ms
-
52
452
ms
Stabilization Time
23
tStab
/32 kHz output
tDC_ROSC
19,24
Output Duty Cycle
Flash specifications
Symbol
thvpgm4
Description
Longword Program high-voltage time
thversscr
Sector Erase high-voltage time
thversall
Erase All high-voltage time
25
25,26
thversblk32k
Erase Block high-voltage time for 32
25,27
KB
-
52
452
ms
thversblk256k
Erase Block high-voltage time for 256
25,27
KB
-
104
904
ms
trd1sec1k/2k
Read 1s Section execution time (flash
28
sector)
-
-
60
µs
-
-
0.5
1.7
ms
ms
27
trd1blk32k
trd1blk256k
Read 1s Block execution time
32 KB FlexNVM
256 KB program Flash
tpgmchk
Program Check execution time
28
-
-
45
µs
trdrsrc
Read Resource execution time
28
-
-
30
µs
tpgm4
Program Longword execution time
-
65
145
µs
-
14
114
ms
-
55
122
465
985
ms
ms
-
2.4
4.7
4.7
9.3
-
ms
ms
ms
ms
-
-
-
-
-
65
tersscr
Erase Flash Sector execution time
tersblk32k
tersblk256k
Erase Flash Block execution time
32 KB FlexNVM
256 KB program Flash
tpgmsec512p
tpgmsec512n
tpgmsec1kp
tpgmsec1kn
Program Section execution time
512 B program Flash
512 B FlexNVM
1 KB program Flash
1 KB FlexNVM
trd1all
trdonce
tpgmonce
tersall
27,29
27
Read 1s All Blocks execution time
Read Once execution time
28
Program Once execution time
Erase All Blocks execution time
29
29
-
70/175
0.9/1.8
30
25
µs
30
575/1500
ms
µs
30
ms
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
13
tvfykey
tpgmpart32k
tsetramff
tsetram8k
tsetram32k
teewr8bers
teewr8b8k
teewr8b16k
teewr8b32k
teewr16bers
teewr16b8k
teewr16b16k
teewr16b32k
teewr32bers
teewr32b8k
teewr32b16k
teewr32b32k
tflashret10k
tflashret1k
Verify Backdoor Access Key execution
28
time
-
-
30
µs
Program Partition for EEPROM execution
27
time for 32 KB FlexNVM
-
70
-
ms
-
50
0.3
0.7
0.5
1.0
µs
ms
ms
-
175
260
µs
-
340
385
475
1700
1800
2000
µs
µs
µs
-
175
260
µs
-
340
385
475
1700
1800
2000
µs
µs
µs
-
360
540
µs
-
545
630
810
1950
2050
2250
µs
µs
µs
5
50
Set FlexRAM Function execution time
Control Code 0xFF
8 KB EEPROM backup
32 KB EEPROM backup
27
Byte-write to erased FlexRAM location
execution time27,31
Byte-write to FlexRAM execution time
8 KB EEPROM backup
16 KB EEPROM backup
32 KB EEPROM backup
27
Word-write to erased FlexRAM location
27
execution time
Word-write to FlexRAM execution time
8 KB EEPROM backup
16 KB EEPROM backup
32 KB EEPROM backup
27
Longword-write to erased FlexRAM
27
location execution time
Longword-write to FlexRAM execution
27
time
8 KB EEPROM backup
16 KB EEPROM backup
32 KB EEPROM backup
Data retention after up to 10 K cycles
Data retention after up to 1 K cycles
nflashcyc
Cycling endurance
teeret100
teeret10
33
20
32
100
-
years
32
-
years
32
-
cycles
-
years
10 K
50 K
Data retention up to 100% of write
27
endurance
5
50
Data retention up to 10% of write
27
endurance
20
100
32
-
years
35 K
175 K
-
writes
315 K
1.6 M
-
writes
1.27 M
6.4 M
-
writes
10 M
50 M
-
writes
20 M
100 M
-
writes
32
27,34
neewr16
neewr128
neewr512
neewr4k
neewr8k
Write endurance
EEPROM backup to FlexRAM ratio =
16
EEPROM backup to FlexRAM ratio =
128
EEPROM backup to FlexRAM ratio =
512
EEPROM backup to FlexRAM ratio =
4096
EEPROM backup to FlexRAM ratio =
8192
WCT101XADS, Rev. 0, 09/2016
14
NXP Semiconductors
12-bit cyclic ADC electrical specifications
Symbol
VDDA
VREFHX
fADCCLK
Characteristic
Supply voltage
35
VREFH supply voltage
36
ADC conversion clock
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
VDDA
V
VDDA - 0.6
37
0.1/0.6
-
10/20
MHz
-( VREFH - VREFL)
VREFL
-
VREFH VREFL
VREFH
V
V
VREFL
VSSA
-
VREFH
VDDA
V
V
-
8/6
-
tADCCLK
-
13
-
tADCCLK
-
1.8
-
mA
-
1
5
-
mA
mA
-
9
15
19
-
mA
mA
mA
-
0.1/0.02
-
µA
-
190/0.001
-
µA
-
+/- 1.5 (3)
+/- 2.2 (5)
LSB
44
-
+/- 0.5 (0.6)
+/- 0.8 (1)
LSB
44
-
+/- 8
+/- 12 (13.7)
-
mV
mV
-
0.996 to 1.004
27
0.801 to 0.809
0.99 to
26
1.101
0.798 to
27
0.814
-
-
10.6/9.5
-
bits
-
-
+/-3
mA
-
4.8
-
pF
Max.
Unit
38
RADC
VADCIN
tADC
tADCPU
Conversion range
26
Fully differential
Single-ended/unipolar
Input voltage range (per input)
External Reference
Internal Reference
Conversion time
39
40
ADC power-up time (from adc_pdn)
26
ADC RUN current (per ADC block)
27
ADC RUN current (per ADC block)
at 600 kHz ADC clock, LP mode
8.33 MHz ADC clock, 00 mode
IADCRUN
12.5 MHz ADC clock, 01 mode
16.67 MHz ADC clock, 10 mode
20 MHz ADC clock, 11 mode
IADPWRDWN
IVREFH
ADC power down current (adc_pdn
enabled)41
VREFH current (in external mode)
43
INLADC
Integral non-linearity
DNLADC
Differential non-linearity
VOFFSET
Offset
26
Fully differential
46
Single ended/Unipolar
43
42
45
EGAIN
Gain Error
ENOB
Effective number of bits
IINJ
CADCI
Input injection current
47
48
Input sampling capacitance
16-bit SAR ADC electrical specifications
Symbol
VDDA
VDDA
26
27
Characteristic
Supply voltage
Supply voltage delta to VDD
Min.
Typ.
49
2.7
-
3.6
V
- 0.1
0
+ 0.1
V
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
15
VSSA
Supply voltage delta to VSS
- 0.1
0
+ 0.1
V
VREFH
ADC reference voltage high
VDDA
VDDA
VDDA
V
VREFL
ADC reference voltage low
VSSA
VSSA
VSSA
V
VADIN
Input voltage range
VSSA
-
VDDA
V
CADIN
Input capacitance
16-bit mode
8-/10-/12-bit mode
-
8
4
10
5
pF
pF
RADIN
Input resistance
-
2
5
fADCK
ADC conversion clock frequency50
16-bit mode
8-/10-/12-bit mode
2
1
-
12
18
MHz
MHz
37.037
20.000
-
461.467
818.330
ksps
ksps
-
-
1.7
mA
1.2
3.0
2.4
4.4
2.4
4.0
5.2
6.2
3.9
7.3
6.1
9.5
MHz
MHz
MHz
MHz
-
+/- 7.0
+/- 1.0
+/- 0.5
- 2.7 to +
1.9
- 0.7 to +
0.5
LSB
52
LSB
LSB52
-
- 1.0 to + 4.0
+/- 0.7
+/- 0.2
- 0.3 to +
0.5
LSB
52
LSB
52
LSB
-
-4
- 1.4
- 5.4
- 1.8
LSB
52
LSB
-
- 1 to 0
-
+/- 0.5
LSB
52
LSB
ADC conversion rate without ADC
Crate
IDDA_ADC
hardware averaging
16-bit mode
8-/10-/12-bit mode
Supply current
51
ADC asynchronous clock source
fADACK
ADLPC = 1, ADHSC = 0
ADLPC = 1, ADHSC = 1
ADLPC = 0, ADHSC = 0
ADLPC = 0, ADHSC = 1
53
INLAD
Integral non-linearity
16-bit mode
12-bit mode
< 12-bit modes
DNLAD
Differential non-linearity
16-bit mode
12-bit mode
< 12-bit modes
52
53
EFS
Full-scale error (VADIN = VDDA)
12-bit mode
< 12-bit modes
EQ
Quantization error
16-bit mode
12-bit mode
52
53
52
52
WCT101XADS, Rev. 0, 09/2016
16
NXP Semiconductors
Effective number of bits
ENOB
STEMP
VTEMP25
54
16-bit single-ended mode
Avg = 32
Avg = 4
12.2
11.4
13.9
13.1
-
bits
bits
12-bit single-ended mode
Avg = 32
Avg = 4
-
10.8
10.2
-
bits
bits
Temp sensor slope under -40 °C to 105 °C
-
1.715
-
mV/°C
-
722
-
mV
Min.
Typ.
Max.
Unit
-
1
-
µs
-
-
11
µs
-
+/- 3
+/- 4
LSB
57
-
+/- 0.8
+/- 0.9
LSB
57
Temp sensor voltage
55
at 25 °C
12-bit DAC electrical specifications
Symbol
Characteristic
56
tSETTLE
tDACPU
Settling time under RLD = 3
, CLD = 400
pF
DAC power-up time (from PWRDWN
release to valid DACOUT)
58
INLDAC
Integral non-linearity
DNLDAC
Differential non-linearity
MONDAC
Monotonicity (> 6 sigma monotonicity, <
3.4 ppm non-monotonicity)
VOFFSET
Offset error
58
58
58
(5% to 95% of full range)
-
-
+ 25
+ 35
mV
-
+/- 0.5
+/- 1.5
%
EGAIN
Gain error
VOUT
Output voltage range
VSSA + 0.04
-
VDDA - 0.04
V
SNR
Signal-to-noise ratio
-
85
-
dB
Effective number of bits
-
11
-
bits
Min.
Typ.
Max.
Unit
2.7
-
3.6
V
-
300/-
-/200
µA
-
36/-
-/20
µA
Vss
-
VDD
V
-
-
20
mV
ENOB
(5% to 95% of full range)
Guaranteed
Comparator and 6-bit DAC electrical specifications
Symbol
VDD
IDDHS
IDDLS
Description
Supply voltage
Supply current, High-speed mode(EN=1,
PMODE=1)
59
Supply current, Low-speed mode(EN=1,
PMODE=0)
59
VAIN
Analog input voltage
VAIO
Analog input offset voltage
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
17
Analog comparator hysteresis
60
VH
-
5
13
mV
-
25/10
48
mV
-
55/20
105
mV
-
80/30
148
mV
VCMPOh
Output high
VDD - 0.5
-
-
V
VCMPOl
Output low
-
-
0.5
V
-
-
50
ns
-
-
200
ns
-
40
-
µs
-
7
-
µA
Propagation delay, high-speed
tDHS
mode(EN=1, PMODE=1)
61
Propagation delay, low-speed
tDLS
mode(EN=1, PMODE=0)
tDInit
61
Analog comparator initialization delay
62
IDAC6b
6-bit DAC current adder (enabled)
RDAC6b
6-bit DAC reference inputs
VDDA
-
VDD
V
INLDAC6b
6-bit DAC integral non-linearity
-0.5
-
0.5
LSB
63
DNLDAC6b
6-bit DAC differential non-linearity
-0.3
-
0.3
LSB
63
Min.
Typ.
Max.
Unit
-
100
-
MHz
-
312
-
ps
1
-
-
ns
-
25
-
µs
Min.
Max.
Unit
Notes
Timer input period
2Ttimer + 6
-
ns
67
PINHL
Timer input high/low period
1Ttimer + 3
-
ns
67
POUT
Timer output period
2Ttimer - 2
-
ns
67
Timer output high/low period
1Ttimer - 2
-
ns
67
PWM timing parameters
Symbol
Characteristic
fPWM
PWM clock frequency
SPWMNEP
NanoEdge Placement (NEP) step size
tDFLT
Delay for fault input activating to PWM
output deactivated
64,65
66
tPWMPU
Power-up time
Quad timer timing
Symbol
Characteristic
PIN
POUTHL
QSPI timing
68
Symbol
tC
Characteristic
Cycle time
Min.
Max.
Unit
Master
Slave
Master
Slave
60/35
60/35
-
-
ns
tELD
Enable lead time
-
20/17.5
-
-
ns
tELG
Enable lag time
-
20/17.5
-
-
ns
tCH
Clock (SCLK) high time
28/16.6
28/16.6
-
-
ns
WCT101XADS, Rev. 0, 09/2016
18
NXP Semiconductors
tCL
Clock (SCLK) low time
28/16.6
28/16.6
-
-
ns
tDS
Data set-up time required for inputs
20/16.5
1
-
-
ns
tDH
Data hold time required for inputs
1
3
-
-
ns
tA
Access time (time to data active from
high-impedance state)
5
-
ns
tD
Disable time (hold time to high-impedance
state)
5
-
ns
tDV
Data valid for outputs
-
-
-/5
-/15
ns
tDI
Data invalid
0
0
-
-
ns
tR
Rise time
-
-
1
1
ns
tF
Fall time
-
-
1
1
ns
QSCI timing
Symbol
Characteristic
Min.
Max.
Unit
Notes
-
(fMAX_SCI /16)
Mbit/s
69
BRSCI
Baud rate
PW RXD
RXD pulse width
0.965/BRSCI
1.04/BRSCI
µs
PW TXD
TXD pulse width
0.965/BRSCI
1.04/BRSCI
µs
LIN Slave Mode
Deviation of slave node clock from nominal
clock rate before synchronization
- 14
14
%
Deviation of slave node clock relative to
the master node clock after
synchronization
-2
2
%
13
-
Mater node
bit periods
11
-
Slave node
bit periods
Min.
Max.
Unit
Baud rate
-
1
Mbit/s
TWAKEUP
CAN Wakeup dominant pulse filtered
-
1.5/2
µs
TWAKEUP
CAN Wakeup dominant pulse pass
5
-
µs
FTOL_UNSYNCH
FTOL_SYNCH
TBREAK
Minimum break character length
CAN timing
Symbol
BRCAN
Characteristic
Notes
70
IIC timing
Symbol
Characteristic
Min.
Max.
Unit
Min.
Max.
Min.
Max.
SCL clock frequency
0
100
0
400
kHz
tHD_STA
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
4
-
0.6
-
µs
tSCL_LOW
LOW period of the SCL clock
4.7
-
1.3
-
µs
fSCL
Notes
WCT101XADS, Rev. 0, 09/2016
NXP Semiconductors
19
tSCL_HIGH
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
-
0.6
-
µs
-
0.6
-
µs
73
0.9
Set-up time for a repeated START
condition
4.7
tHD_DAT
Data hold time for IIC bus devices
0
Data set-up time
71
250
74
3.45
72
-
0
100
75
71
µs
-
ns
72
tr
Rise time of SDA and SCL signals
-
1000
20 + 0.1Cb
300
ns
76
tf
Fall time of SDA and SCL signals
-
300
20 + 0.1Cb
300
ns
75
tSU_STOP
Set-up time for STOP condition
4
-
0.6
-
µs
tBUS_Free
Bus free time between STOP and START
condition
4.7
-
1.3
-
µs
Pulse width of spikes that must be
suppressed by the input filter
N/A
N/A
0
50
ns
tSP
2.
3.
4.
5.
4
tSU_STA
tSU_DAT
1.
HIGH period of the SCL clock
CPU clock = 4 MHz and System running from 8 MHz IRC Applicable to all wakeup times: Wakeup times (in 1,2,3,4) are measured
from GPIO toggle for wakeup till GPIO toggle at the wakeup interrupt subroutine from respective stop/wait mode.
CPU clock = 200 kHz and 8 MHz IRC on standby. Exit via interrupt on Port C GPIO.
Clock configuration: CPU and system clocks= 100 MHz; Bus Clock = 50 MHz. Exit via an interrupt on PortC GPIO.
Using 64 KHz external clock; CPU Clock = 32 KHz. Exit via an interrupt on PortC GPIO.
WCT1011A supports maximum 100 MHz CPU clock and 50 MHz peripheral bus clock, maximum 100 MHz CPU and peripheral bus
clock for WCT1013A. In total, WCT1013A has higher power consumption than WCT1011A in the same operating mode. For the
current consumption data, the former is for WCT1011A, and the latter for WCT1013A.
pin filter is enabled by setting the RST_FLT bit in the SIM_CTRL register to 1, the minimum pulse assertion must be
If the
greater than 21 ns.
TOSC means oscillator clock cycle; TSYSCLK means system clock cycle.
During 3.3 V VDD power supply ramp down.
During 3.3 V VDD power supply ramp up (gated by LVI_2p7).
The maximum TCK operation frequency is fSYSCLK/8 for WCT1011A, fSYSCLK/16 for WCT1013A.
Value is after trim.
Guaranteed by design.
The chip may not function if the high or low pulse width is smaller than 6.25 ns.
External clock input rise time is measured from 10% to 90%.
External clock input fall time is measured from 90% to 10%.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is
optimized for 8 MHz input.
The frequency of the core system clock cannot exceed 100 MHz. If the NanoEdge PWM is available, the PLL output must be set to
400 MHz. And the minimum PLL output frequency is 200 MHz for WCT1011A, 240 MHz for WCT1013A.
This is the time required after the PLL is enabled to ensure reliable operation.
200 kHz internal RC oscillator is on WCT1011A, 32 kHz internal RC oscillator on WCT1013A.
Frequency after application of 8 MHz trimmed.
Frequency after application of 200 kHz/32 kHz trimmed.
Typical +/1.5%, maximum +/3% frequency variation for 200 kHz internal RC oscillator, and typical +/2.5%, maximum +/4%
frequency variation for 32 kHz internal RC oscillator.
Standby to run mode transition.
Power down to run mode transition. Typical 10 µs stabilization time for 200 kHz internal RC oscillator, and 14.4 µs stabilization time
for 32 kHz internal RC oscillator.
Maximum time based on expectations at cycling endoflife.
The specification is only for WCT1011A.
The specification is only for WCT1013A.
Assumes 25 MHz flash clock frequency.
Maximum times for erase parameters based on expectations at cycling endoflife.
All blocks size is 64 KB on WCT1011A, 256 KB on WCT1013A. Longer all blocks command operation time for WCT1013A.
For bytewrites to an erased FlexRAM location, the aligned word containing the byte must be erased.
Typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25°C use
WCT101XADS, Rev. 0, 09/2016
20
NXP Semiconductors
profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering Bulletin EB619.
33. Cycling endurance represents number of program/erase cycles at 40 C Tj 125 C.
34. Write endurance represents the number of writes to each FlexRAM location at 40 C Tj 125 C influenced by the cycling
endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all bytewrites to FlexRAM.
35. The ADC functions up to VDDA = 2.7 V. When VDDA is below 3.0 V, ADC specifications are not guaranteed.
36. When the input is at the VREFL level, the resulting output will be all zeros (hex 000), plus any error contribution due to offset and gain
error. When the input is at the V REFH level, the output will be all ones (hex FFF), minus any error contribution due to offset and gain
error.
37. ADC clock duty cycle is 45% ~ 55%. WCT1011A only supports the maximum ADC clock of 10 MHz and minimum ADC clock of 0.1 MHz,
and WCT1013A supports 20 MHz maximum ADC clock and 0.6 MHz minimum ADC clock.
38. Conversion range is defined for x1 gain setting. For x2 and x4 the range is 1/2 and 1/4, respectively.
39. In unipolar mode, positive input must be ensured to be always greater than negative input.
40. For WCT1011A, the first conversion takes 10 clock cycles, 8 clock cycles for the subsequent conversion; On WCT1013A, 8.5 clock
cycles for the first conversion, 6 clock cycles for the subsequent conversion.
41. For WCT1011A, the power down current of ADC is 0.1 µA, and 0.02 µA for WCT1013A.
42. For WCT1011A, the VREFH current of ADC is 190 µA, and 0.001 µA for WCT1013A.
43. INLADC/DNLADC is measured from VADCIN = VREFL to VADCIN = VREFH using Histogram method at x1 gain setting. On WCT1011A,
typical value is +/ 1.5 LSB, and maximum value +/ 2.2 LSB for INL ADC; typical value is +/ 0.5 LSB, and maximum value +/ 0.8 LSB for
DNLADC. On WCT1013A, typical value is +/ 3 LSB, and maximum value +/ 5 LSB for INL ADC; typical value is +/ 0.6 LSB, and maximum
value +/ 1 LSB for DNLADC.
44. Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 gain setting.
45. Any offchannel with 50 kHz fullscale input to the channel being sampled with DC input (isolation crosstalk).
46. Typical +/ 12 mV offset for WCT1011A, +/ 13.7 mV offset for WCT1013A.
47. Typical ENOB is 10.6 bits for WCT1011A, 9.5 bits for WCT1013A.
48. The current that can be injected into or sourced from an unselected ADC input without affecting the performance of the ADC.
49. Typical values assume VDDA = 3.0 V, Temp = 25 C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only and
are not tested in production.
50. To use the maximum ADC conversion clock frequency, the ADHSC bit must be set and the ADLPC bit must be clear.
51. The ADC supply current depends on the ADC conversion clock speed, conversion rate and the ADLPC bit (low power). For lowest
power operation the ADLPC bit should be set, the HSC bit should be clear with 1MHz ADC conversion clock speed.
52. 1 LSB = (VREFH VREFL)/2N.
53. ADC conversion clock
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