MWCT1016SFVMH

NXP Semiconductors Data Sheet: Advance Information MWCT101XS Data Sheet Key Features • Operating characteristics – Voltage range: 2.7 V to 5.5 V – Ambient temperature range: -40 °C to 105 °C for HSRUN mode, -40 °C to 125 °C for RUN mode • Arm™ Cortex-M4F core, 32-bit CPU – Supports up to 112 MHz frequency (HSRUN) with 1.25 Dhrystone MIPS per MHz – Arm Core based on the Armv7 Architecture and Thumb®-2 ISA – Integrated Digital Signal Processor (DSP) – Configurable Nested Vectored Interrupt Controller (NVIC) – Single Precision Floating Point Unit (FPU) • Clock interfaces – 4 - 40 MHz fast external oscillator (SOSC) – 48 MHz Fast Internal RC oscillator (FIRC) – 8 MHz Slow Internal RC oscillator (SIRC) – 128 kHz Low Power Oscillator (LPO) – Up to 112 MHz (HSRUN) System Phased Lock Loop (SPLL) – Up to 50 MHz DC external square wave input clock – Real Time Counter (RTC) • Power management – Low-power Arm Cortex-M4F core with excellent energy efficiency – Power Management Controller (PMC) with multiple power modes: HSRUN, RUN, STOP, VLPR, and VLPS. Note: CSEc (Security) or EEPROM writes/ erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 Mhz) to execute CSEc (Security) or EEPROM writes/erase. – Clock gating and low power operation supported on specific peripherals. Document Number MWCT101xSF Rev. 4, 08/2020 MWCT101xSF • Memory and memory interfaces – Up to 2 MB program flash memory with ECC – 64 KB FlexNVM for data flash memory with ECC and EEPROM emulation. Note: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase. – Up to 256 KB SRAM with ECC – Up to 4 KB of FlexRAM for use as SRAM or EEPROM emulation – Up to 4 KB Code cache to minimize performance impact of memory access latencies – QuadSPI with HyperBus™ support • Mixed-signal analog – Up to two 12-bit Analog-to-Digital Converter (ADC) with up to 32 channel analog inputs per module – One Analog Comparator (CMP) with internal 8-bit Digital to Analog Converter (DAC) • Debug functionality – Serial Wire JTAG Debug Port (SWJ-DP) combines – Debug Watchpoint and Trace (DWT) – Instrumentation Trace Macrocell (ITM) – Test Port Interface Unit (TPIU) – Flash Patch and Breakpoint (FPB) Unit • Human-machine interface (HMI) – Up to 89 GPIO pins with interrupt functionality – Non-Maskable Interrupt (NMI) This document contains information on a pre-production product. Specifications and pre-production information herein are subject to change without notice. • Communications interfaces – Up to three Low Power Universal Asynchronous Receiver/Transmitter (LPUART/LIN) modules with DMA support and low power availability – Up to three Low Power Serial Peripheral Interface (LPSPI) modules with DMA support and low power availability – Up to two Low Power Inter-Integrated Circuit (LPI2C) modules with DMA support and low power availability – Up to three FlexCAN modules (with optional CAN-FD support) – FlexIO module for emulation of communication protocols and peripherals (UART, I2C, SPI, I2S, LIN, PWM, etc). • Safety and Security – Cryptographic Services Engine (CSEc) implements a comprehensive set of cryptographic functions as described in the SHE (Secure Hardware Extension) Functional Specification. Note: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device will need to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase. – 128-bit Unique Identification (ID) number – Error-Correcting Code (ECC) on flash and SRAM memories – System Memory Protection Unit (System MPU) – Cyclic Redundancy Check (CRC) module – Internal watchdog (WDOG) – External Watchdog monitor (EWM) module • Timing and control – Up eight independent 16-bit FlexTimers (FTM) module, offering up to 64 standard channels (IC/OC/PWM) – One 16-bit Low Power Timer (LPTMR) with flexible wake up control – Two Programmable Delay Blocks (PDB) with flexible trigger system – One 32-bit Low Power Interrupt Timer (LPIT) with 4 channels – 32-bit Real Time Counter (RTC) • I/O and package – 64-pin LQFP, 100-pin LQFP, 100-pin MAPBGA package options • 16 channel DMA with up to 63 request sources using DMAMUX MWCT101XS Data Sheet, Rev. 4, 08/2020 2 NXP Semiconductors Table of Contents 1 Block diagram.................................................................................... 4 2 Feature comparison............................................................................ 5 3 Ordering parts.....................................................................................7 4 6.2.5 6.3 Memory and memory interfaces................................................27 6.3.1 specifications................................................................27 3.2 Ordering information ................................................................ 8 6.3.1.1 General............................................................................................... 9 Flash timing specifications — commands................................................ 27 6.3.1.2 4.2 Voltage and current operating requirements..............................10 6.3.2 4.3 Thermal operating characteristics..............................................11 Reliability specifications..........................30 QuadSPI AC specifications..........................................31 6.4 Analog modules......................................................................... 35 4.4 Power and ground pins.............................................................. 11 6.4.1 ADC electrical specifications...................................... 35 4.5 LVR, LVD and POR operating requirements............................13 6.4.1.1 12-bit ADC operating conditions............. 35 4.6 Power mode transition operating behaviors.............................. 13 6.4.1.2 12-bit ADC electrical characteristics....... 37 4.7 Power consumption................................................................... 14 6.4.2 4.8 ESD handling ratings.................................................................17 CMP with 8-bit DAC electrical specifications............ 39 6.5 Communication modules........................................................... 43 4.9 EMC radiated emissions operating behaviors........................... 17 6.5.1 LPUART electrical specifications............................... 43 I/O parameters....................................................................................17 6.5.2 LPSPI electrical specifications.................................... 43 5.1 AC electrical characteristics...................................................... 17 6.5.3 LPI2C electrical specifications.................................... 49 5.2 General AC specifications......................................................... 18 6.5.4 FlexCAN electical specifications.................................50 5.3 DC electrical specifications at 3.3 V Range.............................. 18 6.5.5 Clockout frequency......................................................50 5.4 DC electrical specifications at 5.0 V Range.............................. 19 6.6 Debug modules.......................................................................... 50 5.5 AC electrical specifications at 3.3 V range .............................. 20 6.6.1 SWD electrical specofications .................................... 50 5.6 AC electrical specifications at 5 V range ................................. 21 6.6.2 Trace electrical specifications......................................52 5.7 Standard input pin capacitance.................................................. 22 6.6.3 JTAG electrical specifications..................................... 53 5.8 Device clock specifications....................................................... 22 6 Flash memory module (FTFC) electrical 3.1 Determining valid orderable parts ............................................ 7 4.1 Absolute maximum ratings........................................................9 5 SPLL electrical specifications .....................................27 7 Thermal attributes.............................................................................. 56 Peripheral operating requirements and behaviors.............................. 23 7.1 Description.................................................................................56 6.1 System modules......................................................................... 23 7.2 Thermal characteristics..............................................................56 6.2 Clock interface modules............................................................ 23 7.3 General notes for specifications at maximum junction 6.2.1 External System Oscillator electrical specifications....23 6.2.2 External System Oscillator frequency specifications . 25 6.2.3 System Clock Generation (SCG) specifications.......... 26 6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications............................ 26 6.2.3.2 Slow internal RC oscillator (SIRC) temperature................................................................................ 59 8 Dimensions.........................................................................................60 8.1 Obtaining package dimensions ................................................. 60 9 Pinouts................................................................................................61 9.1 Package pinouts and signal descriptions....................................61 10 Revision History.................................................................................61 electrical specifications ........................... 26 6.2.4 Low Power Oscillator (LPO) electrical specifications ......................................................................................27 MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 3 Block diagram 1 Block diagram The figure below shows a superset high level architecture block diagram of the device. Other devices within the family have a subset of the features. See Feature comparison for chip specific values. Async Trace port JTAG & Serial Wire Arm Cortex M4F Core MCM TPIU PPB SWJ-DP NVIC AHB-AP FPU FPB DSP DWT System ICODE DCODE LMEM Upper region EIM LMEM controller Lower region System MPU1 Mux Main SRAM2 AWIC ITM System MPU1 DMA MUX LPO 128 kHz eDMA FIRC 48 MHz SIRC 8 MHz SOSC 4-40 MHz 8-40 MHz SPLL TCD 512B Code Cache M3 M2 M1 M0 S2 S1 Clock generation Crossbar switch (AXBS-Lite) S3 S0 System MPU1 Mux System MPU1 QuadSPI GPIO Flash memory controller Peripheral bus controller WDOG ERM 12-bit ADC EWM CMP 8-bit DAC LPUART CRC TRGMUX LPSPI LPI2C FlexIO Low Power Timer FlexCAN FlexTimer PDB RTC LPIT FlexRAM/ SRAM LPIT QSPI 1: On this device, NXP’s system MPU implements the safety mechanisms to prevent masters from accessing restricted memory regions. This system MPU provides memory protection at the level of the Crossbar Switch. Each Crossbar master (Core, DMA) can be assigned different access rights to each protected memory region. The Arm M4 core version in this family does not integrate the Arm Core MPU, which would concurrently monitor only core-initiated memory accesses. In this document, the term MPU refers to NXP’s system MPU. 2: For the device-specific sizes, see the "On-chip SRAM sizes" table in the "Memories and Memory Interfaces" chapter of the MWCT101xS Series Reference Manual. 3: CSEc (Security) or EEPROM writes/erase will trigger error flags in HSRUN mode (112 MHz) because this use case is not allowed to execute simultaneously. The device needs to switch to RUN mode (80 MHz) to execute CSEc (Security) or EEPROM writes/erase. Code flash memory Data flash memory CSEc3 Device architectural IP on all MWCT101xS devices Key: Peripherals present on all MWCT101xS devices Peripherals present on selected MWCT101xS devices (see the "Feature Comparison" section in the RM) Figure 1. High-level architecture diagram for the MWCT101xS family MWCT101XS Data Sheet, Rev. 4, 08/2020 4 NXP Semiconductors Feature comparison 2 Feature comparison The following figure summarizes the memory and package options for the MWCT101xS series and demonstrates where this device fits within the overall series. All devices which share a common package are pin-to-pin compatible. NOTE Availability of peripherals depends on the pin availability in a particular package. For more information see IO Signal Description Input Multiplexing sheet(s) attached with Reference Manual. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 5 Feature comparison MWCT101xS Parameter MWCT1014S MWCT1015S MWCT1016S Arm® Cortex™-M4F Core up to 112 MHz (HSRUN) Frequency IEEE-754 FPU 2 HW security module (CSEc)1 1x CRC module capable up to ASIL-B ISO 26262 Peripheral speed up to 112 MHz (HSRUN) System Crossbar DMA EWM Memory protection unit FIRC CMU Watchdog 1x Low power modes HSRUN mode1 up to 89 Number of I/Os up to 89 up to 89 2.7 - 5.5 V Single supply voltage Operating temperature (Ta) Temperature ambient Flash -40 to +105ºC / +125ºC 1 MB 512 KB 2 MB3 Error correction code (ECC) Memory System RAM (including FlexRAM) 128 KB 64 KB FlexRAM (also available as system RAM) 4 KB Cache 4 KB EEPROM emulated by FlexRAM1 4 KB (up to 64 KB D-Flash) Timer Low power interrupt timer 1x 4x (32) Low power timer (LPTMR) 1x Real time counter (RTC) 1x Analog 1x (64) 1x (73) 1x (81) 12-bit SAR ADC (1 MSPS each) 2x (16) 2x (24) 2x (32) Comparator with 8-bit DAC 1x Low power UART/LIN Communication 8x (64) Trigger mux (TRGMUX) 3x (Supports LIN protocol versions 1.3, 2.0, 2.1, 2.2A and SAE J2602) Low power SPI 3x Low power I2C FlexCAN (CAN-FD ISO/CD 11898-1) Debug & trace 3x (1x with FD) 3x2 (2x with FD) 3x (3x with FD) 1x SWD, Ecosystem (IDE, compiler, debugger) Packages6 2x 1x FlexIO (8 pins configurable as UART, SPI, I2C, I2S) IDEs 6x (48) 2x Programmable delay block (PDB) Other See footnote 4 QuadSPI incl. HyperBus™ External memory interface FlexTimer (16-bit counter) 8 channels 256 KB JTAG5 (ITM, SWV, SWO) SWD, JTAG (ITM, SWV, SWO), ETM NXP S32 Design Studio + GCC + GHS + Lauterbach LQFP-64 LQFP-100 LQFP-100 BGA-100 BGA-100 LEGEND: Not implemented Available on the device 1 No write or erase access to Flash module, including Security (CSEc) and EEPROM commands, are allowed when device is running at HSRUN mode (112MHz) or VLPR mode. 2 Option with No CSEc and CAN-FD is also available for MWCT1015S 3 Available when EEEPROM, CSEc and Data Flash are not used. Else only up to 1,984 KB is available for Program Flash. 4 4 KB (up to 512 KB D-Flash as a part of 2M Flash). Up to 64 KB of flash is used as EEPROM backup and the remaining 448 KB of the last 512 KB block can be used as Data flash or Program flash. See chapter FTFC for details. 5 Only for Boundary Scan Register 6 See Dimensions for package drawing MWCT101XS Data Sheet, Rev. 4, 08/2020 6 NXP Semiconductors Figure 2. MWCT101xS product series comparison Ordering parts 3 Ordering parts 3.1 Determining valid orderable parts To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search. NOTE Not all part number combinations exist MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 7 Ordering parts 3.2 Ordering information M/P WCT 1 0 1 4 S F V LH P N R Product status Product line Generation Config Power Class Memory Size Application Core Platform Temperature Package Features Includes stack Tape and Reel Product status P: Pre Qualification M: Fully Qualified Package Power Class 0=5W 1 = 15 W 2 = 60 W 3 =200 W Pins LQFP BGA 64 LH - 100 LL MH Memory size (Flash) Product line WCT: Wireless Charging Technology M4F 4 5 6 512 K 1M 2M Generation 1: 1st product Gen 2: 2nd product Gen Application Blank =Customer A = Auto/Industr S = A + AUTOSAR Config 0 = Standard 1 = Premium Core platform F: Arm Cortex M4F Features P = No CAN-FD and CSEc Includes stack Blank = No stack N = NFC Tape and Reel R: Tape and Reel Temperature V: -40C to 105C Figure 3. Ordering information MWCT101XS Data Sheet, Rev. 4, 08/2020 8 NXP Semiconductors General 4 General 4.1 Absolute maximum ratings • • • • NOTE Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in the following table for specific conditions. Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. All the limits defined in the datasheet specification must be honored together and any violation to any one or more will not guarantee desired operation. Unless otherwise specified, all maximum and minimum values in the datasheet are across process, voltage, and temperature. Table 1. Absolute maximum ratings Symbol Conditions1 Parameter 2 VDD 2.7 V - 5. 5V input supply voltage VREFH — Min Max -0.3 5.8 3 Unit V 5.8 3 V 3.3 V / 5.0 V ADC high reference voltage — -0.3 Continuous DC input current (positive / negative) that can be injected into an I/O pin — -3 +3 mA Continuous DC Voltage on any I/O pin with respect to VSS — -0.8 5.85 V Sum of absolute value of injected currents on all the pins (Continuous DC limit) — — 30 mA Tramp6 ECU supply ramp rate — 0.5 V/min 500 V/ms — Tramp_MCU7 4 IINJPAD_DC_ABS VIN_DC IINJSUM_DC_ABS MCU supply ramp rate — 0.5 V/min 100 V/ms — TA8 Ambient temperature — -40 125 °C TSTG Storage temperature — -55 165 °C — 9 VIN_TRANSIENT Transient overshoot voltage allowed on I/O pin beyond VIN_DC limit — 6.8 V 1. All voltages are referred to VSS unless otherwise specified. 2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details. 3. 60 s lifetime – No restrictions i.e. The part can switch. 10 hours lifetime – Device in reset i.e. The part cannot switch. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 9 General 4. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible. 5. While respecting the maximum current injection limit 6. This is the Electronic Control Unit (ECU) supply ramp rate and not directly the MCU ramp rate. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions. 7. This is the MCU supply ramp rate, and the ramp rate assumes that the HW design guidelines in AN5426 are followed. Limit applies to both maximum absolute maximum ramp rate and typical operating conditions. 8. TJ (Junction temperature)=135 °C. Assumes TA=125 °C for RUN mode TJ (Junction temperature)=125 °C. Assumes TA=105 °C for HSRUN mode • Assumes maximum θJA for 2s2p board. See Thermal characteristics 9. 60 seconds lifetime; device in reset (no outputs enabled/toggling) 4.2 Voltage and current operating requirements NOTE Device functionality is guaranteed up to the LVR assert level; however, electrical performance of 12-bit ADC, CMP with 8bit DAC, IO electrical characteristics, and communication modules electrical characteristics would be degraded when voltage drops below 2.7 V Table 2. Voltage and current operating requirements 1 Symbol Description Min. Max. Unit Notes VDD2 Supply voltage 2.73 5.5 V 4 0 0.1 V 2.7 5.5 V 4 VDD_OFF Voltage allowed to be developed on VDD pin when it is not powered from any external power supply source. VDDA Analog supply voltage VDD – VDDA – 0.1 0.1 V 4 VREFH VDD-to-VDDA differential voltage ADC reference voltage high 2.7 VDDA + 0.1 V 5 VREFL ADC reference voltage low -0.1 0.1 V Open drain pullup voltage level VDD VDD V VODPU 7 IINJPAD_DC_OP Continuous DC input current (positive / negative) that can be injected into an I/O pin -3 +3 mA IINJSUM_DC_OP Continuous total DC input current that can be injected across all I/O pins such that there's no degradation in accuracy of analog modules: ADC and ACMP (See section Analog Modules) — 30 mA 6 1. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. 2. As VDD varies between the minimum value and the absolute maximum value the analog characteristics of the I/O and the ADC will both change. See section I/O parameters and ADC electrical specifications respectively for details. 3. MWCT1016S will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged MWCT1016S is guaranteed to operate from 2.97 V. All other MWCT101xS family devices operate from 2.7 V in all modes. 4. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR ADC. MWCT101XS Data Sheet, Rev. 4, 08/2020 10 NXP Semiconductors General 5. VREFH should always be equal to or less than VDDA + 0.1 V and VDD + 0.1 V 6. Open drain outputs must be pulled to VDD. 7. When input pad voltage levels are close to VDD or VSS, practically no current injection is possible. 4.3 Thermal operating characteristics Table 3. Thermal operating characteristics for 64-pin LQFP and 100-pin LQFP and MAPBGA packages Symbol Parameter TA C-Grade Part Value Ambient temperature under bias TJ C-Grade Part Junction temperature under bias TA V-Grade Part Min. Typ. Max. −40 — 851 ℃ — 1051 ℃ — 1051 ℃ ℃ −40 Ambient temperature under bias Unit −40 TJ V-Grade Part Junction temperature under bias −40 — 1251 TA M-Grade Part Ambient temperature under bias −40 — 1252 ℃ TJ M-Grade Part Junction temperature under bias −40 — 1352 ℃ 1. Values mentioned are measured at ≤ 112 MHz in HSRUN mode. 2. Values mentioned are measured at ≤ 80 MHz in RUN mode. 4.4 Power and ground pins VDD VREFL/VSSA/VSS VREFH VREFL 100 LQFP Package VDD C DEC CREF VSS C DEC VREFH VDDA C DEC VSS VSS VSSA/VSS VDD CREF VDD 64 LQFP Package VDDA C DEC C DEC VDD C DEC VSS VDD C DEC C DEC NOTE: VDD and VDDA must be shorted to a common source on PCB Figure 4. Pinout decoupling C DEC V CREF, 4, 5 SS VDDA CREF C C DEC VREFH VREFL VSSA/VSS VSS VDD VDD Description Min. 3 Typ. Max. Unit ADC reference high decoupling capacitance 70 100 — nF 144 LQFP Package VDD continues on the next page... Table VSS MWCT101XS Data Sheet, Rev. 4, 08/2020 VDD VSS VDD VSS 11 DD NXP Semiconductors VSS C DEC Symbol DEC C DEC Table 4. Supplies decoupling capacitors 1, 2 General Table 4. Supplies decoupling capacitors 1, 2 (continued) Symbol Description Min. 3 Typ. Max. Unit CDEC5, 6, 7 Recommended decoupling capacitance 70 100 — nF VREFH VREFL VSSA VDD VDDA 1. VDD and VDDA must be shorted to a common source on PCB. The differential voltage between VDD and VDDA is for RF-AC only. Appropriate decoupling capacitors to be used to filter noise on the supplies. See application note AN5032 for reference supply design for SAR ADC. All VSS pins should be connected to common ground at the PCB level. 2. All decoupling capacitors must be low ESR ceramic capacitors (for example X7R type). 3. Minimum recommendation is after considering component aging and tolerance. 4. For improved performance, it is recommended to use 10 μF, 0.1 μF and 1 nF capacitors in parallel. 5. All decoupling capacitors should be placed as close as possible to the corresponding supply and ground pins. 6. Contact your local Field Applications Engineer for details on best analog routing practices. 7. The filtering used for decoupling the device supplies must comply with the following best practices rules: • The protection/decoupling capacitors must be on the path of the trace connected to that component. • No trace exceeding 1 mm from the protection to the trace or to the ground. • The protection/decoupling capacitors must be as close as possible to the input pin of the device (maximum 2 mm). • The ground of the protection is connected as short as possible to the ground plane under the integrated circuit. VOSC = 3.3 V nominal FIRC SIRC SPLL SOSC ADC CMP VCORE = 1.2 V/1.4 V nominal VFlash = 3.3 V nominal PMC Pads LV SOG GPIO VSS Flash System RAM TCD RAM I/D Cache EEE RAM *Note: VSSA and VSS are shorted at package level Figure 5. Power diagram MWCT101XS Data Sheet, Rev. 4, 08/2020 12 NXP Semiconductors General 4.5 LVR, LVD and POR operating requirements Table 5. VDD supply LVR, LVD and POR operating requirements Symbol Description Min. Typ. Max. Unit VPOR Rising and falling VDD POR detect voltage 1.1 1.6 2.0 V VLVR LVR falling threshold (RUN, HSRUN, and STOP modes) 2.50 2.58 2.7 V — 45 — mV LVR falling threshold (VLPS/VLPR modes) 1.97 2.22 2.44 V Falling low-voltage detect threshold 2.8 2.875 3 V LVD hysteresis — 50 — mV 4.19 4.305 4.5 V — 75 — mV 0.97 1.00 1.03 V VLVR_HYST VLVR_LP VLVD VLVD_HYST VLVW VLVW_HYST VBG LVR hysteresis Falling low-voltage warning threshold LVW hysteresis Bandgap voltage reference Notes 1 1 1 1. Rising threshold is the sum of falling threshold and hysteresis voltage. 4.6 Power mode transition operating behaviors All specifications in the following table assume this clock configuration: • RUN Mode: • Clock source: FIRC • SYS_CLK/CORE_CLK = 48 MHz • BUS_CLK = 48 MHz • FLASH_CLK = 24 MHz • HSRUN Mode: • Clock source: SPLL • SYS_CLK/CORE_CLK = 112 MHz • BUS_CLK = 56 MHz • FLASH_CLK = 28 MHz • VLPR Mode: • Clock source: SIRC • SYS_CLK/CORE_CLK = 4 MHz • BUS_CLK = 4 MHz • FLASH_CLK = 1 MHz • STOP1/STOP2 Mode: • Clock source: FIRC • SYS_CLK/CORE_CLK = 48 MHz MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 13 General • BUS_CLK = 48 MHz • FLASH_CLK = 24 MHz • VLPS Mode: All clock sources disabled. Table 6. Power mode transition operating behaviors Symbol tPOR Description Min. Typ. Max. Unit After a POR event, amount of time from the point VDD reaches 2.7 V to execution of the first instruction across the operating temperature range of the chip. — 325 — μs VLPS → RUN 8 — 17 μs STOP1 → RUN 0.07 0.075 0.08 μs STOP2 → RUN 0.07 0.075 0.08 μs VLPR → RUN 19 — 26 μs VLPR → VLPS 5.1 5.7 6.5 μs VLPS → VLPR 18.8 23 27.75 μs RUN → Compute operation 0.72 0.75 0.77 μs HSRUN → Compute operation 0.3 0.31 0.35 μs RUN → STOP1 0.35 0.38 0.4 μs RUN → STOP2 0.2 0.23 0.25 μs RUN → VLPS 0.3 0.35 0.4 μs RUN → VLPR 3.5 3.8 5 μs VLPS → Asynchronous DMA Wakeup 105 110 125 μs 1 1.1 1.3 μs STOP1 → Asynchronous DMA Wakeup STOP2 → Asynchronous DMA Wakeup 1 1.1 1.3 μs Pin reset → Code execution — 214 — μs NOTE HSRUN should only be used when frequencies in excess of 80 MHz are required. When using 80 MHz and below, RUN mode is the recommended operating mode. 4.7 Power consumption The following table shows the power consumption targets for the device in various modes of operation. Attached MWCT101xS_Power_Modes _Configuration.xlsx details the modes used in gathering the power consumption data stated in the following table Table 7. For full functionality refer to table: Module operation in available low power modes of the Reference Manual. MWCT101XS Data Sheet, Rev. 4, 08/2020 14 NXP Semiconductors NXP Semiconductors Chip/Device 1. 125 105 3990 2945 Max Max 560 Typ 336 1660 Typ Max 85 38 3358 Typ Max 2004 Max 25 125 419 Typ 974 Max 105 207 Typ 85 37 1960 Typ Max 850 25 125 256 Typ Max 359 Max 105 150 Typ 85 Ambient Temperature (°C) Typ 29.8 Peripherals disabled 6 25 Peripherals enabled 4166 2970 577 1736 357 54 3380 2017 422 981 209 47 1998 900 273 384 159 39.1 Peripherals disabled 6.00 4.40 2.49 3.48 2.30 2.17 5.28 4.06 1.99 3.32 1.79 1.57 3.18 2.65 1.80 2.60 1.72 1.48 Peripherals enabled 6.08 4.47 2.54 3.55 2.35 2.20 5.38 4.13 2.04 3.38 1.83 1.61 3.25 2.70 2.10 2.65 1.85 1.50 23.4 18.0 10.9 14.5 10.1 8.5 22.6 17.1 9.8 12.7 8.9 8 12.9 10.3 7.8 9.2 7.2 7 24.5 19.0 11.9 15.6 11.1 9.6 23.7 18.3 11 13.9 10.1 9.2 13.8 11.1 8.5 9.9 8.1 7.7 STOP2 (mA) Peripherals disabled 44.3 38.4 29.8 34.8 29.1 27.6 40.2 34.1 25.3 29.3 24.4 23.4 26.9 23.9 20.6 23.2 20.4 19.7 Peripherals enabled 52.5 46.8 37.8 43.6 37.0 34.9 48.8 42.6 33.4 37.9 32.4 31.4 33.6 30.6 27.4 29.6 27.1 26.9 Peripherals disabled 50.9 44.9 37.6 41.9 36.8 35.5 47.3 41.3 32.5 36.7 31.5 30.5 35 30.3 26.6 29.3 26.1 25.1 61.3 55.3 47.5 53.9 46.6 45.3 57.4 51.4 42.2 47 41.3 40.2 40.3 37.3 33.8 36.2 33.5 33.3 Peripherals enabled RUN@64 MHz (mA) RUN@80 MHz (mA) 57.5 51.6 45.2 48.7 43.4 42.1 52.8 46.9 38.1 42.4 37.2 36.2 38.7 35.6 31.2 34.8 30.5 30.2 Peripherals disabled RUN@48 MHz (mA) 71.6 66.8 61.5 65.1 59.9 57.7 64.8 58.8 49.6 54.4 48.7 47.6 46.8 43.5 40.5 42.1 40 39.6 HSRUN@112 MHz (mA) 4 NA 73.6 63.8 70.4 62.9 60.3 NA 65.7 54.4 60.3 53.3 52 NA 47.9 44.8 46.3 43.9 43.3 NA 97.4 89.1 96.1 88.7 83.3 NA 82.8 70.8 78 69.8 68.3 NA 61.3 57.1 59.7 56.1 55.6 719 645 565 609 543 526 660 587 477 530 465 452 484 445 390 435 381 378 Idd/MHz (μA/MHz)5 Typical current numbers are indicative for typical silicon process and may vary based on the silicon distribution and user configuration. Typical conditions assumes VDD = VDDA = VREFH = 5 V, temperature = 25 °C and typical silicon process unless otherwise stated. All output pins are floating and On-chip pulldown is enabled for all unused input pins. MWCT1016S7 MWCT1015S MWCT1014S STOP1 (mA) Peripherals enabled VLPR (mA) Peripherals disabled VLPS (μA)2, 3 Peripherals enabled Table 7. Power consumption (Typicals unless stated otherwise) 1 General MWCT101XS Data Sheet, Rev. 4, 08/2020 15 16 3. 4. 5. 6. 7. 2. This is an average based on the use case described in the Comparator section, whereby the analog sampling is taking place periodically, with a mechanism to only enable the DAC as required. The numbers quoted assumes that only a single ANLCMP is active and the others are disabled Current numbers are for reduced configuration and may vary based on user configuration and silicon process variation. HSRUN mode must not be used at 125°C. Max ambient temperature for HSRUN mode is 105°C. Values mentioned are measured at RUN@80 MHz with peripherals disabled. With PMC_REGSC[CLKBIASDIS] set to 1. See Reference Manual for details. The MWCT1016S data points assume that QuadSPI etc. are inactive. General MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors I/O parameters 4.8 ESD handling ratings Symbol Description VHBM Electrostatic discharge voltage, human body model VCDM Electrostatic discharge voltage, charged-device model ILAT Min. Max. Unit Notes − 4000 4000 V 1 2 All pins except the corner pins − 500 500 V Corner pins only − 750 750 V Latch-up current at ambient temperature of 125 °C − 100 100 mA 3 1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM). 2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components. 3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test. 4.9 EMC radiated emissions operating behaviors EMC measurements to IC-level IEC standards are available from NXP on request. 5 I/O parameters 5.1 AC electrical characteristics Unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. Figure 6. Input signal measurement reference MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 17 I/O parameters 5.2 General AC specifications These general purpose specifications apply to all signals configured for GPIO, UART, and timers. Table 8. General switching specifications Symbol WFRST WNFRST Description Min. Max. Unit Notes GPIO pin interrupt pulse width (digital glitch filter disabled) — Synchronous path 1.5 — Bus clock cycles 1, 2 GPIO pin interrupt pulse width (digital glitch filter disabled, passive filter disabled) — Asynchronous path 50 — ns 3 RESET input filtered pulse — 10 ns 4 Maximum of (100 ns, bus clock period) — ns 5 RESET input not filtered pulse 1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. The greater of synchronous and asynchronous timing must be met. 3. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be recognized. 4. Maximum length of RESET pulse which will be filtered by internal filter. 5. Minimum length of RESET pulse, guaranteed not to be filtered by the internal filter. This number depends on bus clock period also. For example, in VLPR mode bus clock is 4 MHz, which make clock period of 250 ns. In this case, minimum pulse width which will cause reset is 250 ns. For faster bus clock frequencies which have clock period less than 100 ns, the minimum pulse width not filtered will be 100 ns. 5.3 DC electrical specifications at 3.3 V Range NOTE For details on the pad types defined in Table 9 and Table 10, see Reference Manual section IO Signal Table and IO Signal Description Input Multiplexing sheet(s) attached with Reference Manual. Table 9. DC electrical specifications at 3.3 V Range Symbol Parameter Value Min. Typ. Unit Notes Max. VDD I/O Supply Voltage 2.7 3.3 4 V 1 Vih Input Buffer High Voltage 0.7 × VDD — VDD + 0.3 V 2 Vil Input Buffer Low Voltage VSS − 0.3 — 0.3 × VDD V 3 0.06 × VDD — — V 3.5 — — mA Vhys IohGPIO Input Buffer Hysteresis I/O current source capability measured when pad Voh = (VDD − 0.8 V) Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 18 NXP Semiconductors I/O parameters Table 9. DC electrical specifications at 3.3 V Range (continued) Symbol Parameter Value Unit Notes Min. Typ. Max. I/O current sink capability measured when pad Vol = 0.8 V 3 — — mA IohGPIO-HD_DSE_1 I/O current source capability measured when pad Voh = (VDD − 0.8 V) 14 — — mA 4 IolGPIO-HD_DSE_1 I/O current sink capability measured when pad Vol = 0.8 V 12 — — mA 4 IohGPIO-FAST_DSE_0 I/O current sink capability measured when pad Voh=VDD-0.8 V 9.5 — — mA 5 IolGPIO-FAST_DSE_0 I/O current sink capability measured when pad Vol = 0.8 V 10 — — mA 5 IohGPIO-FAST_DSE_1 I/O current sink capability measured when pad Voh=VDD-0.8 V 16 — — mA 5 IolGPIO-FAST_DSE_1 I/O current sink capability measured when pad Vol = 0.8 V 15.5 — — mA 5 — — 100 mA IohGPIO-HD_DSE_0 IolGPIO IolGPIO-HD_DSE_0 IOHT Output high current total for all ports IIN Input leakage current (per pin) for full temperature range at VDD = 3.3 V 6 All pins other than high drive port pins 0.005 0.5 μA High drive port pins 0.010 0.5 μA RPU Internal pullup resistors 20 60 kΩ 7 RPD Internal pulldown resistors 20 60 kΩ 8 1. MWCT1016S will operate from 2.7 V when executing from internal FIRC. When the PLL is engaged MWCT1016S is guaranteed to operate from 2.97 V. All other MWCT101xS family devices operate from 2.7 V in all modes. 2. For reset pads, same Vih levels are applicable 3. For reset pads, same Vil levels are applicable 4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard value given above. 5. For refernce only. Run simulations with the IBIS model and custom board for accurate results. 6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only. For details refer to MWCT101xS_IO_Signal_Description_Input_Multiplexing.xlsx attached with the Reference Manual. 7. Measured at input V = VSS 8. Measured at input V = VDD 5.4 DC electrical specifications at 5.0 V Range Table 10. DC electrical specifications at 5.0 V Range Symbol Parameter VDD I/O Supply Voltage Vih Input Buffer High Voltage Value Unit Min. Typ. Max. 4 — 5.5 V 0.65 x VDD — VDD + 0.3 V Notes 1 Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 19 I/O parameters Table 10. DC electrical specifications at 5.0 V Range (continued) Symbol Parameter Value Unit Notes 2 Min. Typ. Max. Input Buffer Low Voltage VSS − 0.3 — 0.35 x VDD V Input Buffer Hysteresis 0.06 x VDD — — V Ioh_Standard I/O current source capability measured when pad Voh= (VDD - 0.8 V) 5 — — mA Iol_Standard I/O current sink capability measured when pad Vol= 0.8 V 5 — — mA Vil Vhys Ioh_Strong I/O current source capability measured when pad Voh = VDD - 0.8 V 20 — — mA 3, 4 Iol_Strong I/O current sink capability measured when pad Vol = 0.8 V 20 — — mA 4, 5 IOHT Output high current total for all ports — — 100 mA IIN Input leakage current (per pin) for full temperature range at VDD = 5.5 V 6 All pins other than high drive port pins 0.005 0.5 μA High drive port pins 0.010 0.5 μA RPU Internal pullup resistors 20 50 kΩ 7 RPD Internal pulldown resistors 20 50 kΩ 8 1. For reset pads, same Vih levels are applicable 2. For reset pads, same Vil levels are applicable 3. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_Standard value given above. 4. The strong pad I/O pin is capable of switching a 50 pF load at up to 40 MHz. 5. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_Standard value given above. 6. Several I/O have both high drive and normal drive capability selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only. For details refer to MWCT101xS_IO_Signal_Description_Input_Multiplexing.xlsx attached with the Reference Manual. 7. Measured at input V = VSS 8. Measured at input V = VDD 5.5 AC electrical specifications at 3.3 V range Table 11. AC electrical specifications at 3.3 V Range Symbol tRFGPIO tRFGPIO-HD DSE NA 0 Rise time (nS) 1 Fall time (nS) 1 Capacitance (pF) 2 Min. Max. Min. Max. 3.2 14.5 3.4 15.7 25 5.7 23.7 6.0 26.2 50 20.0 80.0 20.8 88.4 200 3.2 14.5 3.4 15.7 25 Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 20 NXP Semiconductors I/O parameters Table 11. AC electrical specifications at 3.3 V Range (continued) Symbol DSE 1 tRFGPIO-FAST 0 1 Rise time (nS) 1 Fall time (nS) 1 Capacitance (pF) 2 Min. Max. Min. Max. 5.7 23.7 6.0 26.2 50 20.0 80.0 20.8 88.4 200 1.5 5.8 1.7 6.1 25 2.4 8.0 2.6 8.3 50 6.3 22.0 6.0 23.8 200 0.6 2.8 0.5 2.8 25 3.0 7.1 2.6 7.5 50 12.0 27.0 10.3 26.8 200 0.4 1.3 0.38 1.3 25 1.5 3.8 1.4 3.9 50 7.4 14.9 7.0 15.3 200 1. For reference only. Run simulations with the IBIS model and your custom board for accurate results. 2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different, for example for QSPI etc. . For protocol specific AC specifications, see respective sections. 5.6 AC electrical specifications at 5 V range Table 12. AC electrical specifications at 5 V Range Symbol tRFGPIO tRFGPIO-HD DSE NA 0 1 tRFGPIO-FAST 0 1 Rise time (nS)1 Fall time (nS) 1 Capacitance (pF) 2 Min. Max . Min. Max. 2.8 9.4 2.9 10.7 25 5.0 15.7 5.1 17.4 50 17.3 54.8 17.6 59.7 200 2.8 9.4 2.9 10.7 25 5.0 15.7 5.1 17.4 50 17.3 54.8 17.6 59.7 200 1.1 4.6 1.1 5.0 25 2.0 5.7 2.0 5.8 50 5.4 16.0 5.0 16.0 200 0.42 2.2 0.37 2.2 25 2.0 5.0 1.9 5.2 50 9.3 18.8 8.5 19.3 200 0.37 0.9 0.35 0.9 25 1.2 2.7 1.2 2.9 50 6.0 11.8 6.0 12.3 200 1. For reference only. Run simulations with the IBIS model and your custom board for accurate results. 2. Maximum capacitances supported on Standard IOs. However interface or protocol specific specifications might be different, for example for QSPI etc. . For protocol specific AC specifications, see respective sections. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 21 I/O parameters 5.7 Standard input pin capacitance Table 13. Standard input pin capacitance Symbol CIN_D Description Input capacitance: digital pins Min. Max. Unit — 7 pF NOTE Please refer to External System Oscillator electrical specifications for EXTAL/XTAL pins. 5.8 Device clock specifications Table 14. Device clock specifications 1 Symbol Description High Speed run Max. Unit fSYS System and core clock — 112 MHz fBUS Bus clock — 56 MHz — 28 MHz — 80 MHz — 404 MHz — 26.67 MHz fFLASH Flash clock Normal run mode (MWCT101xS series) fSYS fBUS fFLASH System and core clock Bus clock Flash clock VLPR 1. 2. 3. 4. 5. Min. mode2 3 mode5 fSYS System and core clock — 4 MHz fBUS Bus clock — 4 MHz fFLASH Flash clock — 1 MHz fERCLK External reference clock — 16 MHz Refer to the section Feature comparison for the availability of modes and other specifications. Only available on some devices. See section Feature comparison. With SPLL as system clock source. 48 MHz when fSYS is 48 MHz The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any other module. MWCT101XS Data Sheet, Rev. 4, 08/2020 22 NXP Semiconductors Peripheral operating requirements and behaviors 6 Peripheral operating requirements and behaviors 6.1 System modules There are no electrical specifications necessary for the device's system modules. 6.2 Clock interface modules 6.2.1 External System Oscillator electrical specifications MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 23 Clock interface modules Single input comparator (EXTAL WAVE) ref_clk Mux Differential input comparator (HG/LP mode) Peak detector LP mode Driver (HG/LP mode) Pull down resistor (OFF) ESD PAD 280 ohms ESD PAD 40 ohms XTAL pin EXTAL pin Series resistor for current limitation 1M ohms Feedback Resistor Crystal or resonator C1 C2 Figure 7. Oscillator connections scheme Table 15. External System Oscillator electrical specifications Symbol Description Min. Typ. Max. Unit gmXOSC Crystal oscillator transconductance 4-8 MHz 2.2 — 13.7 mA/V 8-40 MHz 16 — 47 mA/V VIL Input low voltage — EXTAL pin in external clock mode VIH Input high voltage — EXTAL pin in external clock mode C1 Notes VSS — 0.35 * VDD V 0.7 * VDD — VDD V EXTAL load capacitance — — — 1 C2 XTAL load capacitance — — — 1 RF Feedback resistor Low-gain mode (HGO=0) 2 — — — MΩ Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 24 NXP Semiconductors Clock interface modules Table 15. External System Oscillator electrical specifications (continued) Symbol Description Min. Typ. Max. Unit — 1 — MΩ Low-gain mode (HGO=0) — 0 — kΩ High-gain mode (HGO=1) — 0 — kΩ High-gain mode (HGO=1) RS Notes Series resistor Vpp Peak-to-peak amplitude of oscillation (oscillator mode) 3 Low-gain mode (HGO=0) — 1.0 — V High-gain mode (HGO=1) — 3.3 — V 1. Crystal oscillator circuit provides stable oscillations when gmXOSC > 5 * gm_crit. The gm_crit is defined as: gm_crit = 4 * ESR * (2πF)2 * (C0 + CL)2 where: • • • • • • • gmXOSC is the transconductance of the internal oscillator circuit ESR is the equivalent series resistance of the external crystal F is the external crystal oscillation frequency C0 is the shunt capacitance of the external crystal CL is the external crystal total load capacitance. CL = Cs+ [C1*C2/(C1+C2)] Cs is stray or parasitic capacitance on the pin due to any PCB traces C1, C2 external load capacitances on EXTAL and XTAL pins See manufacture datasheet for external crystal component values • When low-gain is selected, internal RF will be selected and external RF should not be attached. • When high-gain is selected, external RF (1 M Ohm) needs to be connected for proper operation of the crystal. For external resistor, up to 5% tolerance is allowed. 3. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any other devices. 2. 6.2.2 External System Oscillator frequency specifications Table 16. External System Oscillator frequency specifications Symbol Min. Typ. Max. Unit Oscillator crystal or resonator frequency 4 — 40 MHz fec_extal Input clock frequency (external clock mode) — — 50 MHz 1 tdc_extal Input clock duty cycle (external clock mode) 48 50 52 % 1 8 MHz low-gain mode (HGO=0) — 1.5 — ms 2 8 MHz high-gain mode (HGO=1) — 2.5 — 40 MHz low-gain mode (HGO=0) — 2 — 40 MHz high-gain mode (HGO=1) — 2 — fosc_hi tcst Description Notes Crystal Start-up Time 1. Frequencies below 40 MHz can be used for degraded duty cycle up to 40-60% 2. Proper PC board layout procedures must be followed to achieve specifications. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 25 System Clock Generation (SCG) specifications 6.2.3 System Clock Generation (SCG) specifications 6.2.3.1 Fast internal RC Oscillator (FIRC) electrical specifications Table 17. Fast internal RC Oscillator electrical specifications Parameter1 Symbol Value Unit Min. Typ. Max. FIRC target frequency — 48 — MHz ΔF Frequency deviation across process, voltage, and temperature < 105°C — ±0.5 ±1 %FFIRC ΔF125 Frequency deviation across process, voltage, and temperature < 125°C — ±0.5 ±1.1 %FFIRC TStartup Startup time 3.4 5 µs2 TJIT, 3 Cycle-to-Cycle jitter — 250 500 ps Long term jitter over 1000 cycles — 0.04 0.1 %FFIRC FFIRC 3 TJIT 1. With FIRC regulator enable 2. Startup time is defined as the time between clock enablement and clock availability for system use. 3. FIRC as system clock NOTE Fast internal RC Oscillator is compliant with CAN and LIN standards. 6.2.3.2 Slow internal RC oscillator (SIRC) electrical specifications Table 18. Slow internal RC oscillator (SIRC) electrical specifications Symbol Parameter Value Unit Min. Typ. Max. SIRC target frequency — 8 — MHz ΔF Frequency deviation across process, voltage, and temperature < 105°C — — ±3 %FSIRC ΔF125 Frequency deviation across process, voltage, and temperature < 125°C — — ±3.3 %FSIRC TStartup Startup time — 9 12.5 µs1 FSIRC 1. Startup time is defined as the time between clock enablement and clock availability for system use. MWCT101XS Data Sheet, Rev. 4, 08/2020 26 NXP Semiconductors Memory and memory interfaces 6.2.4 Low Power Oscillator (LPO) electrical specifications Table 19. Low Power Oscillator (LPO) electrical specifications Symbol Parameter FLPO Internal low power oscillator frequency Tstartup Startup Time Min. Typ. Max. Unit 113 128 139 kHz — — 20 µs 6.2.5 SPLL electrical specifications Table 20. SPLL electrical specifications Symbol Parameter 1 2 FSPLL_REF FSPLL_Input Min. Typ. Max. Unit PLL Reference Frequency Range 8 — 16 MHz PLL Input Frequency 8 — 40 MHz FVCO_CLK VCO output frequency 180 — 320 MHz FSPLL_CLK PLL output frequency 90 — 160 MHz JCYC_SPLL PLL Period Jitter (RMS)3 — 120 — ps — 75 — ps at FVCO_CLK 180 MHz — 1350 — ps at FVCO_CLK 320 MHz — 600 — ps ± 4.47 — ± 5.97 % at FVCO_CLK 180 MHz at FVCO_CLK 320 MHz JACC_SPLL DUNL TSPLL_LOCK PLL accumulated jitter over 1µs Lock exit frequency tolerance Lock detector detection (RMS)3 time4 — — 10-6 150 × + 1075(1/FSPLL_REF) s 1. FSPLL_REF is PLL reference frequency range after the PREDIV. For PREDIV and MULT settings refer SCG_SPLLCFG register of Reference Manual. 2. FSPLL_Input is PLL input frequency range before the PREDIV must be limited to the range 8 MHz to 40 MHz. This input source could be derived from a crystal oscillator or some other external square wave clock source using OSC bypass mode. For external clock source settings refer SCG_SOSCCFG register of Reference Manual. 3. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary 4. Lock detector detection time is defined as the time between PLL enablement and clock availability for system use. 6.3 Memory and memory interfaces 6.3.1 Flash memory module (FTFC) electrical specifications This section describes the electrical characteristics of the flash memory module. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 27 Memory and memory interfaces 6.3.1.1 Symbol Flash timing specifications — commands Table 21. Flash command timing specifications Description1 MWCT1014S Typ trd1blk Read 1 Block execution time Max MWCT1015S MWCT1016S Typ Typ Max Max 32 KB flash — — — — — — 64 KB flash — 0.5 — 0.5 — — 128 KB flash — — — — — — 256 KB flash — — — — — — Unit Notes ms 512 KB flash — 1.8 — 2 — 2 Read 1 Section execution time 2 KB flash — 75 — 75 — 75 4 KB flash — 100 — 100 — 100 tpgmchk Program Check execution time — — 95 — 95 — 100 µs tpgm8 Program Phrase execution time — 90 225 90 225 90 225 µs tersblk Erase Flash Block execution time 32 KB flash — — — — — — ms 2 64 KB flash 30 550 30 550 — — 128 KB flash — — — — — — 256 KB flash — — — — — — 512 KB flash 250 4250 250 4250 250 4250 2 trd1sec µs tersscr Erase Flash Sector — execution time 12 130 12 130 12 130 ms tpgmsec1k Program Section execution time (1KB flash) — 5 — 5 — 5 — ms trd1all Read 1s All Block execution time — — 2.3 — 5.2 — 8.2 ms trdonce Read Once execution time — — 30 — 30 — 30 µs tpgmonce Program Once execution time — 90 — 90 — 90 — µs tersall Erase All Blocks execution time — 400 4900 700 10000 1400 17000 ms tvfykey Verify Backdoor Access Key execution time — — 35 — 35 — 35 µs tersallu Erase All Blocks Unsecure execution time — 400 4900 700 10000 1400 17000 ms 2 tpgmpart Program Partition for EEPROM execution time 32 KB EEPROM backup 70 — 70 — — — ms 3 64 KB EEPROM backup 71 — 71 — 150 — 2 Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 28 NXP Semiconductors Memory and memory interfaces Table 21. Flash command timing specifications (continued) Description1 Symbol MWCT1014S Typ tsetram teewr8b teewr16b Set FlexRAM Control Code Function execution 0xFF time 32 KB EEPROM backup Max MWCT1015S MWCT1016S Typ Typ Max Max Notes 0.08 — 0.08 — 0.08 — 0.8 1.2 0.8 1.2 — — 48 KB EEPROM backup 1 1.5 1 1.5 — — 64 KB EEPROM backup 1.3 1.9 1.3 1.9 1.3 1.9 Byte write to 32 KB FlexRAM execution EEPROM time backup 385 1700 385 1700 — — 48 KB EEPROM backup 430 1850 430 1850 — — 64 KB EEPROM backup 475 2000 475 2000 475 4000 16-bit write to 32 KB FlexRAM execution EEPROM time backup 385 1700 385 1700 — — 48 KB EEPROM backup 430 1850 430 1850 — — 64 KB EEPROM backup 475 2000 475 2000 475 4000 — 360 2000 360 2000 360 2000 µs µs 3,4 µs 4,5,6 teewr32bers 32-bit write to erased FlexRAM location execution time teewr32b 32-bit write to 32 KB FlexRAM execution EEPROM time backup 630 2000 630 2000 — — 48 KB EEPROM backup 720 2125 720 2125 — — 64 KB EEPROM backup 810 2250 810 2250 810 4500 1st 32-bit write 200 550 200 550 200 1100 2nd through Next to Last (Nth-1) 32-bit write 550 150 550 150 550 tquickwr Unit 32-bit Quick Write execution time: Time from CCIF clearing (start the write) until CCIF setting (32-bit write 150 ms 3 µs 3,4 µs 3,4 Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 29 Memory and memory interfaces Table 21. Flash command timing specifications (continued) Description1 Symbol MWCT1014S Typ tquickwrClnup Max MWCT1015S MWCT1016S Typ Typ Max complete, ready for Last (Nth) 32next 32-bit write) bit write (time for write only, not cleanup) 200 550 200 550 Quick Write — Cleanup execution time — (# of Quick Writes ) * 2.0 — (# of — Quick Writes ) * 2.0 200 Max Unit Notes 550 (# of Quick Writes ) * 2.0 ms 7 1. All command times assumes 25 MHz or greater flash clock frequency (for synchronization time between internal/external clocks). 2. Maximum times for erase parameters based on expectations at cycling end-of-life. 3. For all EEPROM Emulation terms, the specified timing shown assumes previous record cleanup has occurred. This may be verified by executing FCCOB Command 0x77, and checking FCCOB number 5 contents show 0x00 - No EEPROM issues detected. 4. 1st time EERAM writes after a Reset or SETRAM may incur additional overhead for EEE cleanup, resulting in up to 2× the times shown. 5. Only after the Nth write completes will any data be valid. Emulated EEPROM record scheme cleanup overhead may occur after this point even after a brownout or reset. If power on reset occurs before the Nth write completes, the last valid record set will still be valid and the new records will be discarded. 6. Quick Write times may take up to 550 µs, as additional cleanup may occur when crossing sector boundaries. 7. Time for emulated EEPROM record scheme overhead cleanup. Automatically done after last (Nth) write completes, assuming still powered. Or via SETRAM cleanup execution command is requested at a later point. NOTE Under certain circumstances FlexMEM maximum times may be exceeded. In this case the user or application may wait, or assert reset to the FTFC macro to stop the operation. 6.3.1.2 Reliability specifications Table 22. NVM reliability specifications Symbol Description Min. tnvmretp1k Data retention after up to 1 K cycles 20 nnvmcycp Cycling endurance 1K Typ. Max. Unit Notes — — years 1 — — cycles 2, 3 4 When using as Program and Data Flash When using FlexMemory feature: FlexRAM as Emulated EEPROM tnvmretee nnvmwree16 nnvmwree256 Data retention Write endurance • EEPROM backup to FlexRAM ratio = 16 • EEPROM backup to FlexRAM ratio = 256 5 — — years 100 K — — writes 1.6 M — — writes 5, 6, 7 1. Data retention period per block begins upon initial user factory programming or after each subsequent erase. 2. Program and Erase for PFlash and DFlash are supported across product temperature specification in Normal Mode (not supported in HSRUN mode). 3. Cycling endurance is per DFlash or PFlash Sector. 4. Data retention period per block begins upon initial user factory programming or after each subsequent erase. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5 years. MWCT101XS Data Sheet, Rev. 4, 08/2020 30 NXP Semiconductors Memory and memory interfaces 5. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product temperature specification in Normal Mode (not supported in HSRUN mode). Greater write endurance may be achieved with larger ratios of EEPROM backup to FlexRAM. 6. For usage of any EEE driver other than the FlexMemory feature, the endurance spec will fall back to the specified endurance value of the D-Flash specification (1K). 7. FlexMemory calculator tool is available at NXP web site for help in estimation of the maximum write endurance achievable at specific EEPROM/FlexRAM ratios. The “In Spec” portions of the online calculator refer to the NVM reliability specifications section of data sheet. This calculator is only applies to the FlexMemory feature. 6.3.2 QuadSPI AC specifications The following table describes the QuadSPI electrical characteristics. • Measurements are with maximum output load of 25 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). • I/O operating voltage ranges from 2.97 V to 3.6 V • While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. • Add 50 ohm series termination on board in QuadSPI SCK for Flash A to avoid loop back reflection when using in Internal DQS (PAD Loopback) mode. • QuadSPI trace length should be 3 inches. • For non-Quad mode of operation if external device doesn’t have pull-up feature, external pull-up needs to be added at board level for non-used pads. • With external pull-up, performance of the interface may degrade based on load associated with external pull-up. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 31 - MCR[SCLKCFG[1]] MCR[SCLKCFG[2]] MCR[SCLKCFG[3]] MCR[SCLKCFG[5]] SMPR[FSPHS] SMPR[FSDLY] MHz fSCK tSCK FLSHCR[TDH] SCK Clock Frequency SCK Clock Period ns - SOCCR[SOCCFG[15:8]] [SOCCFG[7:0]] SOCCR - MCR[DQS_EN] - MCR[SCLKCFG[0]] MCR[DDR_EN] - - - 0 0 0 - - - - 0 0 - 38 Max 0x00 Min N1 Internal Sampling - - 0 0 1 0 - - 1 1 1 0 Max - - 48 - Timing Parameters 0x00 - 23 0 0 0 - - 0 0 1 0 - - 0 0 0 - - - - 0 0 - 40 Max 0x00 Min Register Settings Min Table continues on the next page... - 64 Max 0x00 Min N1 Internal Sampling FLASH A Internal Loopback Internal DQS SDR PAD Loopback 1/fSCK QuadSPI Mode 1/fSCK RUN1 1/fSCK Unit 1/fSCK Sym - 0x00 - 0 0 1 0 - - 1 1 1 0 - 80 Max PAD Loopback - 0 0x00 0 30 0x00 - 0 0 50.0 0 0 - - - - 30 - - 50 - - 0 Max 204 - 50.04 0x01 0 0 1 0 0 - - 1 - 1 0 Min 0 20 Max 1 Min External DQS External DQS DDR3 0 Max N1 Internal Sampling SDR RUN/HSRUN2 FLASH B 0 Min Internal Loopback Internal DQS SDR HSRUN1 Min 1/fSCK 32 1/fSCK FLASH PORT Table 23. QuadSPI electrical specifications Memory and memory interfaces MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors tOV tIV tCSSCK tSCKCS Data Output Valid Time Data Output In-Valid Time CS to SCK Time 6 SCK to CS Time 7 1. 2. 3. 4. 5. 6. 7. tIH Data Input Hold Time pf ns ns ns ns ns ns ns tSCK/2 - 1.5 5 5 - - 0 15 25 - - 5 4.5 - - Max Min 5 5 - - 1 2.5 tSCK/2 - 1.5 25 - - 5 4.5 - - Max Min 5 5 - - 1 10 25 - - 5 4.5 - - Max Internal Loopback tSCK/2 - 1.5 PAD Loopback tSCK/2 + 1.5 See Reference Manual for details on mode settings See Reference Manual for details on mode settings Valid for HyperRAM only RWDS(External DQS CLK) frequency For operating frequency ≤ 64 Mhz,Output invalid time is 5 ns. Program register value QuadSPI_FLSHCR[TCSS] = 4`h2 Program register value QuadSPI_FLSHCR[TCSH] = 4`h1 Output Load tIS tSDC Data Input Setup Time SCK Duty Cycle Min N1 tSCK/2 + 1.5 Internal DQS tSCK/2 + 1.5 Internal Sampling Min 5 5 - - 0 14 N1 25 - - 5 4 - - Max Internal Sampling tSCK/2 - 1.5 SDR 5 5 - - 1 1.6 25 - 5 5 - 35 1 9 Min 25 - - 5 4 - - Max Internal Loopback 4 - - Max PAD Loopback Internal DQS SDR Min tSCK/2 - 0.750 QuadSPI Mode tSCK/2 + 1.5 HSRUN1 tSCK/2 - 0.750 RUN1 tSCK/2 - 1.5 FLASH A tSCK/2 + 1.5 Unit SDR Min 5 10 - - 0 25 N1 25 - - 5 10 - - Max 5 10 5 - 20 2 Min 25 - - - 10 - - Max External DQS External DQS DDR3 RUN/HSRUN2 FLASH B Internal Sampling tSCK/2 - 2.5 Sym tSCK/2 + 2.5 FLASH PORT tSCK/2 - 2.5 NXP Semiconductors tSCK/2 + 2.5 Table 23. QuadSPI electrical specifications (continued) Memory and memory interfaces MWCT101XS Data Sheet, Rev. 4, 08/2020 33 Memory and memory interfaces 1 2 Clock 3 tSCK tSDC tSDC SCK CS tIS tIH Data in Figure 8. QuadSPI input timing (SDR mode) diagram 1 2 3 Clock tSCK tSDC tSDC SCK tSCKCS tCSSCK CS tIV tOV Data out Invalid Figure 9. QuadSPI output timing (SDR mode) diagram TIS TIS TIH TIH D1 invalid D2 invalid D3 invalid D4 invalid D5 TIS– Setup Time TIH – Hold Time Figure 10. QuadSPI input timing (HyperRAM mode) diagram MWCT101XS Data Sheet, Rev. 4, 08/2020 34 NXP Semiconductors Analog modules CK tIV tOV Output Invalid Data Figure 11. QuadSPI output timing (HyperRAM mode) diagram 6.4 Analog modules 6.4.1 ADC electrical specifications 6.4.1.1 Symbol 12-bit ADC operating conditions Table 24. 12-bit ADC operating conditions Description Conditions Min. Typ.1 Max. Unit Notes VREFH ADC reference voltage high See Voltage and current operating requirements for values VDDA See Voltage and current operating requirements for values V 2 VREFL ADC reference voltage low See Voltage and current operating requirements for values 0 See Voltage and current operating requirements for values mV 2 VADIN Input voltage VREFL — VREFH V — — 5 kΩ RS Source impedendance fADCK < 4 MHz RSW1 Channel Selection Switch Impedance — 0.75 1.2 kΩ RAD Sampling Switch Impedance — 2 5 kΩ CP1 Pin Capacitance — 10 — pF CP2 Analog Bus Capacitance — — 4 pF CS Sampling capacitance — 4 5 pF Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 35 ADC electrical specifications Table 24. 12-bit ADC operating conditions (continued) Description Conditions Min. Typ.1 Max. Unit Notes fADCK ADC conversion clock frequency Normal usage 2 40 50 MHz 3, 4 fCONV ADC conversion frequency No ADC hardware averaging.5 Continuous conversions enabled, subsequent conversion time 46.4 928 1160 Ksps 6, 7 ADC hardware averaging set to 32. 5 Continuous conversions enabled, subsequent conversion time 1.45 29 36.25 Ksps 6, 7 Symbol 1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. Typical values are for reference only, and are not tested in production. 2. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to VSS. To get maximum performance, reference supply quality should be better than SAR ADC. See application note AN5032 for details. 3. Clock and compare cycle need to be set according to the guidelines mentioned in the Reference Manual . 4. ADC conversion will become less reliable above maximum frequency. 5. When using ADC hardware averaging, see the Reference Manual to determine the most appropriate setting for AVGS. 6. Numbers based on the minimum sampling time of 275 ns. 7. For guidelines and examples of conversion rate calculation, see the Reference Manual or download the ADC calculator tool. Figure 12. ADC input impedance equivalency diagram MWCT101XS Data Sheet, Rev. 4, 08/2020 36 NXP Semiconductors ADC electrical specifications 6.4.1.2 12-bit ADC electrical characteristics NOTE • ADC performance specifications are documented using a single ADC. For parallel/simultaneous operation of both ADCs, either for sampling the same channel by both ADCs or for sampling different channels by each ADC, some amount of decrease in performance can be expected. Care must be taken to stagger the two ADC conversions, in particular the sample phase, to minimize the impact of simultaneous conversions. • On reduced pin packages where ADC reference pins are shared with supply pins, ADC analog performance characteristics may be impacted. The amount of variation will be directly impacted by the external PCB layout and hence care must be taken with PCB routing. See AN5426 for details Table 25. 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) Min. Typ.2 Max. Unit Supply voltage 2.7 — 3 V Supply current per ADC — 0.6 — mA 275 — Refer to the Reference Manual ns — ±4 ±8 LSB5 6, 7, 8, 9 — LSB5 6, 7, 8, 9 — LSB5 6, 7, 8, 9 Symbol Description VDDA IDDA_ADC SMPLTS Sample Time TUE4 DNL INL Total unadjusted error Differential non-linearity Integral non-linearity Conditions 1 — — ±1.0 ±2.0 Notes 3 1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than or equal to half of the maximum specified ADC clock frequency. 2. Typical values assume VDDA = 3 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF. 3. The ADC supply current depends on the ADC conversion rate. 4. Represents total static error, which includes offset and full scale error. 5. 1 LSB = (VREFH - VREFL)/2N 6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings for AVGS. 7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC performance may be observed. 8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the internal analog parameters, assume minor degradation. 9. All the parameters in the table are given assuming system clock as the clocking source for ADC. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 37 ADC electrical specifications Table 26. 12-bit ADC characteristics (3 V to 5.5 V)(VREFH = VDDA, VREFL = VSS) Min. Typ.2 Max. Unit Supply voltage 3 — 5.5 V Supply current per ADC — 1 — mA 275 — Refer to the Reference Manual ns — ±4 ±8 LSB5 6, 7, 8, 9 — LSB5 6, 7, 8, 9 — LSB5 6, 7, 8, 9 Symbol Description VDDA IDDA_ADC SMPLTS Sample Time TUE4 DNL INL Total unadjusted error Differential non-linearity Integral non-linearity Conditions 1 — — ±0.7 ±1.0 Notes 3 1. All accuracy numbers assume the ADC is calibrated with VREFH=VDDA=VDD, with the calibration frequency set to less than or equal to half of the maximum specified ADC clock frequency. 2. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 40 MHz, RAS=20 Ω, and CAS=10 nF unless otherwise stated. 3. The ADC supply current depends on the ADC conversion rate. 4. Represents total static error, which includes offset and full scale error. 5. 1 LSB = (VREFH - VREFL)/2N 6. The specifications are with averaging and in standalone mode only. Performance may degrade depending upon device use case scenario. When using ADC averaging, refer to the Reference Manual to determine the most appropriate settings for AVGS. 7. For ADC signals adjacent to VDD/VSS or XTAL/EXTAL or high frequency switching pins, some degradation in the ADC performance may be observed. 8. All values guarantee the performance of the ADC for multiple ADC input channel pins. When using ADC to monitor the internal analog parameters, assume minor degradation. 9. All the parameters in the table are given assuming system clock as the clocking source for ADC. NOTE • Due to triple bonding in lower pin packages like the 64LQFP, degradation might be seen in ADC parameters. • When using high speed interfaces such as the QuadSPI, there may be some ADC degradation on the adjacent analog input paths. See following table for details. Pin name TGATE purpose PTE8 CMP0_IN3 PTC3 ADC0_SE11/CMP0_IN4 PTC2 ADC0_SE10/CMP0_IN5 PTD7 CMP0_IN6 PTD6 CMP0_IN7 PTD28 ADC1_SE22 PTD27 ADC1_SE21 MWCT101XS Data Sheet, Rev. 4, 08/2020 38 NXP Semiconductors ADC electrical specifications 6.4.2 CMP with 8-bit DAC electrical specifications Table 28. Comparator with 8-bit DAC electrical specifications Symbol IDDHS Description Min. — Supply current, Low-speed 230 6 11 6 13 0 0 - VDDA VDDA -25 ±1 25 -40 - 125 ℃ Analog input voltage VAIO Analog input offset voltage, High-speed mode -40 - 125 ℃ mV -40 Propagation delay, High-speed — tDHSS Propagation delay, Low-speed µs 0.5 2 — 0.5 3 Propagation delay, High-speed mode3 Propagation delay, Low-speed Initialization delay, High-speed ns — 70 400 — 70 500 mode3 µs — 1 5 — 1 5 — 1.5 3 mode4 -40 - 125 ℃ μs Initialization delay, Low-speed mode4 -40 - 125 ℃ μs — 10 30 Analog comparator hysteresis, Hyst0 -40 - 125 ℃ VHYST1 300 — -40 - 125 ℃ VHYST0 35 -40 - 125 ℃ -40 - 105 ℃ tIDLS 200 -40 - 105 ℃ -40 - 125 ℃ tIDHS 35 mode2 -40 - 105 ℃ tDLSS 40 ns -40 - 125 ℃ tDLSB ±4 mode2 -40 - 105 ℃ mV — 0 — Analog comparator hysteresis, Hyst1, High-speed mode -40 - 125 ℃ V mV Analog input offset voltage, Low-speed mode -40 - 125 ℃ tDHSB 300 μA — VAIN Unit μA mode1 -40 - 105 ℃ VAIO Max. Supply current, High-speed mode1 -40 - 125 ℃ IDDLS Typ. mV — 19 66 — 15 40 Analog comparator hysteresis, Hyst1, Low-speed mode -40 - 125 ℃ VHYST2 Analog comparator hysteresis, Hyst2, High-speed mode -40 - 125 ℃ mV — 34 133 Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 39 ADC electrical specifications Table 28. Comparator with 8-bit DAC electrical specifications (continued) Symbol Description Min. Typ. Max. — 23 80 Unit Analog comparator hysteresis, Hyst2, Low-speed mode -40 - 125 ℃ VHYST3 Analog comparator hysteresis, Hyst3, High-speed mode mV -40 - 125 ℃ — 46 200 — 32 120 3.3V Reference Voltage — 6 9 μA 5V Reference Voltage — 10 16 μA Analog comparator hysteresis, Hyst3, Low-speed mode -40 - 125 ℃ IDAC8b 1. 2. 3. 4. 5. 6. 8-bit DAC current adder (enabled) INL5 8-bit DAC integral non-linearity –0.75 — 0.75 LSB6 DNL 8-bit DAC differential non-linearity –0.5 — 0.5 LSB6 tDDAC Initialization and switching settling time — — 30 μs Difference at input > 200mV Applied ± (100 mV + VHYST0/1/2/3+ max. of VAIO) around switch point. Applied ± (30 mV + 2 × VHYST0/1/2/3+ max. of VAIO) around switch point. Applied ± (100 mV + VHYST0/1/2/3). Calculation method used: Linear Regression Least Square Method 1 LSB = Vreference/256 NOTE For comparator IN signals adjacent to VDD/VSS or XTAL/ EXTAL or switching pins cross coupling may happen and hence hysteresis settings can be used to obtain the desired comparator performance. Additionally, an external capacitor (1nF) should be used to filter noise on input signal. Also, source drive should not be weak (Signal with < 50 K pull up/down is recommended). MWCT101XS Data Sheet, Rev. 4, 08/2020 40 NXP Semiconductors ADC electrical specifications Figure 13. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 0) Figure 14. Typical hysteresis vs. Vin level (VDDA = 3.3 V, PMODE = 1) MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 41 ADC electrical specifications Figure 15. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 0) Figure 16. Typical hysteresis vs. Vin level (VDDA = 5 V, PMODE = 1) MWCT101XS Data Sheet, Rev. 4, 08/2020 42 NXP Semiconductors Communication modules 6.5 Communication modules 6.5.1 LPUART electrical specifications Refer to General AC specifications for LPUART specifications. 6.5.1.1 Supported baud rate Baud rate = Baud clock / ((OSR+1) * SBR). For details, see section: 'Baud rate generation' of the Reference Manual. 6.5.2 LPSPI electrical specifications The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus with master and slave operations. Many of the transfer attributes are programmable. The following tables provide timing characteristics for classic LPSPI timing modes. • All timing is shown with respect to 20% VDD and 80% VDD thresholds. • All measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew setting ( DSE = 1 ). MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 43 fop tSPSCK tLead8 1 2 3 20 12 - 100 100 50 83 - Master Master Loopback5 Master Loopback(slow)6 Master Loopback(slow)6 Master Loopback5 Master Loopback(slow)6 Enable lead Slave time (PCS to Master SPSCK delay) Master Loopback5 10 12 12 - 100 100 83 83 - 10 48 48 40 40 Max. - - - - - Min. 14 24 12 - 72 72 42 83 - - 14 48 48 56 56 Max. - - - - - Min. 5.0 V IO 2 2 - 500 500 500 500 - 14 12 12 - 72 72 83 83 - - 2 - 7 - 2 - 14 7 4 4 4 4 Max. - - - - Min. - 48 56 56 Max. 5.0 V IO 2 2 2 - 500 500 500 500 - - 2 4 4 4 4 Max. - - - - - Min. 3.3 V IO VLPR Mode 48 - - - - Min. 3.3 V IO HSRUN Mode2 Table continues on the next page... - 10 Master - 48 10 - Master Loopback(slow)6 40 40 40 - - Master Loopback5 Slave - Master SPSCK period Slave Frequency of operation - Slave Max. 3.3 V IO Run Mode2 5.0 V IO Min. (PCSSCK+1)*tperiph-25 fperiph, 3, 4 Peripheral Frequency Conditions (PCSSCK+1)*tperiph-25 Description (PCSSCK+1)*tperiph-25 Symbol (PCSSCK+1)*tperiph-25 Num (PCSSCK+1)*tperiph-50 44 (PCSSCK+1)*tperiph-50 Table 29. LPSPI electrical specifications1 ns ns MHz MHz Unit Communication modules MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors Master Loopback(slow)6 Enable lag Slave time (After Master SPSCK delay) Master Loopback5 tSU tHI 7 Data hold time(inputs) Data setup time(inputs) 0 3 3 Master Loopback5 Master Loopback(slow)6 8 Master Loopback(slow)6 Master 7 Master Loopback5 3 29 Master Slave 3 3 3 0 3 10 8 38 5 - - - - - - - - - - - Max. Min. 3 2 0 3 7 5 26 3 - - - - - - - - - - - Max. Min. 5.0 V IO Table continues on the next page... - - - - - - - - - - - Slave Master Loopback(slow)6 tWSPSCK Clock(SPSCK Slave ) high or low Master time (SPSCK Master duty cycle) Loopback5 6 5 tLag9 (SCKPCS+1)*tperiph- 25 tSPSCK/2-3 4 Max. (SCKPCS+1)*tperiph- 25 tSPSCK/2-3 Min. tSPSCK/2+3 3.3 V IO (SCKPCS+1)*tperiph- 25 tSPSCK/2-3 5.0 V IO tSPSCK/2+3 - - 3 3 0 3 9 7 32 - - - - - - - 3710 11 - 5 - Max. Min. 3.3 V IO HSRUN Mode2 tSPSCK/2+3 Run Mode2 tSPSCK/2+3 Conditions - - 12 11 0 14 20 20 72 18 - - - - - - - - - Max. Min. 5.0 V IO - - 12 11 0 14 20 20 78 18 - Max. Min. 3.3 V IO VLPR Mode tSPSCK/2+5 Description (SCKPCS+1)*tperiph- 25 tSPSCK/2-3 Symbol (SCKPCS+1)*tperiph- 50 tSPSCK/2-5 Num (SCKPCS+1)*tperiph- 50 tSPSCK/2-5 NXP Semiconductors - - - - - - - - tSPSCK/2+5 Table 29. LPSPI electrical specifications1 (continued) ns ns ns ns Unit Communication modules MWCT101XS Data Sheet, Rev. 4, 08/2020 45 46 tRI/FI tRO/FO 13 tv 10 12 tdis 9 tHO ta 8 11 Symbol Num Slave Slave Conditions -10 -15 Master Master Loopback5 Master Loopback(slow)6 - Master Loopback(slow) 6 5 Master Loopback - - - Master Loopback(slow)6 Rise/Fall time Slave output Master - Master Loopback5 - - 4 -15 Slave - Master Loopback(slow)6 Rise/Fall time Slave input Master Data hold time(outputs) - - - - - 25 1 - - - - 8 12 12 30 50 50 Max. - - - - - - - - -22 -14 -22 4 - - - - - - Min. 25 1 - - - - 10 16 16 39 50 50 Max. 3.3 V IO Run Mode2 5.0 V IO Min. Master Loopback5 Data valid Slave (after SPSCK edge) Master Slave MISO (SOUT) disable time Slave access time Description - - - - - - - - -15 -10 -15 4 - - - - - - Min. 25 1 - - - - 7 11 11 26 50 50 Max. - - - - - - - - -22 -14 -23 4 - - - - - - Min. 25 1 - - - - 9 15 15 - - - - - - - - -21 -14 -22 4 - - - - 36 10 31 11 - - 25 1 - - - - 44 47 47 92 100 100 Max. - - - - - - - - -27 -19 -29 4 - - - - - - Min. 25 1 - - - - 44 48 48 96 100 100 Max. 3.3 V IO VLPR Mode 5.0 V IO Min. 50 50 Max. 3.3 V IO HSRUN Mode2 5.0 V IO Table 29. LPSPI electrical specifications1 (continued) ns ns ns ns ns ns Unit Communication modules MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors Trace length should not exceed 11 inches for SCK pad when used in Master loopback mode. While transitioning from HSRUN mode to RUN mode, LPSPI output clock should not be more than 14 MHz. fperiph = LPSPI peripheral clock tperiph = 1/fperiph Master Loopback mode - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock pads used are PTD15 and PTE0. Applicable only for LPSPI0. 6. Master Loopback (slow) - In this mode LPSPI_SCK clock is delayed for sampling the input data which is enabled by setting LPSPI_CFGR1[SAMPLE] bit as 1. Clock pad used is PTB2. Applicable only for LPSPI0. 7. This is the maximum operating frequency (fop) for LPSPI0 with medium PAD type only. Otherwise, the maximum operating frequency (fop) is 12 Mhz. 8. Set the PCSSCK configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where PCSSCK ranges from 0 to 255. 9. Set the SCKPCS configuration bit as 0, for a minimum of 1 delay cycle of LPSPI baud rate clock, where SCKPCS ranges from 0 to 255. 10. Maximum operating frequency (fop ) is 12 MHz irrespective of PAD type and LPSPI instance. 11. Applicable for LPSPI0 only with medium PAD type, with maximum operating frequency (fop) as 14 MHz. 1. 2. 3. 4. 5. Communication modules MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 47 Communication modules SS1 (OUTPUT) 3 2 SPSCK (CPOL=0) (OUTPUT) 12 13 12 13 4 5 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 7 MSB IN2 BIT 6 . . . 1 LSB IN 10 MOSI (OUTPUT) MSB OUT2 11 BIT 6 . . . 1 LSB OUT 1. If configured as an output. 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 17. LPSPI master mode timing (CPHA = 0) SS1 (OUTPUT) 2 3 SPSCK (CPOL=0) (OUTPUT) 5 SPSCK (CPOL=1) (OUTPUT) 6 MISO (INPUT) 5 13 12 13 4 7 MSB IN2 BIT 6 . . . 1 LSB IN 11 10 MOSI (OUTPUT) 12 PORT DATA MASTER MSB OUT2 BIT 6 . . . 1 MASTER LSB OUT PORT DATA 1.If configured as output 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 18. LPSPI master mode timing (CPHA = 1) MWCT101XS Data Sheet, Rev. 4, 08/2020 48 NXP Semiconductors Communication modules SS (INPUT) 2 12 13 12 13 4 SPSCK (CPOL=0) (INPUT) 5 3 SPSCK (CPOL=1) (INPUT) 5 9 8 MISO (OUTPUT) See note1 SLAVE MSB 6 MOSI (INPUT) 10 11 11 BIT 6 . . . 1 SLAVE LSB OUT See note 1 7 MSB IN BIT 6 . . . 1 LSB IN Notes: 1. Undefined Figure 19. LPSPI slave mode timing (CPHA = 0) SS (INPUT) 4 2 3 SPSCK (CPOL=0) (INPUT) 5 SPSCK (CPOL=1) (INPUT) 5 See note 1 8 MOSI (INPUT) SLAVE 13 12 13 11 10 MISO (OUTPUT) 12 MSB OUT 6 9 BIT 6 . . . 1 SLAVE LSB OUT BIT 6 . . . 1 LSB IN 7 MSB IN Notes: 1. Undefined Figure 20. LPSPI slave mode timing (CPHA = 1) 6.5.3 LPI2C electrical specifications See General AC specifications for LPI2C specifications. For supported baud rate see section 'Chip-specific LPI2C information' of the Reference Manual. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 49 Debug modules 6.5.4 FlexCAN electical specifications For supported baud rate, see section 'Protocol timing' of the Reference Manual. 6.5.5 Clockout frequency Maximum supported clock out frequency for this device is 20 MHz 6.6 Debug modules 6.6.1 SWD electrical specofications MWCT101XS Data Sheet, Rev. 4, 08/2020 50 NXP Semiconductors SWD_CLK rise and fall times SWD_DIO input data setup time to SWD_CLK rise SWD_DIO input data hold time after SWD_CLK rise SWD_CLK high to SWD_DIO data valid SWD_CLK high to SWD_DIO high-Z SWD_CLK high to SWD_DIO data invalid S10 S11 S12 S13 SWD_CLK clock pulse width S3 S9 SWD_CLK cycle period S2 S4 SWD_CLK frequency of operation S1 0 - - 3 4 - 1/S1 - 28 28 - - 1 - 25 - 0 - - 3 4 - 38 38 - - 1 - 0 - - 3 4 - 28 28 - - 1 - 0 - - 3 4 - 1/S1 - 38 38 - - 1 - 0 - - 10 16 - 1/S1 - 70 70 - - 1 - - 0 - - 10 16 - 77 77 - - 1 ns ns ns ns ns ns ns ns 1/S1 - - 1/S1 1/S1 MHz 10 - 10 - 25 - 25 - 25 - S2/2 - 5 - Max. Min. Max. Min. Max. Min. Max. 3.3 V IO Min. 5.0 V IO Unit Max. 3.3 V IO VLPR Mode Min. 5.0 V IO S2/2 - 5 S2/2 + 5 S2/2 + 5 Max. 3.3 V IO S2/2 + 5 Min. S2/2 - 5 HSRUN Mode S2/2 - 5 5.0 V IO S2/2 + 5 Run Mode S2/2 + 5 Description S2/2 - 5 Symbol S2/2 + 5 NXP Semiconductors S2/2 - 5 Table 30. SWD electrical specifications Debug modules MWCT101XS Data Sheet, Rev. 4, 08/2020 51 Debug modules S2 S3 S3 SWD_CLK (input) S4 S4 Figure 21. Serial wire clock input timing SWD_CLK S9 SWD_DIO S10 Input data valid S11 S13 SWD_DIO Output data valid S12 SWD_DIO Figure 22. Serial wire data timing 6.6.2 Trace electrical specifications The following table describes the Trace electrical characteristics. • Measurements are with maximum output load of 50 pF, input transition of 1 ns and pad configured with fastest slew settings (DSE = 1'b1). • While doing the mode transition (RUN -> HSRUN or HSRUN -> RUN ), the interface should be OFF. Table 31. Trace specifications Symbol — Fsys Description System frequency RUN Mode 80 48 HSRUN Mode 40 112 80 VLPR Mode Unit 4 MHz Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 52 NXP Semiconductors Debug modules Table 31. Trace specifications (continued) Symbol Trace on fast pads fTRACE RUN Mode Max Trace frequency 80 HSRUN Mode VLPR Mode Unit 48 40 74.667 80 4 MHz tDVO Data Output Valid 4 4 4 4 4 20 ns tDIV Data Output Invalid -2 -2 -2 -2 -2 -10 ns 24 20 22.4 22.86 4 MHz fTRACE Trace on slow pads Description Max Trace frequency 22.86 tDVO Data Output Valid 8 8 8 8 8 20 ns tDIV Data Output Invalid -4 -4 -4 -4 -4 -10 ns Figure 23. TRACE CLKOUT specifications 6.6.3 JTAG electrical specifications MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 53 TCLK clock pulse width J3 TCLK rise and fall times Boundary scan input data setup time to TCLK rise Boundary scan input data hold time after TCLK rise TCLK low to boundary scan output data valid TCLK low to boundary scan output data invalid TCLK low to boundary scan output high-Z TMS, TDI input data setup time to TCLK rise TMS, TDI input data hold time after TCLK rise TCLK low to TDO data valid TCLK low to TDO data invalid TCLK low to TDO high-Z J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 JTAG Boundary Scan TCLK cycle period - JTAG J2 - TCLK frequency of operation JI - 0 - 2 3 - 0 - 5 5 - 1/JI J2/2 + 5 28 - 28 - - 28 - 28 - - 1 - 20 20 Max. - 0 - 2 3 - 0 - 5 5 - 1/JI 32 - 32 - - 32 - 32 - - 1 - 20 20 - Max. Min. - 0 - 2 3 - 0 - 5 5 - 1/JI 28 - 28 - - 28 - 28 - - 1 - 20 - 0 - 2 3 - 0 - 5 5 - 1/JI - 32 - 32 - - 32 - 32 - - 1 - 20 20 - 20 - Max. Min. Max. 3.3 V IO Min. 5.0 V IO J2/2 - 5 J2/2 + 5 3.3 V IO J2/2 + 5 J2/2 - 5 HSRUN Mode J2/2 + 5 Run Mode - 0 - 8 15 - 0 - 8 15 - 1/JI 80 - 80 - - 80 - 80 - - 1 - 10 - 0 - 8 15 - 0 - 8 15 - 1/JI - 80 - 80 - - 80 - 80 - - 1 - 10 10 - 10 - Max. Min. Max. Min. 3.3 V IO VLPR Mode 5.0 V IO J2/2 + 5 5.0 V IO Min. J2/2 - 5 Boundary Scan Description Symbol J2/2 - 5 J2/2 - 5 54 J2/2 + 5 Table 32. JTAG electrical specifications ns ns ns ns ns ns ns ns ns ns ns ns MHz Unit Debug modules MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors J2/2 - 5 Debug modules J2 J3 J3 TCLK (input) J4 J4 Figure 24. Test clock input timing TCLK J5 Data inputs J6 Input data valid J7 J8 Data outputs Output data valid J9 Data outputs Figure 25. Boundary scan (JTAG) timing MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 55 Thermal attributes TCLK J10 TDI/TMS J11 Input data valid J12 J13 TDO Output data valid J14 TDO Figure 26. Test Access Port timing 7 Thermal attributes 7.1 Description The tables in the following sections describe the thermal characteristics of the device. NOTE Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting side (board) temperature, ambient temperature, air flow, power dissipation or other components on the board, and board thermal resistance. 7.2 Thermal characteristics MWCT101XS Data Sheet, Rev. 4, 08/2020 56 NXP Semiconductors NXP Semiconductors Four layer board (2s2p) Thermal resistance, Junction to Ambient (@200 ft/ min)1, 3 5. 6. 2. 3. 4. 1. Two layer board (1s1p) Thermal resistance, Junction to Ambient (@200 ft/min)1 Natural Convection ψJT RθJC RθJB RθJMA RθJMA RθJMA RθJA RθJA RθJA Symbol Values 2 2 100 12 100 64 12 25 100 64 25 34 100 64 36 35 100 64 38 42 100 64 49 40 100 64 43 42 100 64 45 52 100 64 61 2 2 11 11 24 23 33 35 34 37 41 48 39 41 40 44 21 59 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA MWCT1014S MWCT1015S MWCT1016S 64 Packages °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Unit Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Thermal resistance, Junction to Package Top6 Thermal resistance, Junction to Case — Single layer board (1s) Thermal resistance, Junction to Ambient (@200 ft/ min)1, 3 5 Four layer board (2s2p) Thermal resistance, Junction to Ambient (Natural Convection)1, 2 — Two layer board (1s1p) Thermal resistance, Junction to Ambient (Natural Convection)1 Thermal resistance, Junction to Single layer board (1s) Thermal resistance, Junction to Ambient (Natural Convection)1, 2 Board4 Conditions Rating Table 33. Thermal characteristics for the 64/100-pin LQFP package Thermal attributes MWCT101XS Data Sheet, Rev. 4, 08/2020 57 58 7. 5. 6. 2. 3. 4. 1. — — 10.2 0.2 12.2 ψJT ψJB 15.3 27.2 RθJC RθJB 44.1 32.1 57.2 MWCT1015S 15.9 0.4 14.2 18.9 30.9 46.6 35.6 61.0 MWCT1014S Values 18.3 0.2 7.5 11.2 22.8 39.0 27.5 52.5 MWCT1016S °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Unit Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. Per JEDEC JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. Thermal resistance, Junction to Package Bottom outside center7 Thermal resistance, Junction to Package Top outside — Thermal resistance, Junction to Case 5 center6 — Two layer board (2s2p) Thermal resistance, Junction to Board4 Thermal resistance, Junction to Ambient (@200 RθJMA RθJMA Single layer board (1s) Thermal resistance, Junction to Ambient (@200 ft/min) 1, 2, 3 ft/min)1, 3 RθJA 1, 2, 3 Thermal resistance, Junction to Ambient (Natural Convection) Four layer board (2s2p) Symbol RθJA 1, 2 Conditions Thermal resistance, Junction to Ambient (Natural Convection) Single layer board (1s) Rating Table 34. Thermal characteristics for the 100 MAPBGA package Thermal attributes MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors Thermal attributes 7.3 General notes for specifications at maximum junction temperature An estimation of the chip junction temperature, TJ, can be obtained from this equation: where: • TA = ambient temperature for the package (°C) • RθJA = junction to ambient thermal resistance (°C/W) • PD = power dissipation in the package (W) The junction to ambient thermal resistance is an industry standard value that provides a quick and easy estimation of thermal performance. Unfortunately, there are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. For packages such as the PBGA, these values can be different by a factor of two. Which value is closer to the application depends on the power dissipated by other components on the board. The value obtained on a single layer board is appropriate for the tightly packed printed circuit board. The value obtained on the board with the internal planes is usually appropriate if the board has low power dissipation and the components are well separated. When a heat sink is used, the thermal resistance is expressed in the following equation as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: where: • RθJA = junction to ambient thermal resistance (°C/W) • RθJC = junction to case thermal resistance (°C/W) • RθCA = case to ambient thermal resistance (°C/W) RθJC is device related and cannot be influenced by the user. The user controls the thermal environment to change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit board, or change the thermal dissipation on the printed circuit board surrounding the device. MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 59 Dimensions To determine the junction temperature of the device in the application when heat sinks are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the junction temperature with a measurement of the temperature at the top center of the package case using this equation: where: • TT = thermocouple temperature on top of the package (°C) • ΨJT = thermal characterization parameter (°C/W) • PD = power dissipation in the package (W) The thermal characterization parameter is measured per JESD51-2 specification using a 40 gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. 8 Dimensions 8.1 Obtaining package dimensions Package dimensions are provided in the package drawings. To find a package drawing, go to http://www.nxp.com and perform a keyword search for the drawing’s document number: Package option Document Number 64-pin LQFP 98ASS23234W 100-pin LQFP 98ASS23308W 100-pin MAPBGA 98ASA00802D MWCT101XS Data Sheet, Rev. 4, 08/2020 60 NXP Semiconductors Pinouts 9 Pinouts 9.1 Package pinouts and signal descriptions For package pinouts and signal descriptions, refer to the Reference Manual. 10 Revision History The following table provides a revision history for this document. Table 35. Revision History Rev. No. Date Substantial Changes Rev. 0 May 2017 • Initial release. Rev. 1 Dec 2017 • In "Feature comparison" section, updated the "MWCT101xS product series comparison" figure. • In Table 1, • Updated note 'All the limits defined ... ' • Updated parameter 'IINJPAD_DC_ABS', 'VIN_DC', IINJSUM_DC_ABS. • In Table 2, • Updated min. value of VDD_OFF • Added parameter IINJPAD_DC_OP and IINJSUM_DC_OP. • Updated footnote to TSPLL_LOCK and removed IDDSPLL in "SPLL electrical specifications" table. • In "12-bit ADC electrical characteristics" section, • Updated table: 12-bit ADC characteristics (2.7 V to 3 V) (VREFH = VDDA, VREFL = VSS) • Added typ. value to IDDA_ADC, TUE, DNL, and INL • Added min. value to SMPLTS • Removed footnote 'All the parameters in this table ... ' • Updated table: 12-bit ADC characteristics (3 V to 5.5 V) (VREFH = VDDA, VREFL = VSS) • Added typ. value to IDDA_ADC • Removed footnote 'All the parameters in this table ... ' • In "Flash command timing specifications" table, updated Max. value of tvfykey to 35 μs • Updated "MWCT101xS product series comparison" figure. • In Table 5, updated TBDs for VLVR_HYST, VLVD_HYST, and VLVW_HYST • In Power mode transition operating behaviors, • Added VLPR → VLPS • Added VLPS → VLPR • Updated TBDs for VLPS → Asynchronous DMA Wakeup, STOP1 → Asynchronous DMA Wakeup, and STOP2 → Asynchronous DMA Wakeup • In Table 7, updated the specifications for MWCT1014S. • Updated the attachment MWCT101xS_Power_Modes _Configuration.xlsx. • In "Standard input pin capacitance" table, removed CIN_A. • In "External System Oscillator electrical specifications" table, Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 61 Revision History Table 35. Revision History (continued) Rev. No. Date Substantial Changes • • • • • • • • • • Rev. 2 July 2018 • Updated specifications for gmXOSC. • Removed IDDOSC In "Fast internal RC Oscillator (FIRC) electrical specifications" section, • Added parameter ΔF125. • Removed IDDFIRC In "Slow internal RC oscillator (SIRC) electrical specifications" section, • Added parameter ΔF125. • Removed IDDSIRC In "Low Power Oscillator (LPO) electrical specifications" section, removed ILPO Updated section: "Flash memory module (FTFC) electrical specifications" In section: "12-bit ADC electrical characteristics", • Updated TBDs in Table 25. • Updated TBDs in Table 26. In section: QuadSPI AC specifications, updated figure 'QuadSPI output timing (HyperRAM mode) diagram'. In section: "ADC electrical specifications", updated Table 24. In section: "CMP with 8-bit DAC electrical specifications", added note 'For comparator IN signals adjacent ... ' In table: "LPSPI electrical specifications", minor update in footnote 6. In table: Table 33, updated specifications for MWCT1015S. • Global update: removed Ethernet and SAI • Updated the attachment MWCT101xS_Power_Modes _Configuration.xlsx • In 'Key features': • Added a note under 'Power management', 'Memory and memory interfaces', and 'Safety and security' • Updated FlexIO under Communications interfaces • Updated Cryptographic Services Engine (CSEc) under 'Safety and security' • Updated package information • In High-level architecture diagram for the MWCT101xS family, added footnote 3 • In "Feature comparison" section, updated the "MWCT101xS product series comparison" figure: • Updated the "System RAM" row • Added support for LIN protocol version 2.2 A • Updated the Ecosystem information • Updated the Package information • Updated the Legend notes • Updated Ordering information • In Absolute maximum ratings : • Updated the NOTE section • Added parameter 'Tramp_MCU' • Updated footnote for 'Tramp' • Updated Voltage and current operating requirements • In Power and ground pins • Removed the 144-pin LQFP package • Updated footnote 'VDD and VDDA must be shorted ...' • Updated the "Power diagram" figure • In Power mode transition operating behaviors updated numbers for: • VLPR → VLPS Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 62 NXP Semiconductors Revision History Table 35. Revision History Rev. No. Date Substantial Changes • • • • • • • • • • • • • • VLPS → VLPR • RUN → VLPS • RUN → VLPR In Power consumption : • Updated specs • Removed section 'Modes configuration', amd moved its content under the fisrt paragraph. • Updated footnote 'Typical current numbers are indicative ...' • Updated footnote 'The MWCT1016S data ...' • Removed footnote 'Above MWCT1016S data is preliminary targets only' In General AC specifications : • Updated max value and footnote of WFRST • Updated symbol for not filtered pulse to 'WNFRST', updated min value, removed max. value, and added footnote Fixed naming conventions to align with DS in DC electrical specifications at 3.3 V Range and DC electrical specifications at 5.0 V Range Updated specs for AC electrical specifications at 3.3 V range and AC electrical specifications at 5 V range In Device clock specifications : • Added footnote to fBUS In External System Oscillator frequency specifications : • Updated 'tdc_extal' • Added footnote 'Frequecies below ... ' to 'fec_extal' and 'tdc_extal' Updated Flash timing specifications — commands In Reliability specifications : • Updated footnotes In QuadSPI AC specifications : • Updated 'MCR[SCLKCFG[5]]' value to 0 • Updated 'Data Input Setup Time' HSRUN Internal DQS PAD Loopback value to 1.6 • Updated 'Data Input Setup Time' DDR External DQS min. value to 2 • Updated 'Data Input Hold Time' DDR External DQS min. value to 20 • Updated tIV • Upadted figure 'QuadSPI output timing (SDR mode) diagram' and 'QuadSPI input timing (HyperRAM mode) diagram' In 12-bit ADC operating conditions : • Fixed the typo in RSW1 • Removed parameter 'ΔVDDA' In 12-bit ADC electrical characteristics : • Added note 'On reduced pin packages where ... ' • Removed max. value of 'IDDA_ADC' • Added note 'Due to triple ... ' In CMP with 8-bit DAC electrical specifications : • Updated Typ. and Max. values of 'IDDLS' • Upadted Typ. value of 'tDHSB' • Updated Typ. value of 'VHYST1' , 'VHYST2', and 'VHYST3' In LPSPI electrical specifications : • Updated 'fperiph' and 'fop', and 'tSPSCK' • Updated 3.3 V numbers and added footnote against fop, tSU, ans tV in HSRUN Mode • Added footnote to 'tWSPSCK' Table continues on the next page... MWCT101XS Data Sheet, Rev. 4, 08/2020 NXP Semiconductors 63 Revision History Table 35. Revision History (continued) Rev. No. Date Substantial Changes • Updated tLead and tLag • Added footnote in Figure: LPSPI slave mode timing (CPHA = 0) and Figure: LPSPI slave mode timing (CPHA = 1) • In Thermal characteristics : • Updated table name for the LQFP packages • Added table for the BGA package • Updated Obtaining package dimensions Rev. 3 Dec 2019 • Updated Ordering Information in Ordering information • Updated CAN-FD and CSec information for MWCT1015SF in Feature Comparison figure Rev. 4 Aug 2020 • Removed Trays and Tubes from the Ordering information MWCT101XS Data Sheet, Rev. 4, 08/2020 64 NXP Semiconductors How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. 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