N74F125N,602

74F125 Quad buffers; 3-State Rev. 3 — 18 January 2013 Product data sheet 1. General description The 74F125 provides four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable input (nOE). A HIGH at nOE causes the outputs to assume a high-impedance OFF-state. 2. Features and benefits  High impedance NPN base inputs for reduced loading (20 mA in HIGH and LOW states) 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version N74F125N 0 C to +70 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 N74F125D 0 C to +70 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74F125 NXP Semiconductors Quad buffers; 3-state 4. Functional diagram 2 1A 1 1OE 5 2A 4 2OE 1Y 3 2 2Y 1 6 1 3 EN1 5 6 4 9 3A 3Y 8 9 10 3OE 12 4A 13 4OE 8 10 4Y 11 12 11 13 mna229 mna228 Fig 1. Logic symbol Fig 2. IEC logic symbol 5. Pinning information 5.1 Pinning ) 2(   9&& $   2( <   $ 2(   < $   2( <   $ *1'   < DDD Fig 3. Pin configuration DIP14 and SO14 package 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 2 of 12 74F125 NXP Semiconductors Quad buffers; 3-state 5.2 Pin description Table 2. Pin description Symbol Pin Description Unit load HIGH/LOW Load value[1] HIGH/LOW 1OE to 4OE 1, 4, 10, 13 output enable input (active LOW) 1.0/0.033 20 A/20 A 1A to 4A 2, 5, 9, 12 data input 1.0/0.033 20 A/20 A 1Y to 4Y 3, 6, 8, 11 data output 750/106.7 15 mA/64 mA GND 7 ground (0 V) - - VCC 14 supply voltage - - [1] One FAST Unit Load (UL) is defined as 20 A in HIGH state, 0.6 A in LOW state. 6. Functional description Table 3. Function table[1] Control Input Output nOE nA nY L L L H H X Z H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Conditions output in HIGH-state Min Max Unit 0.5 +7.0 V [1] 0.5 +7.0 V [1] 0.5 VCC V IIK input clamping current VI < 0 V 30 +5 mA IO output current output in LOW-state - 128 mA Tamb ambient temperature in free air 0 70 C Tstg storage temperature 65 +150 C [2] [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 3 of 12 74F125 NXP Semiconductors Quad buffers; 3-state 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VCC Conditions Min Typ Max Unit supply voltage 4.5 5.0 5.5 V VIH HIGH-level input voltage 2.0 - - V VIL LOW-level input voltage - - 0.8 V IIK input clamping current 18 - - mA IOH HIGH-level output current 15 - - mA IOL LOW-level output current - - 64 mA Tamb ambient temperature 0 70 C 9. Static characteristics Table 6. Static characteristics Symbol Parameter 25 C Conditions VIK input clamping voltage VCC = 4.5 V; IIK = 18 mA VOH HIGH-level output voltage VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V 0 C to +70 C Unit Min Typ[1] Max Min Max 1.2 0.73 - 1.2 - V IOH = 3 mA VCC = 10 % - - - 2.4 - V VCC = 5 % - 3.3 - 2.7 - V - - - 2.0 - V - - - - 0.55 V VCC = 5 % - 0.42 - - 0.55 V VCC = 0 V; VI = 7.0 V - - - - 100 A IOH = 15 mA VCC = 10 % VOL LOW-level output voltage VCC = 4.5 V; VIL = 0.8 V; VIH = 2.0 V IOL = 64 mA VCC = 10 % II input leakage current IIH HIGH-level input current VCC = 5.5 V; VI = 2.7 V - - - - 20 A IIL LOW-level input current - - - 20 - A IOZ OFF-state output current VCC = 5.5 V - - - - 50 A - - - 50 - A - - - 225 100 mA outputs HIGH-state - 17 - - 24 mA outputs LOW-state - 28 - - 40 mA outputs OFF-state - 25 - - 35 mA VCC = 5.5 V; VI = 0.5 V VO = 2.7 V VO = 0.5 V [2] IO output current VCC = 5.5 V ICC supply current VCC = 5.5 V; VI = GND or VCC [1] All typical values are measured at VCC = 5 V. [2] No more than one output should be tested at a time, and the duration of the test should not exceed one second. 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 4 of 12 74F125 NXP Semiconductors Quad buffers; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V. Test circuit is shown in Figure 6. Symbol Parameter 25 C; VCC = 5.0 V Conditions 0 C to +70 C; Unit VCC = 5.0 V  0.5 V Min Typ Max Min Max tPLH LOW to HIGH propagation delay nA to nY, see Figure 4 2.0 4.0 6.0 2.0 6.5 ns tPHL HIGH to LOW propagation delay nA to nY; see Figure 4 3.0 5.5 7.5 3.0 8.0 ns tPZH OFF-state to HIGH propagation delay nOE to nY; see Figure 5 3.5 5.5 7.5 3.5 8.5 ns tPZL OFF-state to LOW propagation delay nOE to nY; see Figure 5 4.0 6.0 8.0 4.0 9.0 ns tPHZ HIGH to OFF-state propagation delay nOE to nY; see Figure 5 1.5 3.5 5.0 1.5 6.0 ns tPLZ LOW to OFF-state propagation delay nOE to nY; see Figure 5 1.5 3.5 5.5 1.5 6.0 ns 11. Waveforms VI VM nA input GND tPHL tPLH VOH VM nY output VOL mna230 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 4. Propagation delay input (nA) to output (nY) 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 5 of 12 74F125 NXP Semiconductors Quad buffers; 3-state VI nOE input VM VM GND tPZL tPLZ 3.5 V output LOW-to-OFF OFF-to-LOW VM VOL + 0.3 V VOL tPHZ VOH tPZH VOH − 0.3 V output HIGH-to-OFF OFF-to-HIGH VM GND outputs enabled outputs enabled outputs disabled 001aal294 VM = 1.5 V VOL and VOH are typical voltage output levels that occur with the output load. Fig 5. Enable and disable times VI tW 90 % 90 % negative pulse VM 0V VCC 10 % tf tr tr tf VI 90 % positive pulse 0V VEXT VM 10 % VI DUT RT 90 % VM RL VO G CL RL VM 10 % mna616 10 % tW 001aai298 a. Input pulse definition b. Test circuit Test data is given in Table 8. Test circuit definitions: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = Test voltage for switching times. Fig 6. Table 8. Load circuitry for switching times Test data Input Load VEXT VI fi tW tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 3.0 V 1 MHz 500 ns  2.5 ns 50 pF 500  open open 7.0 V 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 6 of 12 74F125 NXP Semiconductors Quad buffers; 3-state 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 2.2 inches 0.17 0.02 0.13 0.068 0.044 0.021 0.015 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT27-1 050G04 MO-001 SC-501-14 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-13 Fig 7. Package outline SOT27-1 (DIP14) 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 7 of 12 74F125 NXP Semiconductors Quad buffers; 3-state SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 8. Package outline SOT108-1 (SO14) 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 8 of 12 74F125 NXP Semiconductors Quad buffers; 3-state 13. Abbreviations Table 9. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor LSTTL Low-power Schottky Transistor-Transistor Logic ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model CDM Charge-Device Model TTL Transistor-Transistor Logic 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes 74F125 v.3 20130118 Product data sheet - 74F125 v.2 Modifications: 74F125 v.2 74F125 Product data sheet • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 19890328 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 74F125 v.1 © NXP B.V. 2013. All rights reserved. 9 of 12 74F125 NXP Semiconductors Quad buffers; 3-state 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74F125 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 10 of 12 74F125 NXP Semiconductors Quad buffers; 3-state Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74F125 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 18 January 2013 © NXP B.V. 2013. All rights reserved. 11 of 12 74F125 NXP Semiconductors Quad buffers; 3-state 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 9 Legal information. . . . . . . . . . . . . . . . . . . . . . . 10 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 10 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . 11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 January 2013 Document identifier: 74F125