N74F821D,602

INTEGRATED CIRCUITS 74F821 10-bit bus interface register, non-inverting (3-State) Product data sheet Replaces data sheet 74F821/822/823/824/825/826 of 1996 Jan 05 
   2004 Jul 22 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) FEATURES 74F821 PIN CONFIGURATION • High speed parallel registers with positive edge-triggered D-type flip-flops • High performance bus interface buffering for wide data/address paths or buses carrying parity • High-impedance PNP base inputs for reduced loading (20 µA in HIGH and LOW states) • IIL is 20 µA versus 1000 µA for AM29821 series • Buffered control inputs to reduce AC effects • Ideal where high speed, light loading, or increased fan-in as required with MOS microprocessor • Positive and negative over-shoots are clamped to ground • 3-State outputs glitch free during power-up and power-down • Slim Dip 300 mil package • Broadside pinout compatible with AMD AM 29821 • Outputs sink 64 mA and source 24 mA OE 1 24 VCC D0 2 23 Q0 D1 3 22 Q1 D2 4 21 Q2 D3 5 20 Q3 D4 6 19 Q4 D5 7 18 Q5 D6 8 17 Q6 D7 9 16 Q7 D8 10 15 Q8 D9 11 14 Q9 GND 12 13 CP SF00482 DESCRIPTION The 74F821 bus interface register is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity. The 74F821 is a buffered 10-bit wide version of the popular 74F374/74F534 functions. TYPE 74F821 TYPICAL fmax TYPICAL SUPPLY CURRENT (TOTAL) 180 MHz 75 mA INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dn Data inputs 1.0/1.0 20 µA/0.6 mA CP Clock input 1.0/1.0 20 µA/0.6 mA OE Output enable input (active-LOW) 1.0/3.0 20 µA/1.8 mA Qn Data outputs 1200/106.7 24 mA/64 mA NOTE: One (1.0) FAST unit load is defined as: 20 µA in the HIGH state and 0.6 mA in the LOW state. ORDERING INFORMATION Commercial range: VCC = 5 V ± 10 %; Tamb = 0 °C to +70 °C Type number Package Name Description Version N74F821D SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 N74F821N DIP24 plastic dual in-line package; 24 leads (300 mil) SOT222-1 2004 Jul 22 2 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) LOGIC SYMBOL 74F821 IEC/IEEE SYMBOL 2 3 4 5 6 7 8 10 9 11 1 EN1 13 G2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 2 13 CP 1 OE 2D 23 1 3 22 4 21 5 20 6 19 7 18 8 17 14 9 16 SF00483 10 15 11 14 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 23 VCC = Pin 24 GND = Pin 12 22 21 20 19 18 17 16 15 SF00484 LOGIC DIAGRAM 74F821 D1 3 D0 2 D CP Q CP OE D2 4 D CP Q D3 5 D CP Q D4 6 D CP Q D5 7 D CP Q D6 8 D CP Q D8 10 D7 9 D CP Q D9 11 D CP Q D CP Q D CP Q 13 1 23 Q0 22 21 Q1 Q2 20 19 Q3 Q4 18 Q5 17 15 16 Q6 Q7 Q8 VCC = Pin 24 GND = Pin 12 SF00500 FUNCTION TABLE INPUTS H = h = L = l = NC= X = Z = ↑ = ↑ = OUTPUTS OE CP L ↑ l L L ↑ h H L ↑ X NC H X X Z Dn OPERATING MODE Q Load and read data Hold High-impedance HIGH-voltage level HIGH state must be present one setup time before the LOW-to-HIGH clock transition LOW-voltage level LOW state must be present one setup time before the LOW-to-HIGH clock transition No change Don’t care High–impedance “off” state LOW-to-HIGH clock transition Not LOW-to-HIGH clock transition 2004 Jul 22 14 Q9 3 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) 74F821 ABSOLUTE MAXIMUM RATINGS (Operation beyond the limit set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range.) SYMBOL PARAMETER RATING UNIT VCC Supply voltage –0.5 to +7.0 V VIN Input voltage –0.5 to +7.0 V IIN Input current VOUT Voltage applied to output in HIGH output state IOUT Current applied to output in LOW output state Tamb Operating free-air temperature range Tstg Storage temperature range –30 to +5 mA –0.5 to VCC V 128 mA 0 to +70 °C –65 to +150 °C RECOMMENDED OPERATING CONDITIONS LIMITS PARAMETER SYMBOL MIN NOM MAX UNIT VCC Supply voltage 4.5 5.0 5.5 V VIH HIGH-level input voltage 2.0 – – V VIL LOW-level input voltage – – 0.8 V IIk Input clamp current – – –18 mA IOH HIGH–level output current – – –24 mA IOL LOW–level output current – – 64 mA Tamb Operating free-air temperature range 0 – +70 °C 2004 Jul 22 4 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) 74F821 DC ELECTRICAL CHARACTERISTICS (Over recommended operating free-air temperature range unless otherwise noted.) SYMBOL VOH O LIMITS TEST CONDITIONS1 PARAMETER VCC = MIN; VIL = MAX; VIH = MIN HIGH level output voltage HIGH-level VCC = MIN; VIL = MAX; VIH = MIN IOH 15 mA O = –15 IOH 24 mA O = –24 TYP2 MAX ± 10 %VCC 2.4 – – V ± 5 %VCC 2.4 – – V ± 10 %VCC 2.0 – – V ± 5 %VCC 2.0 – – V ± 10 %VCC – – 0.55 V ± 5 %VCC – 0.42 0.55 V VOL O LOW level output voltage LOW-level VIK Input clamp voltage VCC = MIN; II = IIK – –0.73 –1.2 V II Input current at maximum input voltage VCC = 0 V; VI = 7.0 V – – 100 µA IIH HIGH–level input current VCC = MAX; VI = 2.7 V – – 20 µA IIL LOW–level input current VCC = MAX; VI = 0.5 V – – –20 µA IOZH Off–state output current, HIGH–level voltage applied VCC = MAX; VO = 2.7 V – – 50 µA IOZL Off–state output current, LOW–level voltage applied VCC = MAX; VO = 0.5 V – – –50 µA IOS Short–circuit output current3 VCC = MAX –100 – –225 mA – 75 105 mA ICC Supply current (total) – 75 105 mA – 75 115 mA ICCH ICCL VCC = MAX ICCZ IOL O = MAX UNIT MIN NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions for the applicable type. 2. All typical values are at VCC = 5 V, Tamb = 25 °C. 3. Not more than one output should be shorted at a time. For testing IOS, the use of high-speed test apparatus and/or sample-and-hold techniques are preferable in order to minimize internal heating and more accurately reflect operational values. Otherwise, prolonged shorting of a HIGH output may raise the chip temperature well above normal and thereby cause invalid readings in other parameter tests. In any sequence of parameter tests, IOS tests should be performed last. 2004 Jul 22 5 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) 74F821 AC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL TEST CONDITION PARAMETER Tamb = +25 °C VCC = +5.0 V CL = 50 pF, RL = 500 Ω Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10 % CL = 50 pF, RL = 500 Ω UNIT MIN TYP MAX MIN Waveform 1 150 180 – 140 – ns Propagation delay CP to Qn Waveform 1 4.0 4.0 6.5 6.0 8.5 8.5 4.0 3.5 9.5 9.0 ns tPZH tPZL Output enable time OEn to Qn Waveform 3 Waveform 4 2.0 3.0 4.5 5.0 8.0 8.0 2.0 2.5 9.0 9.0 ns tPHZ tPLZ Output disable time OEn to Qn Waveform 3 Waveform 4 1.5 1.5 3.5 3.5 6.5 6.5 1.5 1.5 7.5 7.5 ns TEST CONDITION Tamb = +25 °C VCC = +5.0 V CL = 50 pF, RL = 500 Ω fmax Maximum clock frequency tPLH tPHL MAX AC SETUP REQUIREMENTS LIMITS SYMBOL PARAMETER Tamb = 0 °C to +70 °C VCC = +5.0 V ± 10 % CL = 50 pF, RL = 500 Ω MIN TYP MAX MIN MAX UNIT tsu (H) tsu (L) Setup time, HIGH or LOW Dn to CP Waveform 2 1.0 1.0 – – – – 1.0 1.0 – – ns th (H) th (L) Hold time, HIGH or LOW Dn to CP Waveform 2 2.0 2.0 – – – – 2.0 2.0 – – ns tw (H) tw (L) CP Pulse width, HIGH or LOW Waveform 1 3.5 3.5 – – – – 4.0 4.0 – – ns AC WAVEFORMS For all waveforms, VM = 1.5 V. The shaded areas indicate when the input is permitted to change for predictable output performance. 1/fmax OEn CP VM VM tw(H) tPLH tw(L) VM Qn VM VM tPZH tPHZ VM tPHL Qn VM 0V VM SF00506 SF00509 Waveform 3. 3-State output enable time to HIGH level and output disable time from HIGH level Waveform 1. Propagation delay for clock input to output, clock pulse width, and maximum clock frequency OEn Dn VM tsu(H) VM th(H) VM CP VM tsu(L) VOH – 0.3 V VM VM VM tPZL th(L) Qn tPLZ 3.5V VM VM VOL + 0.3 V SF00510 SF00508 Waveform 2. 2004 Jul 22 Waveform 4. 3-State output enable time to LOW level and output disable time from LOW level Data setup time and hold times 6 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) 74F821 TEST CIRCUIT AND WAVEFORMS VCC 7.0 V VIN RL VOUT PULSE GENERATOR tw 90% NEGATIVE PULSE VM CL AMP (V) VM 10% D.U.T. RT 90% 10% tTHL (tf ) tTLH (tr ) tTLH (tr ) tTHL (tf ) 0V RL AMP (V) 90% 90% Test Circuit for Open Collector Outputs POSITIVE PULSE VM VM 10% TEST tPLZ tPZL All other SWITCH closed closed open DEFINITIONS: RL = Load resistor; see AC electrical characteristics for value. CL = Load capacitance includes jig and probe capacitance; see AC electrical characteristics for value. RT = Termination resistance should be equal to ZOUT of pulse generators. 10% tw SWITCH POSITION 0V Input Pulse Definition INPUT PULSE REQUIREMENTS family amplitude VM 74F 3.0 V 1.5 V rep. rate 1 MHz tw tTLH 500 ns 2.5 ns tTHL 2.5 ns SF00128 2004 Jul 22 7 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) SO24: plastic small outline package; 24 leads; body width 7.5 mm 2004 Jul 22 8 74F821 SOT137-1 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) DIP24: plastic dual in-line package; 24 leads (300 mil) 2004 Jul 22 9 74F821 SOT222-1 Philips Semiconductors Product data sheet 10-bit bus interface register, non-inverting (3-State) 74F821 REVISION HISTORY Rev Date Description _3 20040722 (74F821_3) Product data sheet (9397 750 13819). Replaces data sheet 74F821/822/823/824/825/826 of 1996 Jan 05 (9397 750 05185). Modifications: • Remove part numbers 74F822/823/824/825/826 and references to them. _2 19960105 (74F821–74F826_2) Product specification (9397 750 05185). ECN 853-1304 16195 of 05 January 1996. Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data sheet Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data sheet Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data sheet Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.  Koninklijke Philips Electronics N.V. 2004 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 07-04 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 
   2004 Jul 22 10 9397 750 13819