NE57810

NE57810 Advanced DDR memory termination power with external reference voltage in Rev. 04 — 24 November 2008 Product data sheet 1. Introduction The NE57810 is designed to provide power for termination of a Double Data Rate (DDR) SDRAM memory bus. It significantly reduces parts count, board space, and overall system cost compared to previous solutions. 2. General description The NE57810 DDR termination regulator maintains an output voltage (DDR reference bus voltage) that is half the RAM supply voltage. It is capable of providing up to ± 3.5 A for sustained periods. Overcurrent limiting protects the NE57810 from inrush currents at start-up. Overtemperature shutdown protects the device in extreme temperature situations. The package is thermally robust for flexibility of thermal design. The NE57810 is a linear regulator so no external inductors or switching FETs are necessary. Fast response to load changes reduces the need for output capacitors. 3. Features I I I I I I I I I Fast transient response time Overtemperature protection Overcurrent protection Commercial (0 °C to +70 °C) temperature range Reduced need for external components (switching FETs, inductors, decoupling capacitors) Internal divider maintains termination voltage at half the memory supply voltage Reference out for other memory and control components Optional external voltage reference in for flexible application Compatible with DDR-I (VDD = 2.5 V) or DDR-II (VDD = 1.8 V) SDRAM systems 4. Applications I I I I I I Desktop microcomputer systems Workstations Servers Game machines Set top boxes Embedded systems NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in I Digital video recorders 5. Ordering information Table 1. Ordering information Package Name NE57810S Description plastic single-ended surface-mounted package; 5 leads Version SOT756 Type number 6. Functional diagram DIMM0 DIMM1 RefOut ExtRefIn (optional) Contrtol and address 0.1 µF VTT MEMORY CONTROLLER Data 100 µF NE57810 TERMINATOR POWER RS 27 Ω (typical) RT 27 Ω (typical) 014aaa407 Fig 1. Simplified system diagram 7. Pinning information 7.1 Pinning Table 2. Symbol VTT VDD VSS ExtRefIn RefOut [1] Pinning Pin 1 2 3 4 5 Description Regulated terminator voltage Power supply Circuit ground[1] External reference voltage in Reference voltage out 12345 mb Simplified outline The thermal pad on the rear of the device (shown by dotted outline) is connected electrically to VSS internally and provides enhancement to thermal conductivity. It should not be used as the primary connection to ground as device specifications indicate the use of the VSS pin for this purpose. NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 2 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in 8. Application design-in information The NE57810 can be used in a variety of DDR memory configurations. Its small footprint, fast transient response and reduced need for large bulk output capacitance, makes it highly adaptable. Some of examples methods of use are described in the following sections. 8.1 Normal operating mode (VTT = VDDR/2) The most common implementation of a DDR terminator regulator using the NE57810 is shown in Figure 2. The NE57810 has an internal resistor divider between the VDD (pin 2) and VSS (pin 3) pins which maintains the output voltage, VTT, at VDD/2. Typically, the VDD voltage is the DDR RAM supply voltage, which can range from 1.8 V to 2.5 V. The center node of this resistor divider is connected to ExtRefIn (pin 4). This node acts as the reference for the VTT output voltage and the buffered RefOut signal (pin 5). If the ExtRefIn pin is not connected to other voltage sources, two small bypass capacitors (0.01 µF) should be placed between the ExtRefIn pin and the VSS and VDD pins to improve the terminator’s noise performance. These two capacitors improve enable the terminator to better track any variations in the memory VDD voltage. This method can be seen in Figure 2. +VDD 2 0.01µF VDD 1 5 COUT (LF) COUT (HF) +VTT NE57810 CIN 4 ExtRefIn RefOut 0.01µF VSS 3 GND GND VREF 014aaa409 Fig 2. Normal operating method (VTT = VDD/2) There are two components to the memory signal load: a high frequency component caused by the 266 MHz plus speed of the address, data and control buses, and a low frequency component caused by the time-average skew of all of the bus states away from an equal number of 1s and 0s. Electrolytic and tantalum capacitors show inductance at the high frequencies, so two types of capacitors are required for output filtering. A very good, low ESR bulk electrolytic capacitor of no less than 470 µF should be placed next to the terminator which, in turn, should be placed as close as possible to the memory array. Multiple high frequency ceramic filter capacitors are also needed for high speed transient filtering and output stability. These capacitors may be from VTT to VSS (shown in the diagrams) or one half from VTT to VDD and the other half from VTT to VSS so the output will better track any variations in the VDD voltage. NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 3 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in For different memory sizes, the values of the recommended output filter capacitances will change. For a 256 MB memory space, for example, approximately 100 µF of ceramic surface mount chip capacitors should be evenly distributed across the physical memory layout. Depending upon the PCB noise environment, this can be 10 pieces of 10 µF, 20 pieces of 5 µF, and so on. 8.2 Externally programmed VTT output voltage The NE57810 enables use of an external reference voltage to set its VTT output voltage. This pin (ExtRefIn pin 4) is used for applications where the VTT voltage is not VDD divided by 2. This allows VTT voltage and current to be drawn from a power supply bus that is not the DDR RAM supply voltage. This has some advantages when you are attempting to better match the power being drawn from the outputs emerging from the main system power supply. This can be seen in Figure 3. The internal reference voltage is set by two matched 100 kΩ resistors connected in a resistor divider between the VDD and VSS pins of the NE57810 VREF External Reference In +VDD VDD VTT +VTT NE57810 ExtRefIn CIN RefOut COUT (LF) COUT (HF) VSS GND GND 014aaa419 Fig 3. Externally programmed VTT 8.3 Cascading the NE57810 For high-performance computer systems, sometimes memory banks are driven 180 degrees out of phase with one another in such a way that the apparent access time is halved (even and odd memory addresses). To do this, NXP recommends that two NE57810s are used, one to terminate each memory bank. Cascading NE57810 terminators offers two advantages, it improves the system noise performance by bringing the memory SIMMs closer to the terminator, and it distributes any heat generated by the terminator system. By using the RefOut pin from one NE57810 to the ExtRefIn pin for the other NE57810(s) used in the system, one can always guarantee that the VTT voltages are identical. Because of the very tight output voltage regulation of the NE57810, the VTT outputs should never be wired together. This is because the terminators would ‘fight’ one another if their output were different by only a few millivolts. This method can be used in either the normal operating mode and the externally programmed operating mode. This method of use can be seen in Figure 4. NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 4 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in VREF +VDD VDD ExtRefIn CIN Master VTT RefOut COUT (LF) COUT (HF) +VTT1 NE57810 VSS GND GND (HF) VDD ExtRefIn CIN Slave VTT RefOut COUT (LF) COUT (HF) +VTT NE57810 VSS To other NE5781s GND 014aaa420 Fig 4. Cascading terminator systems for complex memory systems 9. Technical description The NE57810 supplies power to the DDR memory bus termination resistors at nominally half the voltage supplied to the memory ICs or DIMMs. DDR memory output drivers source and sink current into and out of their outputs. A typical DDR memory system is seen in Figure 1. Each input/output pin on the bus has a series 20 Ω resistor connected to it. The bus is terminated to the DDR terminator through a 27 Ω to 50 Ω resistance. The memory system then requires current from the VTT terminator bus only when the instantaneous values of the aggregate bus state are not equal amounts of 1s and 0s. When memory bus speeds are in the 200 MHz to 300 MHz region, the period of any single bus state is extremely small. This permits the DDR bus termination regulator to be a linear power operational amplifier that can source and sink current instantly to the DDR bus from the VDD supply voltage. Figure 6 models the VTT loading condition of each bus line equivalent circuit during operation and with terminating resistors. NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 5 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in VDD VDD VDD VDD ExtRefIn 100 kΩ OVERCURRENT OVERTEMPERATURE RefOut 100 kΩ VTT a. '0' data b. '1' data 014aaa424 VSS 014aaa410 Fig 5. VTT loading conditions Fig 6. Block diagram This yields the worst case current loading Equation 1: N DDR V DD I O(max) = -------------------------2 ( RT + RS ) Where: (1) • NDDR is the total number of terminated control, address and data lines within the DDR memory system. (typically 192). • RT is the value of the terminating resistors. • RS is the value of the series resistors from the active output driver. Hence the worst case current loading condition, where there are either all 1s or all 0s for an instant, and RT is 27 Ω and RS is 20 Ω, produces an instantaneous output current of either +3.5 A or −3.5 A. 10. Thermal design Designing the proper thermal system for the NE57810 is important for its reliable operation. The NE57810 will be operating at an average power level less than the maximum rating of the part. In a typical DDR terminator system the average power dissipation is between 0.8 W and 1.5 W. The termination power will vary as the average number of 1s and 0s changes during normal operation of the DDR memory. The load current will assume a new value for each bus cycle at a 266 MHz rate, and will increase and decrease as the statistical average of bus states change. The terminator heat sink must be designed to accommodate the average power as a steady state condition and be able to withstand momentary periods of increased dissipation, typically 2 seconds to 5 seconds duration. For the typical NE57810 application, the power dissipated by the terminator can be calculated by Equation 2: P D = I DD × V TT W NE57810_4 (2) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 6 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in The thermal resistance of a surface mount package is given as Rth(j-a), the thermal resistance from the junction to air. JESD51-7 specifies a 4-layer multilayer PCB (2 oz/1 oz/1 oz/2 oz copper) that is 4 inches on each side. This is probably the best (or lowest) thermal resistance you will see in any application. Most applications cannot afford the PCB area to create this situation, but the thermal performance of a multilayer PCB will still provide a significant heatsinking effect. The actual thermal resistance will be higher than the 16.5 °C/W given for the 4-layer JEDEC PCB. Figure 7 shows the thermal resistance you can expect for heatsinking PCB areas less than the JEDEC specification. The graph is for a 2 oz single-sided PCB with a square area of the side dimension as given on the X-axis. If you use a double-sided PCB with some plated-through holes to help transfer heat to the bottom side, the thermal resistance only improves by about 3 °C/W to 4 °C/W. 40.0 10 0.25 s 0.5 s DC IDD (A) 1 30.0 Thermal resistance 20.0 (°C/W) 10.0 0.0 0 20 40 60 80 Length of side of 2 oz. copper area (mm) 100 0.1 1 2 3 4 VDD (V) 5 6 7 8 9 10 014aaa426 014aaa425 Fig 7. PCB heat sink area versus thermal resistance Fig 8. Safe operating area for the NE57810 After the power is estimated, the minimum PCB area can be determined by calculating the worst case thermal resistance and, based on Figure 7, determine the PCB area. This is done by Equation 3: T j – T amb R qJA(min) = ----------------------PD Where: (3) • Tj is the maximum desired junction temperature. • Tamb is the highest expected local ambient temperature. • PD is the estimated average power The junction temperature should be kept well away from the overtemperature cut-off threshold temperature (+150 °C) in normal operation. Using the above power dissipation, the highest ambient temperature and a junction temperature of +125 °C, calculate the maximum thermal resistance using Equation 4, (1.5 W is used only as an example). 125 ° C – 70 ° C R th((j-a)(min)) = ---------------------------------- = 36.6 ° C /W 1.5W NE57810_4 (4) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 7 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in Looking at Figure 7, you see that this power dissipation requires a minimum PCB island area of 225 mm2 (15 mm on each side). This is the smallest area you could use at this power dissipation. Of course, increasing this area will allow the NE57810 to operate at cooler temperatures, thus enhancing its long-term reliability. 11. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD Tamb Tstg Tj PD [1] Parameter supply voltage ambient temperature storage temperature junction temperature power dissipation Conditions VDD to VSS voltage Min −0.3 0 −40 [1] Max +3.6 +70 +165 160 3.3 Unit V °C °C °C W - Tested on a minimum footprint on a four-layer PCB per JEDEC specification JESD51-7 12. Thermal characteristics Table 4. Symbol Rth(j-a) Thermal characteristics Parameter thermal resistance from junction to ambient Conditions Typ 16.5 Unit °C/W 13. Characteristics Table 5. Characteristics Tamb = 0 °C to +70 °C, VDD = 2.5 V; ITT = –3.5 A to +3.5 A, unless otherwise specified. Symbol VTT VACC VDD IQ ITT ∆VTT CLOAD VTT Parameter output voltage output voltage accuracy supply voltage supply current output current load regulation load capacitance output voltage swing output voltage accuracy line regulation ITT = 0 A ExtRefIn = 1.25 V; VDD = 2.25 – 3.6 V [3] Conditions ExtRefIn not connected [1] Min −15 1.6 −3.5 −2.5 −18 [2] Typ VDD/2 14 ±6 100 50 - Max +15 3.6 30 +3.5 +2.5 +18 VDD − 0.8 +15 +6 Unit V mV V mA A A mV mV µF V kΩ mV mV ITT = 0 A 2.5 V ≤ VDD ≤ 3.6 V VDD = 1.6 V ITT = ± 1.0 A ITT = ± 3.5 A stable operation 0.8 35 −15 −6 External reference in Rin(ExtRefIn) input impedance NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 8 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in Table 5. Characteristics …continued Tamb = 0 °C to +70 °C, VDD = 2.5 V; ITT = –3.5 A to +3.5 A, unless otherwise specified. Symbol RefOut IrefOut CLOAD IIlim Tlim Parameter voltage reference out reference out current max load capacitance current limit temperature shutdown temperature shutdown hysteresis [1] [2] [3] [4] VACC = VTT − VDD/2. Ceramic capacitors only. Low ESR electrolytic capacitors are not necessary. Voltage accuracy refers to voltage at ExtRefIn pin. RefOut voltage referenced to 0.5 VDD if ExtRefIn is not connected. Conditions IrefOut = 0 A; source or sink stable operation [4] Min −15 2.2 0.1 3.6 - Typ ExtRefIn 3 4.5 150 20 Max +15 6.5 - Unit mV mA µF A °C °C Reference out Power stage 14. Typical performance curves Figure 9 through Figure 13 show the typical performance curves for the NE57810. NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 9 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in +5 mV VTT 0.5 mV 2 −3 A ITT 1 +3 A CH3 25.0 mV Ch4 10.0 mV M10.0 µs CH1 200 mV Ch2 200 mV 014aaa427 M50.0 µs Ch2 −100 mV 014aaa428 Fig 9. VTT transient response (output filter 50 µF ceramic) Fig 10. VDD to VTT response (output filter 50 µF ceramic) VTT VTT −35 A VREF Input ITT +35 A CH1 500 mv Ch2 500 mV M10.0 µs 014aaa421 CH3 25.0 mV Ch4 10.0 mV M10.0 µs 014aaa422 Fig 11. VREF to VTT transient response (output filter 820 µF + 50 µF ceramic) Fig 12. VREF to VTT transient response (output filter 50 µF ceramic) NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 10 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in 1.300 Normal operating region 1.280 1.260 Volts 1.240 Output sink 1.220 Output source 1.200 −6 −4 −2 0 Amps 2 4 6 014aaa429 Fig 13. Typical VTT versus output current (VDD = 2.5 V at 25 °C) 15. Test information Figure 14, Figure 15 and Figure 16 show the diagrams for the NE57810 test circuits. NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 11 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in 2 VDD NE57810 VIN 820 µF Oscon 4 ExtRefIn VTT 1 R (Load) 0.01 µF VSS 3 (5 ea) 10 µF Ceramic 820 µF Oscon V Light load Heavy load 014aaa411 Fig 14. Load transient test (+3 A to –3 A) 2 VDD NE57810 4 VIN ExtRefIn VTT 1 R (Load) VSS 3 (5 ea) 10 µF Ceramic 820 µF Oscon V Light load Heavy load 014aaa412 Fig 15. ExtRefIn to VTT transient test VIN 0.4 V 2 VDD NE57810 VIN 2.5 V 4 ExtRefIn VTT 1 0.01µF VSS 3 V 014aaa423 Fig 16. VDD to VTT transient test NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 12 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in 16. Package outline Plastic single-ended surface-mounted package; 5 leads SOT756 D D1 D2 A A1 mounting base E1 E HE E2 1 2 3 4 5 e b w M c 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A 2.05 1.75 A1 0.3 0.2 b 0.76 0.65 c 0.3 0.2 D 9.60 9.25 D1 9.15 8.85 D2 5.75 5.45 E 9.20 8.85 E1 7.65 7.40 E2 8.15 7.85 e 1.7 HE 10.7 10.4 w 0.25 OUTLINE VERSION SOT756 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 08-02-08 08-02-15 Fig 17. Package outline SOT756 NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 13 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in 17. Revision history Table 6. Revision history Release date 20081124 Data sheet status Product data sheet Product data sheet Product data sheet Product data sheet Change notice Supersedes NE57810_3 NE57810_2 NE57810_1 Document ID NE57810_4 Modifications: NE57810_3 NE57810_2 NE57810_1 • The values for IIlim in Table 5 has been updated. 20080702 20030912 20020716 NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 14 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in 18. Legal information 18.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 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Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NE57810_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 24 November 2008 15 of 16 NXP Semiconductors NE57810 Advanced DDR memory termination power with external reference voltage in 20. Contents 1 2 3 4 5 6 7 7.1 8 8.1 8.2 8.3 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Application design-in information . . . . . . . . . . 3 Normal operating mode (VTT = VDDR/2) . . . . . . 3 Externally programmed VTT output voltage . . . 4 Cascading the NE57810. . . . . . . . . . . . . . . . . . 4 Technical description . . . . . . . . . . . . . . . . . . . . 5 Thermal design . . . . . . . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal characteristics. . . . . . . . . . . . . . . . . . . 8 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Typical performance curves . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 November 2008 Document identifier: NE57810_4