NTSX2102
Dual supply translating transceiver; open-drain; auto
direction sensing
Rev. 2.3 — 6 October 2022
1
Product data sheet
General description
The NTSX2102 is a 2-bit, dual supply translating transceiver with auto direction sensing,
that enables bidirectional voltage level translation. It features two 2-bit input-output ports
(An and Bn), one output enable input (OE) and two supply pins (VCC(A) and VCC(B)).
Both supplies can be supplied at any voltage between 1.65 V and 5.5 V. This flexibility
makes the device suitable for translating between any of the voltage nodes (1.8 V, 2.5 V,
3.3 V, and 5.0 V). Pins An and OE are referenced to VCC(A) and pins Bn are referenced
to VCC(B). A LOW level at pin OE causes the outputs to assume a high-impedance OFFstate. This device is fully specified for partial power-down applications using IOFF. The
IOFF circuitry disables the output, preventing the damaging backflow current through the
device when it is powered down.
2
Features and benefits
• Wide supply voltage range:
– VCC(A): 1.65 V to 5.5 V and VCC(B): 1.65 V to 5.5 V
• Maximum data rates:
– 50 Mbit/s
• IOFF circuitry provides partial power-down mode operation
• Inputs accept voltages up to 5.5 V
• ESD protection:
– HBM JS-001 Class 2 exceeds 2000 V
– CDM JESD22-C101E exceeds 2000 V
• Latch-up performance exceeds 100 mA per JESD 78B Class II
• Multiple package options
• Specified from –40 °C to +85 °C
3
Applications
2
• I C/SMBus
• UART
• GPIO
NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
4
Ordering information
Table 1. Ordering information
Type number
Topside
marking
Package
Name
Description
Version
NTSX2102GU8
sX
XQFN8
plastic, extremely thin quad flat package; no
leads; 8 terminals; body 1.4 × 1.2 × 0.5 mm
SOT1309-1
NTSX2102GD
sX2
XSON8
plastic extremely thin small outline package; no
leads; 8 terminals; body 3 × 2 × 0.5 mm
SOT996-2
NTSX2102TL
tX2
XSON8
plastic extremely thin small outline package; no
leads; 8 terminals; body 3 × 2 × 0.5 mm
SOT1052-2
4.1 Ordering options
Table 2. Ordering options
Type number
Orderable part
number
Package
Packing
[1]
method
Minimum order
quantity
Temperature
NTSX2102GU8
NTSX2102GU8H
XQFN8
Reel 7" Q3 NDP
4000
–40 °C to +85 °C
NTSX2102GDH
XSON8
Reel 7" Q3 NDP
3000
–40 °C to +85 °C
NTSX2102TLH
XSON8
Reel 7" Q3 NDP
4000
–40 °C to +85 °C
NTSX2102GD
[2]
NTSX2102TL
[1]
[2]
5
Standard packing quantities and other packaging data are available at www.nxp.com/packages/.
Discontinuation Notice 202111012DN - drop in replacement is NTSX0102TLH.
The TL package has a center pad vs no center pad for the GD package. The TL package pad is not electrically connected to the silicon and is not required
to connect to the PCB so it can drop onto the GD package PCB layout. If the existing GD package has a trace underneath the risk is low since the TL
package center pad is not connected to the silicon. If there are multiple traces there could be EMI and cross talk. In both cases the customer needs to
evaluate risk.
Note: The length and width are reversed between the "GD" and "TL" package drawings but the shorter edge contains the pins and is 2.0 mm in both
cases.
Functional diagram
OE
A2
6
levelshifter
4
one shot
1
one shot
A1
5
B2
one shot
8
one shot
VCC(A)
B1
VCC(B)
aaa-005252
Figure 1. Logic symbol
NTSX2102
Product data sheet
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NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
6
Pinning information
6.1 Pinning
NTSX2102
NTSX2102
1 VCC(A)
terminal 1
index area
8 VCC(B)
A2 3
7 B1
GND 4
6 B2
OE 5
A1 2
VCC(A)
1
8
VCC(B)
A1
2
7
B1
A2
3
6
B2
GND
4
5
OE
aaa-005254
aaa-005255
Transparent top view
Transparent top view
Figure 2. Pin configuration SOT1309-1 (XQFN8)
Figure 3. Pin configuration SOT996-2 (XSON8)
NTSX2102TL
VCC(A)
1
8
VCC(B)
A1
2
7
B1
A2
3
6
B2
GND
4
5
OE
aaa-044520
Transparent top view
Figure 4. Pin configuration SOT1052-2 (XSON8)
6.2 Pin description
Table 3. Pin description
Symbol
Pin
Description
B2, B1
6, 7
data input or output (referenced to VCC(B))
GND
4
ground (0 V)
VCC(A)
1
supply voltage A
A2, A1
3, 2
data input or output (referenced to VCC(A))
OE
5
output enable input (active HIGH; referenced to VCC(A))
VCC(B)
8
supply voltage B
NTSX2102
Product data sheet
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NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
7
Functional description
Table 4. Function table
[1]
Supply voltage
Input
Input/output
VCC(A)
VCC(B)
OE
An
Bn
1.65 V to 5.5 V
1.65 V to 5.5 V
L
Z
Z
1.65 V to 5.5 V
1.65 V to 5.5 V
H
input or output
output or input
X
Z
Z
GND
[1]
[2]
[2]
GND
[2]
H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
When either VCC(A) or VCC(B) is at GND level, the device goes into power-down mode.
8
Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC(A)
supply voltage A
VCC(B)
supply voltage B
VI
input voltage
VO
output voltage
Conditions
Min
Max
Unit
–0.5
+6.5
V
–0.5
+6.5
V
A port and OE input
[1] [2]
–0.5
+6.5
V
B port
[1] [2]
–0.5
+6.5
V
Active mode
[1] [2]
–0.5
VCCO + 0.5
V
–0.5
+6.5
V
–50
—
mA
–50
—
mA
—
±50
mA
—
100
mA
A or B port
Power-down or 3-state mode
[1]
A or B port
IIK
input clamping current
VI < 0 V
IOK
output clamping current
VO < 0 V
[2]
IO
output current
VO = 0 V to VCCO
ICC
supply current
ICC(A) or ICC(B)
IGND
ground current
–100
—
mA
Tstg
storage temperature
–65
+150
°C
Ptot
total power dissipation
—
250
mW
[1]
[2]
9
Tamb = –40 °C to +85 °C
If the input and output current ratings are observed, the minimum input and minimum output voltage ratings may be exceeded.
VCCO is the supply voltage associated with the output.
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol
Parameter
VCC(A)
VCC(B)
[1]
Min
Max
Unit
supply voltage A
1.65
5.5
V
supply voltage B
1.65
5.5
V
NTSX2102
Product data sheet
Conditions
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NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
Table 6. Recommended operating conditions
Symbol
Parameter
Tamb
ambient temperature
Δt/ΔV
input transition rise and fall rate
[1]
...continued
Conditions
Max
Unit
–40
+85
°C
—
10
ns/V
A, B or OE port
VCC(A) = 1.65 V to 5.5 V;
VCC(B) = 1.65 V to 5.5 V
[1]
Min
Hold the A and B sides of an unused I/O pair in the same state, both at VCCI or both at GND.
10 Static characteristics
Table 7. Typical static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); Tamb = 25 °C.
Symbol Parameter
Conditions
Min
Typ
Max
Unit
CI
input
capacitance
OE input; VCC(A) = VCC(B) = 0 V
—
2.2
—
pF
CI/O
input/output
capacitance
A or B port; VCC(A) = 5.0 V; VCC(B) = 5.0 V
—
10
—
pF
Table 8. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
VIH
Parameter
HIGH-level input
voltage
Conditions
-40 °C to +85 °C
Unit
Min
Max
VCCI – 0.4
—
V
0.65VCC(A)
—
V
—
0.4
V
—
0.35VCC(A)
V
A or B port
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V
[1]
OE input
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V
VIL
LOW-level input
voltage
A or B port
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V
OE input
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V
[2]
LOW-level output
voltage
A or B port; IO = 6 mA
VI ≤ 0.15 V; VCC(A) = 1.65 V to 5.5 V; VCC(B) =
1.65 V to 5.5 V
—
0.4
V
II
input leakage
current
OE input; VI = 0 V to VCC(A); VCC(A) = 1.65 V to 5.5 V;
VCC(B) = 1.65 V to 5.5 V
—
±1
μA
IOZ
OFF-state output
current
A or B port; VO = 0 V or VCCO; VCC(A) = 0 V to 5.5 V;
VCC(B) = 0 V to 5.5 V
—
±2
μA
IOFF
power-off leakage A port; VI or VO = 0 V to 5.5 V; VCC(A) = 0 V; VCC(B) =
current
0 V to 5.5 V
—
±2
μA
B port; VI or VO = 0 V to 5.5 V; VCC(B) = 0 V; VCC(A) =
0 V to 5.5 V
—
±2
μA
VOL
NTSX2102
Product data sheet
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[2]
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NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
Table 8. Static characteristics...continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
ICC
Parameter
supply current
Conditions
-40 °C to +85 °C
Unit
Min
Max
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V;
OE = LOW or HIGH
—
5
μA
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 0 V
—
2
μA
VCC(A) = 0 V; VCC(B) = 1.65 V to 5.5 V
—
–2
μA
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 1.65 V to 5.5 V;
OE = LOW
—
5
μA
VCC(A) = 1.65 V to 5.5 V; VCC(B) = 0 V
—
–2
μA
VCC(A) = 0 V; VCC(B) = 1.65 V to 5.5 V
—
2
μA
[1]
VI = 0 V or VCCI; IO = 0 A
ICC(A)
ICC(B)
[1]
[2]
VCCI is the supply voltage associated with the input.
VCCO is the supply voltage associated with the output.
11 Dynamic characteristics
Table 9. Typical dynamic characteristics for temperature 25 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for waveforms see Figure 5 and Figure 6.
Symbol
Parameter
[1]
Conditions
VCCO
Unit
1.8 V
2.5 V
3.3 V
5.0 V
tTLH
LOW to HIGH
output transition
time
A or B port
7
5
4
3
ns
tTHL
HIGH to LOW
output transition
time
A or B port
4
6
8
11
ns
CPD
power dissipation
capacitance
OE = VCC(A); VCC(A) = VCC(B);
[2]
fI = 400 kHz; VI = VCCI
—
—
—
13.5
pF
[1]
[2]
[3]
[3]
VCCO is the supply voltage associated with the output.
VCCI is the supply voltage associated with the input.
CPD is used to determine the dynamic power dissipation (PD in μW).
2
2
PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
2
Σ(CL × VCC × fo) = sum of the outputs.
NTSX2102
Product data sheet
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NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
[1]
Table 10. Dynamic characteristics for temperature range -40 °C to +85 °C
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Typ
Max
Typ
Max
Typ
Max
Typ
Max
VCC(A) = 1.8 V ± 0.15 V
tPHL
HIGH to LOW
A to B
propagation delay
3
7
3
6
3
5
5
7
ns
tPLH
LOW to HIGH
A to B
propagation delay
5
12
5
8
4
8
4
7
ns
tPHL
HIGH to LOW
B to A
propagation delay
3
7
3
6
3
5
5
7
ns
tPLH
LOW to HIGH
B to A
propagation delay
5
12
1
3
1
2
1
2
ns
tPZL
OFF-state to LOW OE to A
propagation delay
OE to B
9
16
9
18
10
14
10
15
ns
9
16
6
12
6
12
6
14
ns
LOW to OFF-state OE to A
propagation delay
OE to B
100
120
100
120
100
120
100
120
ns
100
120
100
120
100
120
100
120
ns
—
1
—
1
—
1
—
1
ns
—
18
—
18
—
18
—
18
Mbit/
s
tPLZ
tsk(o)
output skew time
fdata
data rate
between channels
[2]
VCC(A) = 2.5 V ± 0.2 V
tPHL
HIGH to LOW
A to B
propagation delay
3
6
2
5
2
5
2
5
ns
tPLH
LOW to HIGH
A to B
propagation delay
1
3
2
4
2.5
7
2.5
5
ns
tPHL
HIGH to LOW
B to A
propagation delay
3
6
2
5
2
5
2
5
ns
tPLH
LOW to HIGH
B to A
propagation delay
5
8
2
4
1.5
3
1
3
ns
tPZL
OFF-state to LOW OE to A
propagation delay
OE to B
6
12
5
10
8
10
5
8
ns
9
18
5
10
4.5
9
4
8
ns
LOW to OFF-state OE to A
propagation delay
OE to B
100
120
100
120
100
120
100
120
ns
100
120
100
120
100
120
100
120
ns
—
1
—
1
—
1
—
1
ns
—
18
—
32
—
32
—
32
Mbit/
s
tPLZ
tsk(o)
output skew time
fdata
data rate
between channels
[2]
VCC(A) = 3.3 V ± 0.3 V
tPHL
HIGH to LOW
A to B
propagation delay
3
5
2
5
2
4
2
4
ns
tPLH
LOW to HIGH
A to B
propagation delay
1
2
1.5
3
1.5
3
2
4
ns
NTSX2102
Product data sheet
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NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
[1]
Table 10. Dynamic characteristics for temperature range -40 °C to +85 °C ...continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7; for wave forms see Figure 5 and Figure 6.
Symbol Parameter
Conditions
VCC(B)
Unit
1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5.0 V ± 0.5 V
Typ
Max
Typ
Max
Typ
Max
Typ
Max
tPHL
HIGH to LOW
B to A
propagation delay
3
5
2
5
2
4
2
4
ns
tPLH
LOW to HIGH
B to A
propagation delay
4
8
2.5
7
1.5
3
1
3
ns
tPZL
OFF-state to LOW OE to A
propagation delay
OE to B
6
12
4.5
9
6
9
4
7
ns
10
14
5
10
6
9
4
8
ns
100
120
100
120
100
120
100
120
ns
100
120
100
120
100
120
100
120
ns
—
1
—
1
—
1
—
1
ns
—
18
—
32
—
40
—
40
Mbit/
s
LOW to OFF-state OE to A
propagation delay
OE to B
tPLZ
tsk(o)
output skew time
fdata
data rate
between channels
[2]
VCC(A) = 5.0 V ± 0.5 V
tPHL
HIGH to LOW
A to B
propagation delay
5
7
2
5
2
4
2
4
ns
tPLH
LOW to HIGH
A to B
propagation delay
1
2
1
3
1
3
1
3
ns
tPHL
HIGH to LOW
B to A
propagation delay
5
7
2
5
2
4
2
4
ns
tPLH
LOW to HIGH
B to A
propagation delay
4
7
2.5
5
2
4
1
3
ns
tPZL
OFF-state to LOW OE to A
propagation delay
OE to B
6
14
4
8
4
8
3
5
ns
10
15
5
8
4
7
4
5
ns
100
120
100
120
100
120
100
120
ns
100
120
100
120
100
120
100
120
ns
—
1
—
1
—
1
—
1
ns
—
18
—
32
—
40
—
52
Mbit/
s
LOW to OFF-state OE to A
propagation delay
OE to B
tPLZ
tsk(o)
output skew time
fdata
data rate
[1]
[2]
between channels
[2]
All typical values are measured at nominal VCC and Tamb = 25 °C.
Skew between any two outputs of the same package switching in the same direction.
NTSX2102
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NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
12 Waveforms
VI
An, Bn
input
VM
GND
tPHL
tPLH
VOH
Bn, An
output
70 % of VCCO
VM
30 % of VCCO
VOL
tTHL
tTLH
aaa-005256
Measurement points are given in Table 11.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 5. The data input (An, Bn) to data output (Bn, An) propagation delay times
VI
OE input
VM
GND
tPLZ
output
LOW-to-OFF
OFF-to-LOW
tPZL
VCCO
VX
VY
VOL
outputs
enabled
outputs
disabled
outputs
enabled
aaa-005257
Measurement points are given in Table 11.
VOL and VOH are typical output voltage levels that occur with the output load.
Figure 6. Enable and disable times
[1][2]
Table 11. Measurement points
Supply voltage
Input
Output
VCCO
VM
VM
VX
VY
1.65 V to 5.5 V
0.5VCCI
0.5VCCO
0.5VCCO
0.1VCCO
[1]
[2]
VCCI is the supply voltage associated with the input.
VCCO is the supply voltage associated with the output.
NTSX2102
Product data sheet
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Rev. 2.3 — 6 October 2022
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9 / 32
NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
tW
VI
90 %
negative
pulse
VM
VM
10 %
0V
VI
tf
tr
tr
tf
90 %
positive
pulse
VM
VM
10 %
0V
tW
VCC
VI
G
DUT
VCCO
RL
VO
CL
aaa-005258
Test data is given in Table 12.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; ZO = 50 Ω; dV/dt ≥ 1.0
V/ns.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VCC0 = Supply voltage associated with the output.
Figure 7. Test circuit for measuring switching times
Table 12. Test data
Supply voltage
Input
VCC(A)
VCC(B)
[1]
VI
tr/tf
CL
RL
1.65 V to 1.95 V
1.65 V to 1.95 V
VCCI
≤ 2.0 ns
50 pF
2.2 kΩ
2.3 V to 2.7 V
2.3 V to 2.7 V
VCCI
≤ 2.0 ns
50 pF
2.2 kΩ
3.0 V to 3.6 V
3.0 V to 3.6 V
VCCI
≤ 2.5 ns
50 pF
2.2 kΩ
4.5 V to 5.5 V
4.5 V to 5.5 V
VCCI
≤ 2.5 ns
50 pF
2.2 kΩ
[1]
Load
VCCI is the supply voltage associated with the input.
13 Application information
13.1 Applications
The NTSX2102 can be used in point-to-point applications to interface between devices
2
or systems operating at different supply voltages. The device is targeted at I C or 1-wire
buses which use open-drain drivers.
NTSX2102
Product data sheet
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Rev. 2.3 — 6 October 2022
© 2022 NXP B.V. All rights reserved.
10 / 32
NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
1.8 V
3.3 V
0.1 µF
1.8 V
SYSTEM
CONTROLLER
2.2 kΩ
2.2 kΩ
VCC(A)
VCC(B)
2.2 kΩ
3.3 V
SYSTEM
CONTROLLER
2.2 kΩ
OE
0.1 µF
1 µF
NTSX2102
DATA
A1
B1
A2
B2
DATA
aaa-005259
Figure 8. Typical voltage level-translation circuit
13.2 Architecture
The architecture of the NTSX2102 is shown in Figure 9. The device does not require
an extra input signal to control the direction of data flow from A to B or B to A. The
NTSX2102 is a "switch" type voltage translator, it employs two key circuits to enable
voltage translation:
1. Two pass-gate transistors (N-channel) that tie the ports together.
2. An output edge-rate accelerator that detects and accelerates rising and falling edges
on the I/O pins (see Figure 10).
VCC(A)
VCC(B)
T1
ONE
SHOT
ONE
SHOT
T3
T2
ONE
SHOT
ONE
SHOT
T4
VCC(A)
A
T5
VCC(B)
T6
B
aaa-005260
Figure 9. Architecture of NTSX2102 I/O cell (one channel)
During an input transition, a one-shot accelerates the output transition by switching on
the PMOS transistors (T1, T3) for a LOW-to-HIGH transition. Alternatively, it switches on
the NMOS transistors (T2, T4) for a HIGH-to-LOW transition. Once activated, the oneshot is de-activated after approximately 25 ns (see Figure 11). During the acceleration
time, the driver output resistance is between approximately 10 Ω and 35 Ω. To avoid
signal contention, the application must not exceed the maximum data rate or wait for the
one-shot circuit to turn-off, before applying a signal in the opposite direction.
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aaa-005261
4
VI(An)
(V) 3
2
1
0
4
VO(Bn)
(V) 3
2
1
0
0
20
40
60
80
T (ns)
100
VCC(A) = 3.3 V; VCC(B) = 3.3 V.
Figure 10. Input and output waveforms showing edge-rate acceleration
aaa-005262
80
One-shot
time
(ns)
60
40
20
0
1
2
3
4
5
VCCO (V)
6
Figure 11. One-shot pulse time versus VCCO
13.3 Input driver requirements
As the NTSX2102 is a switch type translator, properties of the input driver directly affect
the output signal. The external open-drain driver applied to an I/O, determines the static
current sinking capability of the system. The maximum data rate, output transition times
(tTHL, tTLH) and propagation delays (tPHL, tPLH) are dependent upon the output impedance
and edge-rate of the external driver.
13.4 Output load considerations
The maximum lumped capacitive load that can be driven is dependent upon the one-shot
pulse duration and has been tuned to 600 pF. In cases with higher capacitive loading,
there is a risk that the output does not reach the positive rail within the one-shot pulse
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duration. To avoid excessive capacitive loading and to ensure correct triggering of the
one-shot, use short trace lengths and low capacitance connectors on NTSX2102 PCB
layouts. The length of the PCB trace should be such that the round-trip delay of any
reflection is within the one-shot pulse duration. Such a length ensures low impedance
termination and avoids output signal oscillations and one-shot retriggering.
13.5 Output enable (OE)
An output enable input (OE) is used to disable the device. Setting OE = LOW causes all
I/Os to assume the high-impedance OFF-state.
13.6 Power-up
When either of the supplies VCC(n) is at 0 V, outputs are in the high-impedance OFFstate. One of the advantages of NTSX translators is that either VCC(A) or VCC(B) may
be powered up first. To reduce dissipation during power-up, ensure that output enable
(OE) is defined. Connect it via a pulldown resistor to GND or, if the application allows,
hardwired to VCC(A). If the OE pin is hardwired to VCC(A), either supply can be powered up
or down first. If a pulldown is used, the following sequences are recommended.
For power-up:
1. Apply power to either supply pin
2. Apply power to other supply pin
3. Enable the device by driving OE HIGH
For power down:
1. Disable the device by driving OE LOW
2. Remove power from either supply pin
3. Remove power from other supply pin
13.7 Pull-up resistors on I/O lines
Each A port I/O requires a pull-up resistor to VCC(A), and each B port I/O requires a pullup resistor to VCC(B). Choose the magnitude of the pull-up resistors to ensure that the
output voltage levels meet the application requirement.
13.8 GD package vs TL package
Due to differences in package construction the TL package has a center pad vs no center
pad for the GD package. The following section provides guidance in replacement vs new
applications.
• No trace under GD package
1. Replacement of GD package: The pad is not electrically connected to the silicon
(no wire bond and epoxy is not conductive) and can be left floating. It is not
required to be connected to the PCB. Simply place the TL package on the same
PCB traces as the existing GD package.
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2. New use of the TL package: Place PCB trace for soldering of the center pad based
on PCB layout recommendations for better mechanical connection and thermal
conductivity. The PCB center pad can be connect to GND or left floating.
• Trace under the GD package
1. Replacement of GD package: It is not best practice to have center pad over the
trace but since the TL package center pad is not connected to the silicon the risk is
low. If there are multiple traces there could be EMI and cross talk. In both cases the
customer needs to evaluate risk.
2. New use of the TL package: Do not route traces under the package
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14 Package outline
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.4 x 1.2 x 0.5 mm
B
D
SOT1309-1
A
E
A
A1
A3
terminal 1
index area
detail X
e1
v
w
b
terminal 1
index area
C A B
C
C
y
y1 C
e
2
4
L
1
5 b
8
L1
6
X
0
3 mm
scale
Dimensions
Unit
mm
A
A1
A3
b
D
E
max 0.50 0.025
0.25 1.45 1.25
nom
0.127 0.20 1.40 1.20
0.00
0.15 1.35 1.15
min
e
e1
0.4
0.8
L
L1
v
w
y
y1
0.35 0.45
0.30 0.40 0.10 0.05 0.05 0.05
0.25 0.35
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included
Outline
version
SOT1309-1
References
IEC
JEDEC
JEITA
sot1309-1_po
European
projection
Issue date
11-08-18
11-08-23
MO-255
Figure 12. Package outline SOT1309-1 (XQFN8)
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XSON8: plastic extremely thin small outline package; no leads;
8 terminals; body 3 x 2 x 0.5 mm
D
SOT996-2
B
A
E
A
A1
detail X
terminal 1
index area
e1
1
4
8
5
C
C A B
C
v
w
b
e
L1
y1 C
y
L2
L
X
0
1
2 mm
scale
Dimensions (mm are the original dimensions)
Unit(1)
mm
max
nom
min
A
0.5
A1
b
D
E
0.05 0.35
2.1
3.1
0.00 0.15
1.9
2.9
e
e1
0.5
1.5
L
L1
L2
0.5
0.15
0.6
0.3
0.05
0.4
v
0.1
w
y
0.05 0.05
y1
0.1
sot996-2_po
Outline
version
References
IEC
JEDEC
JEITA
European
projection
Issue date
07-12-21
12-11-20
SOT996-2
Figure 13. Package outline SOT996-2 (XSON8)
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Figure 14. Package outline SOT1052-2 (XSON8)
NTSX2102
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Figure 15. Package outline SOT1052-2 (XSON8)
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15 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
15.4 Reflow soldering
Key characteristics in reflow soldering are:
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• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 16) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and Table 14
Table 13. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 14. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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16 Soldering: PCB footprints
Footprint information for reflow soldering of SOT1309 package
SOT1309-1
1.5
0.35
0.15
1.25
0.25
0.2
0.45
0.25
0.15
1.05
1.7 1.55 1.15
0.4
0.35
0.5
0.35
1.35
occupied area
solder resist
solder lands
solder paste
Dimensions in mm
Issue date
13-07-18
13-07-31
sot1309-1_fr
Figure 17. PCB footprint for SOT1309-1 (XQFN8); reflow soldering
NTSX2102
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2.400 pa + oa
2.000
0.500
0.500
0.250
0.025
0.025
4.250
3.400
pa + oa
2.000
4.000
0.900
solder lands
placement area
solder paste
occupied area
Dimensions in mm
sot996-2_fr
Figure 18. PCB footprint for SOT996-2 (XSON8U); reflow soldering
NTSX2102
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Figure 19. PCB footprint for SOT1052-2 (XSON8); recommended solder mask opening pattern
NTSX2102
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Figure 20. PCB footprint for SOT1052-2 (XSON8); recommended I/O pads and solderable area
NTSX2102
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Figure 21. PCB footprint for SOT1052-2 (XSON8); recommended solder paste stencil
NTSX2102
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Figure 22. PCB footprint for SOT1052-2 (XSON8); notes
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17 Abbreviations
Table 15. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
GPIO
General Purpose Input Output
HBM
Human Body Model
2
I C
Inter-Integrated Circuit
PCB
Printed-circuit board
PMOS
Positive Metal Oxide Semiconductor
SMBus
System Management Bus
UART
Universal Asynchronous Receiver Transmitter
UTLP
Ultra Thin Leadless Package
18 Revision history
Table 16. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NTSX2102 v.2.3
20221006
Product data sheet
202210008I
NTSX2102 v.2.2
Modifications:
• Table 2: NTSX2102TL Minimum Order Quantity corrected to 4Ku per reel
NTSX2102 v.2.2
20220321
Product data sheet
—
NTSX2102 v.2.1
NTSX2102 v.2.1
20211112
Product data sheet
—
NTSX2102 v.2
NTSX2102 v.2
20130211
Product data sheet
—
NTSX2102 v.1.1
NTSX2102 v.1.1
20121121
Product data sheet
—
NTSX2102 v.1
NTSX2102 v.1
20121119
Product data sheet
—
—
NTSX2102
Product data sheet
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19 Legal information
19.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
19.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NTSX2102
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use in non-automotive qualified products — Unless
this data sheet expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts no liability for
inclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document, including
the legal information in that document, is for reference only. The English
version shall prevail in case of any discrepancy between the translated and
English versions.
NTSX2102
Product data sheet
Security — Customer understands that all NXP products may be subject to
unidentified vulnerabilities or may support established security standards or
specifications with known limitations. Customer is responsible for the design
and operation of its applications and products throughout their lifecycles
to reduce the effect of these vulnerabilities on customer’s applications
and products. Customer’s responsibility also extends to other open and/or
proprietary technologies supported by NXP products for use in customer’s
applications. NXP accepts no liability for any vulnerability. Customer should
regularly check security updates from NXP and follow up appropriately.
Customer shall select products with security features that best meet rules,
regulations, and standards of the intended application and make the
ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may be
provided by NXP.
NXP has a Product Security Incident Response Team (PSIRT) (reachable
at PSIRT@nxp.com) that manages the investigation, reporting, and solution
release to security vulnerabilities of NXP products.
19.4 Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 2.3 — 6 October 2022
© 2022 NXP B.V. All rights reserved.
30 / 32
NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Ordering information ..........................................2
Ordering options ................................................2
Pin description ...................................................3
Function table ....................................................4
Limiting values .................................................. 4
Recommended operating conditions ................. 4
Typical static characteristics ..............................5
Static characteristics ......................................... 5
Typical dynamic characteristics for
temperature 25 °C .............................................6
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Dynamic characteristics for temperature
range -40 °C to +85 °C .....................................7
Measurement points ..........................................9
Test data ..........................................................10
SnPb eutectic process (from J-STD-020D) ..... 20
Lead-free process (from J-STD-020D) ............ 20
Abbreviations ...................................................28
Revision history ...............................................28
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Logic symbol ..................................................... 2
Pin configuration SOT1309-1 (XQFN8) .............3
Pin configuration SOT996-2 (XSON8) ...............3
Pin configuration SOT1052-2 (XSON8) .............3
The data input (An, Bn) to data output (Bn,
An) propagation delay times ............................. 9
Enable and disable times ..................................9
Test circuit for measuring switching times ....... 10
Typical voltage level-translation circuit ............ 11
Architecture of NTSX2102 I/O cell (one
channel) ...........................................................11
Input and output waveforms showing edgerate acceleration ..............................................12
One-shot pulse time versus VCCO ................. 12
Package outline SOT1309-1 (XQFN8) ............ 15
Package outline SOT996-2 (XSON8) ..............16
Package outline SOT1052-2 (XSON8) ............17
NTSX2102
Product data sheet
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Package outline SOT1052-2 (XSON8) ............18
Temperature profiles for large and small
components ..................................................... 21
PCB footprint for SOT1309-1 (XQFN8);
reflow soldering ............................................... 22
PCB footprint for SOT996-2 (XSON8U);
reflow soldering ............................................... 23
PCB footprint for SOT1052-2 (XSON8);
recommended solder mask opening pattern ... 24
PCB footprint for SOT1052-2 (XSON8);
recommended I/O pads and solderable
area ................................................................. 25
PCB footprint for SOT1052-2 (XSON8);
recommended solder paste stencil ..................26
PCB footprint for SOT1052-2 (XSON8);
notes ................................................................27
All information provided in this document is subject to legal disclaimers.
Rev. 2.3 — 6 October 2022
© 2022 NXP B.V. All rights reserved.
31 / 32
NTSX2102
NXP Semiconductors
Dual supply translating transceiver; open-drain; auto direction sensing
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
8
9
10
11
12
13
13.1
13.2
13.3
13.4
13.5
13.6
13.7
13.8
14
15
15.1
15.2
15.3
15.4
16
17
18
19
General description ............................................ 1
Features and benefits .........................................1
Applications .........................................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Functional diagram ............................................. 2
Pinning information ............................................ 3
Pinning ............................................................... 3
Pin description ................................................... 3
Functional description ........................................4
Limiting values .................................................... 4
Recommended operating conditions ................ 4
Static characteristics .......................................... 5
Dynamic characteristics .....................................6
Waveforms ........................................................... 9
Application information .................................... 10
Applications ......................................................10
Architecture ......................................................11
Input driver requirements .................................12
Output load considerations .............................. 12
Output enable (OE) ......................................... 13
Power-up ..........................................................13
Pull-up resistors on I/O lines ........................... 13
GD package vs TL package ............................ 13
Package outline .................................................15
Soldering of SMD packages .............................19
Introduction to soldering .................................. 19
Wave and reflow soldering .............................. 19
Wave soldering ................................................ 19
Reflow soldering .............................................. 19
Soldering: PCB footprints ................................ 22
Abbreviations .................................................... 28
Revision history ................................................ 28
Legal information .............................................. 29
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© 2022 NXP B.V.
All rights reserved.
For more information, please visit: http://www.nxp.com
Date of release: 6 October 2022
Document identifier: NTSX2102
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