NVT2003/06
Bidirectional voltage-level translator for open-drain and pushpull applications
Rev. 5.1 — 8 October 2021
1
Product data sheet
General description
The NVT2003/06 is a family of bidirectional voltage level translators operational from
1.0 V to 3.6 V (Vref(A)) and 1.8 V to 5.5 V (Vref(B)), which allow bidirectional voltage
translations between 1.0 V and 5 V without the need for a direction pin in open-drain
or push-pull applications. Bit widths ranging from 3-bit to 6-bit are offered for level
translation application with transmission speeds < 33 MHz for an open-drain system with
a 50 pF capacitance and a pull-up of 197 Ω.
When the An or Bn port is LOW, the clamp is in the ON-state and a low resistance
connection exists between the An and Bn ports. The low ON-state resistance (Ron) of
the switch allows connections to be made with minimal propagation delay. Assuming the
higher voltage is on the Bn port when the Bn port is HIGH, the voltage on the An port is
limited to the voltage set by VREFA. When the An port is HIGH, the Bn port is pulled to
the drain pull-up supply voltage (Vpu(D)) by the pull-up resistors. This functionality allows
a seamless translation between higher and lower voltages selected by the user without
the need for directional control.
When EN is HIGH, the translator switch is on, and the An I/O are connected to the Bn
I/O, respectively, allowing bidirectional data flow between ports. When EN is LOW, the
translator switch is off, and a high-impedance state exists between ports. The EN input
circuit is designed to be supplied by Vref(B). To ensure the high-impedance state during
power-up or power-down, EN must be LOW.
All channels have the same electrical characteristics and there is minimal deviation from
one output to another in voltage or propagation delay. This is a benefit over discrete
transistor voltage translation solutions, since the fabrication of the switch is symmetrical.
The translator provides excellent ESD protection to lower voltage devices, and at the
same time protects less ESD-resistant devices.
2
Features and benefits
• Provides bidirectional voltage translation with no direction pin
• Less than 1.5 ns maximum propagation delay
• Allows voltage level translation between:
– 1.0 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
– 1.2 V Vref(A) and 1.8 V, 2.5 V, 3.3 V or 5 V Vref(B)
– 1.8 V Vref(A) and 3.3 V or 5 V Vref(B)
– 2.5 V Vref(A) and 5 V Vref(B)
– 3.3 V Vref(A) and 5 V Vref(B)
• Low 3.5 Ω ON-state connection between input and output ports provides less signal
distortion
• 5 V tolerant I/O ports to support mixed-mode signal operation
• High-impedance An and Bn pins for EN = LOW
NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
• Lock-up free operation
• Flow through pinout for ease of printed-circuit board trace routing
• ESD protection exceeds 3.5 kV HBM per JESD22-A114 and 1000 V CDM per JESD22C101
• Packages offered: TSSOP10, DHVQFN16, HVQFN16, TSSOP16
3
Ordering information
Table 1. Ordering information
Type number
Topside
marking
Number Package
of bits
Name
NVT2003DP
N2003
3
TSSOP10
NVT2006BQ
N2006
6
DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads;16 terminals; body
2.5 × 3.5 × 0.85 mm
SOT763-1
NVT2006BS
N06
6
HVQFN16
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3 × 3 × 0.85 mm
SOT758-1
NVT2006PW
NVT2006
6
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
Description
Version
plastic thin shrink small outline package; 10 leads;
body width 3 mm
SOT552-1
3.1 Ordering options
Table 2. Ordering options
Type number
Orderable part
number
Package
Packing method
NVT2003DP
NVT2003DP,118
TSSOP10
NVT2006BQ
NVT2006BQ,115
NVT2006BS
NVT2006PW
[1]
[1]
Minimum
order quantity
Temperature
Reel 13" Q1/T1
*Standard mark SMD
2500
Tamb = -40 °C to +85 °C
DHVQFN16
Reel 7" Q1/T1
*Standard mark SMD
3000
Tamb = -40 °C to +85 °C
NVT2006BS,118
HVQFN16
Reel 13" Q1/T1
*Standard mark SMD
6000
Tamb = -40 °C to +85 °C
NVT2006PW,118
TSSOP16
Reel 13" Q1/T1
*Standard mark SMD
2500
Tamb = -40 °C to +85 °C
Standard packing quantities and other packaging data are available at www.nxp.com/packages/.
NVT2003_06
Product data sheet
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
4
Functional diagram
VREFA
VREFB
NVT20xx
EN
A1
SW
B1
An
SW
Bn
GND
002aae132
Figure 1. Logic diagram of NVT2003/06 (positive logic)
5
Pinning information
5.1 Pinning
5.1.1 3-bit in TSSOP10 package
GND
1
10 EN
VREFA
2
9
VREFB
A1
3
8
B1
A2
4
7
B2
A3
5
6
B3
NVT2003DP
002aae836
Figure 2. Pin configuration for TSSOP10
1
terminal 1
index area
VREFA
2
15 VREFB
A1
3
14 B1
14 B1
A2
4
13 B2
A3
5
12 B3
A4
6
11 B4
6
11 B4
A5
7
10 B5
A5
7
10 B5
A6
8
2
15 VREFB
A1
3
A2
4
A3
5
A4
NVT2006PW
9
B6
Figure 3. Pin configuration for TSSOP16
Product data sheet
13 B2
12 B3
Transparent top view
002aae221
Figure 4. Pin configuration for DHVQFN16
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Rev. 5.1 — 8 October 2021
NVT2006BQ
9
VREFA
B6
16 EN
8
1
A6
GND
002aae220
NVT2003_06
16 EN
GND
5.1.2 6-bit in TSSOP16, DHVQFN16 and HVQFN16 packages
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NVT2003/06
NXP Semiconductors
4
14 EN
13 VREFB
11 B2
10 B3
9
8
A4
B5
3
7
A3
NVT2006BS
B6
2
6
A2
12 B1
A6
1
5
A1
A5
terminal 1
index area
15 GND
16 VREFA
Bidirectional voltage-level translator for open-drain and push-pull applications
Transparent top view
B4
002aae222
Figure 5. Pin configuration for HVQFN16
5.2 Pin description
Table 3. Pin description
Symbol
Pin
NVT2003DP
Description
[1]
NVT2006BQ,
[2]
NVT2006PW
NVT2006BS
[2]
GND
1
1
15
ground (0 V)
VREFA
2
2
16
low-voltage side reference supply voltage for
An
A1
3
3
1
A2
4
4
2
low-voltage side; connect to VREFA through a
pull-up resistor
A3
5
5
3
A4
-
6
4
A5
-
7
5
A6
-
8
6
B1
8
14
12
B2
7
13
11
B3
6
12
10
B4
-
11
9
B5
-
10
8
B6
-
9
7
VREFB
9
15
13
high-voltage side reference supply voltage for
Bn
EN
10
16
14
switch enable input; connect to VREFB and
pull-up through a high resistor
[1]
[2]
high-voltage side; connect to VREFB through
a pull-up resistor
3-bit NVT2003 available in TSSOP10 package.
6-bit NVT2006 available in TSSOP16, DHVQFN16, HVQFN16 packages.
NVT2003_06
Product data sheet
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
6
Functional description
Refer to Figure 1.
6.1 Function table
Table 4. Function selection (example)
H = HIGH level; L = LOW level.
[1]
Input EN
Function
H
An = Bn
L
disconnect
[1]
7
EN is controlled by the Vref(B) logic levels and should be at least 1 V higher than Vref(A) for best translator operation.
Application design-in information
The NVT2003/06 can be used in level translation applications for interfacing devices or
systems operating at different interface voltages with one another. The NVT2003/06 is
ideal for use in applications where an open-drain driver is connected to the data I/Os.
The NVT2003/06 can also be used in applications where a push-pull driver is connected
to the data I/Os.
7.1 Enable and disable
The NVT20xx has an EN input that is used to disable the device by setting EN LOW,
which places all I/Os in the high-impedance state.
Vpu(D) = 3.3 V(1)
NVT20xx
Vref(A) = 1.8 V(1)
VREFA
RPU
VCC
SCL
I2C-BUS
CONTROLLER
SDA
2
8 EN
7
VREFB
RPU
A1
A2
3
4
SW
SW
GND
6
5
B1
B2
1
GND
RPU
RPU
VCC
SCL
I2C-BUS
DEVICE
SDA
GND
002aae134
1. The applied voltages at Vref(A) and Vpu(D) should be such that Vref(B) is at least 1 V higher than
Vref(A) for best translator operation.
Figure 6. Typical application circuit (switch always enabled)
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Product data sheet
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NVT2003/06
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Bidirectional voltage-level translator for open-drain and push-pull applications
Table 5. Application operating conditions
Refer to Figure 6.
Symbol
Parameter
Vref(B)
Min
Typ
reference voltage (B)
Vref(A) + 0.6
VI(EN)
input voltage on pin EN
Vref(A)
[1]
Max
Unit
2.1
5
V
Vref(A) + 0.6
2.1
5
V
reference voltage (A)
0
1.5
4.4
V
Isw(pass)
pass switch current
-
14
-
mA
Iref
reference current
transistor
-
5
-
μA
Tamb
ambient temperature
operating in
free-air
-40
-
+85
°C
[1]
Conditions
All typical values are at Tamb = 25 °C.
Vpu(D) = 3.3 V
3.3 V enable signal(1)
on
off
NVT20xx
Vref(A) = 1.8 V(1)
VREFA
RPU
VCC
SCL
I2C-BUS
CONTROLLER
SDA
2
(2)
8 EN
7
VREFB
RPU
RPU
RPU
A1
A2
3
4
SW
SW
GND
6
5
B1
B2
1
GND
VCC
SCL
I2C-BUS
DEVICE
SDA
GND
002aae135
1. In the Enabled mode, the applied enable voltage VI(EN) and the applied voltage at Vref(A)
should be such that Vref(B) is at least 1 V higher than Vref(A) for best translator operation.
2. Note that the enable time and the disable time are essentially controlled by the RC time
constant of the capacitor and the 200 kΩ resistor on the EN pin.
Figure 7. Typical application circuit (switch enable control)
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
1.8 V
1.5 V
1.2 V
1.0 V
5V
totem pole or
open-drain I/O
NVT20xx
EN
VREFA
VCORE
VREFB
A1
CPU I/O
A2
SW
SW
B1
B2
VCC
CHIPSET I/O
3.3 V
A3
A4
A5
A6
An
SW
SW
SW
SW
SW
B3
B4
VCC
CHIPSET I/O
B5
B6
Bn
GND
002aae133
Figure 8. Bidirectional translation to multiple higher voltage levels
7.2 Bidirectional translation
For the bidirectional clamping configuration (higher voltage to lower voltage or lower
voltage to higher voltage), the EN input must be connected to VREFB and both pins
pulled to HIGH side Vpu(D) through a pull-up resistor (typically 200 kΩ). This allows
VREFB to regulate the EN input. A filter capacitor on VREFB is recommended. The
controller output driver can be totem pole or open-drain (pull-up resistors may be
required) and the target device output can be totem pole or open-drain (pull-up resistors
are required to pull the Bn outputs to Vpu(D)). However, if either output is totem-pole, data
must be unidirectional or the outputs must be 3-stateable and be controlled by some
direction-control mechanism to prevent HIGH-to-LOW contentions in either direction. If
both outputs are open-drain, no direction control is needed.
The reference supply voltage (Vref(A)) is connected to the processor core power supply
voltage. When VREFB is connected through a 200 kΩ resistor to a 3.3 V to 5.5 V Vpu(D)
power supply, and Vref(A) is set between 1.0 V and (Vpu(D) - 1 V), the output of each
An has a maximum output voltage equal to VREFA, and the output of each Bn has a
maximum output voltage equal to Vpu(D).
7.3 Bidirectional level shifting between two different power domains
nominally at the same potential
The less obvious application for the NVT2003 is for level shifting between two different
power domains that are nominally at the same potential, such as a 3.3 V system where
the line crosses power supply domains that under normal operation would be at 3.3 V,
but one could be at 3.0 V and the other at 3.6 V, or one could be experiencing a power
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NVT2003/06
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Bidirectional voltage-level translator for open-drain and push-pull applications
failure while the other domain is trying to operate. One of the NVT2003 three channel
transistors is used as a second reference transistor with its B side connected to a voltage
supply that is at least 1 V (and preferably 1.5 V) above the maximum possible for either
Vpu(A) or Vpu(B). Then if either pull-up voltage is at 0 V, the channels are disabled, and
otherwise the channels are biased such that they turn OFF at the lower pull-up voltage,
and if the two pull-up voltages are equal, the channel is biased such that it just turns OFF
at the common pull-up voltage.
Vpu(B) = 3.3 V
Vpu(H)
NVT20xx
Vpu(A) = 3.3 V
VREFA
RPU
VCC
SCL
I2C-BUS
CONTROLLER
SDA
GND
RPU
2
10 EN
9
VREFB
RPU
RPU
Vpu(B)
A1
3
A2
4
A3
5
SW
SW
SW
8
B1
7
B2
6
B3
1
GND
VCC
SCL
I2C-BUS
DEVICE
SDA
GND
002aae967
The applied enable voltage Vpu(H) and the applied voltage at Vref(A) and Vref(B) should be such that Vref(H) is at least 1 V
higher than Vref(A) and Vref(B) for best translator operation.
Figure 9. Bidirectional level shifting between two different power domains
7.4 How to size pull-up resistor value
Sizing the pull-up resistor on an open-drain bus is specific to the individual application
and is dependent on the following driver characteristics:
•
•
•
•
The driver sink current
The VOL of driver
The VIL of the driver
Frequency of operation
The following tables can be used to estimate the pull-up resistor value in different use
cases so that the minimum resistance for the pull-up resistor can be found.
Table 6, Table 7 and Table 8 contain suggested minimum values of pull-up resistors
for the PCA9306 and NVT20xx devices with typical voltage translation levels and drive
currents. The calculated values assume that both drive currents are the same. VOL =
VIL = 0.1 × VCC and accounts for a ±5 % VCC tolerance of the supplies, ±1 % resistor
values. It should be noted that the resistor chosen in the final application should be equal
to or larger than the values shown in Table 6, Table 7 and Table 8 to ensure that the pass
voltage is less than 10 % of the VCC voltage, and the external driver should be able to
sink the total current from both pull-up resistors. When selecting the minimum resistor
value in Table 6, Table 7 or Table 8, the drive current strength that should be chosen
should be the lowest drive current seen in the application and account for any drive
strength current scaling with output voltage. For the GTL devices, the resistance table
NVT2003_06
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Bidirectional voltage-level translator for open-drain and push-pull applications
should be recalculated to account for the difference in ON resistance and bias voltage
limitations between VCC(B) and VCC(A).
Table 6. Pull-up resistor minimum values, 3 mA driver sink current for PCA9306 and NVT20xx
A-side
1.0 V
B-side
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
Rpu(A) = 750 Ω
Rpu(B) = 750 Ω
Rpu(A) = 845 Ω
Rpu(B) = 845 Ω
Rpu(A) = 976 Ω
Rpu(B) = 976 Ω
Rpu(A) = none
Rpu(B) = 887 Ω
Rpu(A) = none
Rpu(B) = 1.18 kΩ
Rpu(A) = none
Rpu(B) = 1.82 kΩ
Rpu(A) = 931 Ω
Rpu(B) = 931 Ω
Rpu(A) = 1.02 kΩ
Rpu(B) = 1.02 kΩ
Rpu(A) = none
Rpu(B) = 887 Ω
Rpu(A) = none
Rpu(B) = 1.18 kΩ
Rpu(A) = none
Rpu(B) = 1.82 kΩ
Rpu(A) = 1.1 kΩ
Rpu(B) = 1.1 kΩ
Rpu(A) = none
Rpu(B) = 866 Ω
Rpu(A) = none
Rpu(B) = 1.18 kΩ
Rpu(A) = none
Rpu(B) = 1.78 kΩ
Rpu(A) = 1.47 kΩ
Rpu(B) = 1.47 kΩ
Rpu(A) = none
Rpu(B) = 1.15 kΩ
Rpu(A) = none
Rpu(B) = 1.78 kΩ
Rpu(A) = 1.96 kΩ
Rpu(B) = 1.96 kΩ
Rpu(A) = none
Rpu(B) = 1.78 kΩ
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Rpu(A) = none
Rpu(B) = 1.74 kΩ
Table 7. Pull-up resistor minimum values, 10 mA driver sink current for PCA9306 and NVT20xx
A-side
1.0 V
B-side
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
Rpu(A) = 221 Ω
Rpu(B) = 221 Ω
Rpu(A) = 255 Ω
Rpu(B) = 255 Ω
Rpu(A) = 287 Ω
Rpu(B) = 287 Ω
Rpu(A) = none
Rpu(B) = 267 Ω
Rpu(A) = none
Rpu(B) = 357 Ω
Rpu(A) = none
Rpu(B) = 549 Ω
Rpu(A) = 274 Ω
Rpu(B) = 274 Ω
Rpu(A) = 309 Ω
Rpu(B) = 309 Ω
Rpu(A) = none
Rpu(B) = 267 Ω
Rpu(A) = none
Rpu(B) = 357 Ω
Rpu(A) = none
Rpu(B) = 549 Ω
Rpu(A) = 332 Ω
Rpu(B) = 332 Ω
Rpu(A) = none
Rpu(B) = 261 Ω
Rpu(A) = none
Rpu(B) = 348 Ω
Rpu(A) = none
Rpu(B) = 536 Ω
Rpu(A) = 442 Ω
Rpu(B) = 442 Ω
Rpu(A) = none
Rpu(B) = 348 Ω
Rpu(A) = none
Rpu(B) = 536 Ω
Rpu(A) = 590 Ω
Rpu(B) = 590 Ω
Rpu(A) = none
Rpu(B) = 523 Ω
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
Rpu(A) = none
Rpu(B) = 523 Ω
Table 8. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx
A-side
1.0 V
B-side
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
Rpu(A) = 147 Ω
Rpu(B) = 147 Ω
Rpu(A) = 169 Ω
Rpu(B) = 169 Ω
Rpu(A) = 191 Ω
Rpu(B) = 191 Ω
Rpu(A) = none
Rpu(B) = 178 Ω
Rpu(A) = none
Rpu(B) = 237 Ω
Rpu(A) = none
Rpu(B) = 365 Ω
Rpu(A) = 182 Ω
Rpu(B) = 182 Ω
Rpu(A) = 205 Ω
Rpu(B) = 205 Ω
Rpu(A) = none
Rpu(B) = 178 Ω
Rpu(A) = none
Rpu(B) = 237 Ω
Rpu(A) = none
Rpu(B) = 365 Ω
1.2 V
NVT2003_06
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NVT2003/06
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Bidirectional voltage-level translator for open-drain and push-pull applications
Table 8. Pull-up resistor minimum values, 15 mA driver sink current for PCA9306 and NVT20xx...continued
A-side
B-side
1.2 V
1.5 V
1.5 V
1.8 V
2.5 V
3.3 V
5.0 V
Rpu(A) = 221 Ω
Rpu(B) = 221 Ω
Rpu(A) = none
Rpu(B) = 174 Ω
Rpu(A) = none
Rpu(B) = 232 Ω
Rpu(A) = none
Rpu(B) = 357 Ω
Rpu(A) = 294 Ω
Rpu(B) = 294 Ω
Rpu(A) = none
Rpu(B) = 232 Ω
Rpu(A) = none
Rpu(B) = 357 Ω
Rpu(A) = 392 Ω
Rpu(B) = 392 Ω
Rpu(A) = none
Rpu(B) = 357 Ω
1.8 V
2.5 V
3.3 V
Rpu(A) = none
Rpu(B) = 348 Ω
7.5 How to design for maximum frequency operation
The maximum frequency is limited by the minimum pulse width LOW and HIGH as well
as rise time and fall time. See Equation 1 as an example of the maximum frequency. The
rise and fall times are shown in Figure 10.
(1)
tr(actual)
VIH
VIL
VCC
tf(actual)
tHIGH(min)
0.9 × VCC
tLOW(min)
VOL
GND
1 / fmax
0.1 × VCC
002aag912
Figure 10. An example waveform for maximum frequency
The rise and fall times are dependent upon translation voltages, the drive strength,
the total node capacitance (CL(tot)) and the pull-up resistors (RPU) that are present on
the bus. The node capacitance is the addition of the PCB trace capacitance and the
device capacitance that exists on the bus. Because of the dependency of the external
components, PCB layout and the different device operating states the calculation of rise
and fall times is complex and has several inflection points along the curve.
The main component of the rise and fall times is the RC time constant of the bus line
when the device is in its two primary operating states: when device is in the ON state and
it is low-impedance, the other is when the device is OFF isolating the A-side from the Bside.
A description of the fall time applied to either An or Bn output going from HIGH to LOW
is as follows. Whichever side is asserted first, the B-side down must discharge to the
VCC(A) voltage. The time is determined by the pull-up resistor, pull-down driver strength
and the capacitance. As the level moves below the VCC(A) voltage, the channel resistance
drops so that both A and B sides equal. The capacitance on both sides is connected
to form the total capacitance and the pull-up resistors on both sides combine to the
parallel equivalent resistance. The Ron of the device is small compared to the pull-up
resistor values, so its effect on the pull-up resistance can be neglected and the fall is
determined by the driver pulling the combined capacitance and pull-up resistor currents.
An estimation of the actual fall time seen by the device is equal to the time it takes for
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
the B-side to fall to the VCC(A) voltage and the time it takes for both sides to fall from the
VCC(A) voltage to the VIL level.
A description of the rise time applied to either An or Bn output going from LOW to HIGH
is as follows. When the signal level is LOW, the Ron is at its minimum, so the A and B
sides are essentially one node. They will rise together with an RC time constant that is
the sum of all the capacitance from both sides and the parallel of the resistance from
both sides. As the signal approaches the VCC(A) voltage, the channel resistance goes up
and the waveforms separate, with the B side finishing its rise with the RC time constant
of the B side. The rise to VCC(A) is essentially the same for both sides.
There are some basic guidelines to follow that will help maximize the performance of the
device:
• Keep trace length to a minimum by placing the NVT device close to the processor.
• The signal round trip time on trace should be shorter than the rise or fall time of signal
to reduce reflections.
• The faster the edge of the signal, the higher the chance for ringing.
• The higher drive strength controlled by the pull-up resistor (up to 15 mA), the higher the
frequency the device can use.
The system designer must design the pull-up resistor value based on external current
drive strength and limit the node capacitance (minimize the wire, stub, connector and
trace length) to get the desired operation frequency result.
8
Limiting values
Table 9. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Over operating free-air temperature range.
Symbol
Parameter
Vref(A)
Vref(B)
VI
Min
Max
Unit
reference voltage (A)
-0.5
+6
V
reference voltage (B)
-0.5
input voltage
+6
V
[1]
+6
V
[1]
-0.5
VI/O
voltage on an input/output pin
-0.5
+6
V
Ich
channel current (DC)
-
128
mA
IIK
input clamping current
-50
-
mA
-50
+50
mA
-65
+150
°C
IOK
output clamping current
Tstg
storage temperature
[1]
[2]
9
Conditions
VI < 0 V
[2]
The input and input/output negative voltage ratings may be exceeded if the input and input/output clamp current ratings
are observed.
Low duty cycle pulses, not DC because of heating.
Recommended operating conditions
Table 10. Operating conditions
Symbol
Parameter
Conditions
VI/O
voltage on an input/output pin
An, Bn
Vref(A)
NVT2003_06
Product data sheet
reference voltage (A)
VREFA
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 8 October 2021
[1]
Min
Max
Unit
0
5.5
V
0
5.4
V
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Table 10. Operating conditions...continued
Symbol
Parameter
Conditions
[1]
Max
Unit
0
5.5
V
Vref(B)
reference voltage (B)
VI(EN)
input voltage on pin EN
0
5.5
V
Isw(pass)
pass switch current
-
64
mA
Tamb
ambient temperature
-40
+85
°C
[1]
VREFB
Min
operating in free-air
Vref(A) ≤ Vref(B) - 1 V for best results in level shifting applications.
10 Static characteristics
Table 11. Static characteristics
Tamb = -40 °C to +85 °C, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
VIK
input clamping voltage
II = -18 mA; VI(EN) = 0 V
-
IIH
HIGH-level input current
VI = 5 V; VI(EN) = 0 V
Ci(EN)
input capacitance on pin EN
Cio(off)
[1]
Max
Unit
-
-1.2
V
-
-
5
μA
VI = 3 V or 0 V
-
12
-
pF
off-state input/output capacitance
An, Bn; VO = 3 V or 0 V;
VI(EN) = 0 V
-
5
7
pF
Cio(on)
on-state input/output capacitance
An, Bn; VO = 3 V or 0 V;
VI(EN) = 3 V
-
11.5
13
Ron
ON-state resistance
An, Bn; VI = 0 V; IO = 64 mA;
VI(EN) = 4.5 V
[3][4][5]
1
2.4
5.0
Ω
VI = 2.4 V; IO = 15 mA; VI(EN)
= 4.5 V
[3][4]
-
4.8
7.5
Ω
[1]
[2]
[3]
[4]
[5]
[2]
pF
All typical values are at Tamb = 25 °C.
Not production tested, maximum value based on characterization data of typical parts.
Measured by the voltage drop between the An and Bn terminals at the indicated current through the switch. ON-state resistance is determined by the
lowest voltage of the two terminals.
See curves in Figure 11 for typical temperature and VI(EN) behavior.
Guaranteed by design.
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
10
Ron(typ)
(Ω)
8
6
002aaf680
002aaf681
8
Ron(typ)
(Ω)
VI(EN) = 1.5 V
2.3 V
3.0 V
4.5 V
6
4
4
2
2
0
- 40
- 20
0
20
40
60
80
100
Tamb (°C)
a. IO = 64 mA; VI = 0 V
0
- 40
002aaf682
60
40
40
20
20
0
20
40
60
80
100
Tamb (°C)
20
40
60
80
100
Tamb (°C)
c. IO = 15 mA; VI = 2.4 V; VI(EN) = 3.0 V
002aaf683
80
Ron(typ)
(Ω)
60
- 20
0
b. IO = 15 mA; VI = 2.4 V; VI(EN) = 4.5 V
80
Ron(typ)
(Ω)
0
- 40
- 20
0
- 40
- 20
0
20
40
60
80
100
Tamb (°C)
d. IO = 15 mA; VI = 1.7 V; VI(EN) = 2.3 V
Figure 11. NVT2006 typical ON-state resistance versus ambient temperature
11 Dynamic characteristics
11.1 Open-drain drivers
Table 12. Dynamic characteristics for open-drain drivers
Tamb = -40 °C to +85 °C; VI(EN) = Vref(B); unless otherwise specified.
Symbol
Parameter
Conditions
tPLH
LOW to HIGH propagation
delay
from (input) Bn to
(output) An
tPHL
HIGH to LOW propagation
delay
from (input) Bn to
(output) An
Min
Typ
Max
Unit
Figure 14
[1]
NVT2003_06
Product data sheet
[1]
Ron × (CL + Cio(on))
ns
Ron × (CL + Cio(on))
ns
See graphs based on Ron typical and Cio(on) + CL = 50 pF.
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
5.5 V
002aaf348
1 V/div
200 kΩ
6.6 V
0.1 µF
1.5 V swing
SIGNAL
GENERATOR
EN
VREFB
500 Ω
DUT
50 pF
VREFA
450 Ω
1.5 V
GND
GND
Bn
An
40 ns/div
002aaf347
Figure 12. AC test setup
Figure 13. Example of typical AC waveform
VIH
VTT
input
VM
VM
VIL
RL
VOH
S1
S2 (open)
from output under test
output
CL
VM
002aab845
a. Load circuit
VM
002aab846
VOL
b. Timing diagram; high-impedance scope probe used
S2 = translating down, and same voltage.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz; Zo = 50 Ω; tr ≤ 2 ns; tf ≤ 2
ns.
The outputs are measured one at a time, with one transition per measurement.
Figure 14. Load circuit for outputs
12 Performance curves
tPLH up-translation is typically dominated by the RC time constant, i.e., CL(tot) × RPU = 50
pF × 197 Ω = 9.85 ns, but the Ron × CL(tot) = 50 pF × 5 Ω = 0.250 ns.
tPHL is typically dominated by the external pull-down driver + Ron, which is typically small
compared to the tPLH in an up-translation case.
Enable/disable times are dominated by the RC time constant on the EN pin since the
transistor turn off is on the order of ns, but the enable RC is on the order of ms.
Fall time is dominated by the external pull-down driver with only a slight Ron addition.
Rise time is dominated by the RPU × CL.
Skew time within the part is virtually non-existent, dominated by the difference in bond
wire lengths, which is typically small compared to the board-level routing differences.
Maximum data rate is dominated by the system capacitance and pull-up resistors.
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
002aaf707
0.6
(1)
tPD
(ns)
(3)
(2)
0.4
0
1.
2.
3.
4.
5.
(1)
tPD
(ns)
(4)
(5)
0.2
002aaf708
3
(2)
2
1
0
20
40
60
VI(EN) = 1.5 V; IO = 64 mA; VI = 0 V.
VI(EN) = 4.5 V; IO = 15 mA; VI = 2.4 V.
VI(EN) = 2.3 V; IO = 64 mA; VI = 0 V.
VI(EN) = 3.0 V; IO = 64 mA; VI = 0 V.
VI(EN) = 4.5 V; IO = 64 mA; VI = 0 V.
80
C (pF)
100
0
0
20
40
60
80
C (pF)
100
1. VI(EN) = 3.0 V; IO = 15 mA; VI = 2.4 V.
2. VI(EN) = 2.3 V; IO = 15 mA; VI = 1.7 V.
Figure 15. NVT2006 typical capacitance versus propagation delay
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
13 Package outline
TSSOP10: plastic thin shrink small outline package; 10 leads; body width 3 mm
D
E
SOT552-1
A
X
c
y
HE
v M A
Z
6
10
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
5
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.15
0.23
0.15
3.1
2.9
3.1
2.9
0.5
5.0
4.8
0.95
0.7
0.4
0.1
0.1
0.1
0.67
0.34
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-07-29
03-02-18
SOT552-1
Figure 16. Package outline SOT552-1 (TSSOP10)
NVT2003_06
Product data sheet
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
B
D
A
A
E
A1
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
b
2
y
y1 C
v M C A B
w M C
7
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
0.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Figure 17. Package outline SOT763-1 (DHVQFN16)
NVT2003_06
Product data sheet
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Rev. 5.1 — 8 October 2021
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17 / 33
NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
A
B
D
SOT758-1
terminal 1
index area
A
E
A1
c
detail X
e1
C
1/2 e
e
5
8
y
y1 C
v M C A B
w M C
b
L
4
9
e
e2
Eh
1/2 e
12
1
16
terminal 1
index area
13
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.75
1.45
3.1
2.9
1.75
1.45
0.5
1.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT758-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-03-25
02-10-21
Figure 18. Package outline SOT758-1 (HVQFN16)
NVT2003_06
Product data sheet
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
D
SOT403-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Figure 19. Package outline SOT403-1 (TSSOP16)
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
14 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
14.4 Reflow soldering
Key characteristics in reflow soldering are:
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 20) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 13 and Table 14
Table 13. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 14. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 20.
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 20. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
NVT2003_06
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Bidirectional voltage-level translator for open-drain and push-pull applications
15 Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP10 package
SOT552 -1
Hx
P1
Hy
Gy
solder land
occupied area
Dimensions in mm
Gy
Hy
Hx
P1
3.1
5.0
3.1
0.5
Issue date
11-04-19
13-05-02
sot552-1_fr
Figure 21. PCB footprint for SOT552-1 (TSSOP10); reflow soldering
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Footprint information for reflow soldering of DHVQFN16 package
SOT763-1
4.750
3.800
0.240
0.500
0.400
0.025
0.025
3.750
2.800
0.105
0.400
0.900
1.700
3.500
1.100
1.900
2.700
4.500
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
sot763-1_fr
Figure 22. PCB footprint for SOT763-1 (DHVQFN16); reflow soldering
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Footprint information for reflow soldering of HVQFN16 package
SOT758-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
Hy
SPy tot
nSPx
Gy
SPy
nSPy
SLy
By
Ay
SPx tot
SLx
Bx
Ax
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
0.50
4.00
4.00
2.20
2.20
0.90
0.24
1.50
1.50
Issue date
SPx tot SPy tot
0.90
0.90
SPx
SPy
Gx
Gy
Hx
Hy
0.30
0.30
3.30
3.30
4.25
4.25
12-03-07
12-03-08
sot758-1_fr
Figure 23. PCB footprint for SOT758-1 (HVQFN16); reflow soldering
NVT2003_06
Product data sheet
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NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Figure 24. PCB footprint for SOT403-1 (TSSOP16); solder mask opening pattern
NVT2003_06
Product data sheet
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Figure 25. PCB footprint for SOT403-1 (TSSOP16); I/O pads and solderable area
NVT2003_06
Product data sheet
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Figure 26. PCB footprint for SOT403-1 (TSSOP16); solder paste stencil
NVT2003_06
Product data sheet
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
16 Abbreviations
Table 15. Abbreviations
Acronym
Description
CDM
Charged Device Model
ESD
ElectroStatic Discharge
HBM
Human Body Model
2
I C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
PRR
Pulse Repetition Rate
RC
Resistor-Capacitor network
17 Revision history
Table 16. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NVT2003_06 v.5.1
20211008
Product data sheet
-
NVT2003_04_06 v.5
Modifications:
• Corrected PCB layout for SOT403-1
• NVT2004 discontinued in DN_201406022DN 30 Jun 2014
• The words "master" and "slave" replaced by "controller" and "target" throughout to comply with
NXP's inclusive language terminology.
NVT2003_04_06 v.5
20140219
Modifications:
• Table 1: Topside marking for NVT2004TL corrected from "N04" to "N4" (this is a correction to
documentation only; no change to device)
• deleted (old) Section 7.4 "Sizing pull-up resistor"
• added (new) Section 7.4
• added (new) Section 7.5
• added (new) Section 15
NVT2003_04_06 v.4
20120907
Product data sheet
-
NVT2003_04_06 v.3
NVT2003_04_06 v.3
20111025
Product data sheet
-
NVT2003_04_06 v.2
NVT2003_04_06 v.2
20110329
Product data sheet
-
NVT2003_04_06 v.1
NVT2003_04_06 v.1
20101004
Product data sheet
-
-
NVT2003_06
Product data sheet
Product data sheet
-
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Rev. 5.1 — 8 October 2021
NVT2003_04_06 v.4
© NXP B.V. 2021. All rights reserved.
29 / 33
NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
18 Legal information
18.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
18.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
NVT2003_06
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
NVT2003_06
Product data sheet
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
18.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Ordering information ..........................................2
Ordering options ................................................2
Pin description ...................................................4
Function selection (example) ............................ 5
Application operating conditions ........................6
Pull-up resistor minimum values, 3 mA
driver sink current for PCA9306 and
NVT20xx ............................................................9
Pull-up resistor minimum values, 10 mA
driver sink current for PCA9306 and
NVT20xx ............................................................9
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Pull-up resistor minimum values, 15 mA
driver sink current for PCA9306 and
NVT20xx ............................................................9
Limiting values ................................................ 11
Operating conditions ....................................... 11
Static characteristics ....................................... 12
Dynamic characteristics for open-drain
drivers ..............................................................13
SnPb eutectic process (from J-STD-020D) ..... 21
Lead-free process (from J-STD-020D) ............ 21
Abbreviations ...................................................29
Revision history ...............................................29
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Logic diagram of NVT2003/06 (positive
logic) .................................................................. 3
Pin configuration for TSSOP10 ......................... 3
Pin configuration for TSSOP16 ......................... 3
Pin configuration for DHVQFN16 ...................... 3
Pin configuration for HVQFN16 .........................4
Typical application circuit (switch always
enabled) .............................................................5
Typical application circuit (switch enable
control) ...............................................................6
Bidirectional translation to multiple higher
voltage levels .................................................... 7
Bidirectional level shifting between two
different power domains ....................................8
An example waveform for maximum
frequency .........................................................10
NVT2006 typical ON-state resistance
versus ambient temperature ............................13
AC test setup .................................................. 14
Example of typical AC waveform .................... 14
Load circuit for outputs ....................................14
NVT2003_06
Product data sheet
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
NVT2006 typical capacitance versus
propagation delay ............................................15
Package outline SOT552-1 (TSSOP10) ..........16
Package outline SOT763-1 (DHVQFN16) ....... 17
Package outline SOT758-1 (HVQFN16) ......... 18
Package outline SOT403-1 (TSSOP16) ..........19
Temperature profiles for large and small
components ..................................................... 22
PCB footprint for SOT552-1 (TSSOP10);
reflow soldering ............................................... 23
PCB footprint for SOT763-1 (DHVQFN16);
reflow soldering ............................................... 24
PCB footprint for SOT758-1 (HVQFN16);
reflow soldering ............................................... 25
PCB footprint for SOT403-1 (TSSOP16);
solder mask opening pattern ...........................26
PCB footprint for SOT403-1 (TSSOP16); I/
O pads and solderable area ............................27
PCB footprint for SOT403-1 (TSSOP16);
solder paste stencil ......................................... 28
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NVT2003/06
NXP Semiconductors
Bidirectional voltage-level translator for open-drain and push-pull applications
Contents
1
2
3
3.1
4
5
5.1
5.1.1
5.1.2
5.2
6
6.1
7
7.1
7.2
7.3
7.4
7.5
8
9
10
11
11.1
12
13
14
14.1
14.2
14.3
14.4
15
16
17
18
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Functional diagram ............................................. 3
Pinning information ............................................ 3
Pinning ............................................................... 3
3-bit in TSSOP10 package ................................3
6-bit in TSSOP16, DHVQFN16 and
HVQFN16 packages ..........................................3
Pin description ................................................... 4
Functional description ........................................5
Function table .................................................... 5
Application design-in information ..................... 5
Enable and disable ............................................5
Bidirectional translation ......................................7
Bidirectional level shifting between two
different power domains nominally at the
same potential ................................................... 7
How to size pull-up resistor value ......................8
How to design for maximum frequency
operation .......................................................... 10
Limiting values .................................................. 11
Recommended operating conditions .............. 11
Static characteristics ........................................ 12
Dynamic characteristics ...................................13
Open-drain drivers ........................................... 13
Performance curves ..........................................14
Package outline .................................................16
Soldering of SMD packages .............................20
Introduction to soldering .................................. 20
Wave and reflow soldering .............................. 20
Wave soldering ................................................ 20
Reflow soldering .............................................. 20
Soldering: PCB footprints ................................ 23
Abbreviations .................................................... 29
Revision history ................................................ 29
Legal information .............................................. 30
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 October 2021
Document identifier: NVT2003_06