NX3DV642GU,115

NX3DV642 3-lane high-speed MIPI compatible switch Rev. 1 — 20 August 2012 Product data sheet 1. General description The NX3DV642 is a high-speed triple-pole double-throw differential signal switch. The device is optimized for switching between two MIPI devices, such as cameras or LCD displays and on-board multimedia application processors. The NX3DV642 is compatible with the requirements of Mobile Industry Processor Interface (MIPI). The low capacitance design allows the NX3DV642 to switch signals that exceed 500 MHz in frequency 2. Features and benefits        Supply voltage range from 2.65 V to 4.3 V 7.5  typical ON resistance 8.4 pF typical ON capacitance 950 MHz typical bandwidth or data frequency Low crosstalk of 55 dB at 100 MHz Break-before-make switching ESD protection:  HBM JESD22-A114F Class 2 exceeds 2000 V  CDM AEC-Q100-011 revision B exceeds 1000 V  HBM exceeds 12000 V for power to GND protection  Latch-up performance exceeds 100 mA per JESD 78 Class II Level A  Specified from 40 C to +85 C 3. Applications  Dual camera applications for cell phones  Dual LCD applications for cell phones, digital camera displays and viewfinders 4. Ordering information Table 1. Ordering information Type number NX3DV642GU Package Temperature range Name Description Version 40 C to +85 C plastic, extremely thin quad flat package; no leads; 24 terminals; body 2.5 x 3.4 x 0.5 mm SOT1310-1 XQFN24 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 5. Marking Table 2. Marking Type number Marking code NX3DV642GU 3DV642 6. Functional diagram 1 2 3 4 5 6 8 11 CLK+ CLK- 1D+ 1D- 2D+ 2D- OE S CLK1+ CLK2+ CLK1CLK21D1+ 1D2+ 1D11D22D1+ 2D2+ 2D12D2- 17 22 16 23 15 20 14 21 13 19 12 18 CONTROL LOGIC aaa-002567 Fig 1. Logic symbol CAMERA 1 D D C CAMERA 2 C D D LCD 1 D D C LCD 2 D D C NX3DV642 NX3DV642 D D C MAP PROCESSOR D D C MAP PROCESSOR aaa-002568 Fig 2. Application block diagram NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 2 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 7. Pinning information 7.1 Pinning CLK2- CLK2+ 1D2- 1D2+ 2D2+ terminal 1 index area n.c. NX3DV642 24 23 22 21 20 19 17 CLK1+ 1D+ 3 16 CLK1- 1D- 4 15 1D1+ 2D+ 5 14 1D1- 2D- 6 13 2D1+ 7 8 9 10 11 12 2D1- 2 S CLK- VCC 2D2- GND 18 OE 1 n.c. CLK+ aaa-002569 Transparent top view Fig 3. Pin configuration SOT1310-1 (XQFN24) 7.2 Pin description Table 3. Pin description Symbol Pin Description CLK+, CLK 1, 2 common output or input clock path 1D+, 1D 3, 4 common output or input data path 1D 2D+, 2D 5, 6 common output or input data path 2D n.c. 7, 24 not connected OE 8 output enable input (active LOW) GND 9 ground (0 V) VCC 10 supply voltage S 11 select input 2D1+, 2D1 13, 12 independent input or output data path 2D1 1D1+, 1D1 15, 14 independent input or output data path 1D1 CLK1+, CLK1 17, 16 independent input or output clock path CLK1 2D2+, 2D2 19, 18 independent input or output data path 2D2 1D2+, 1D2 20, 21 independent input or output data path 1D2 CLK2+, CLK2 22, 23 independent input or output clock path CLK2 NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 3 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 8. Functional description Table 4. Function table[1] Input Channel on S OE L L CLKn, 1Dn, 2Dn = CLK1n, 1D1n, 2D1n H L CLKn, 1Dn, 2Dn = CLK2n, 1D2n, 2D2n X H switch off [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. (n = + or ) 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions [1] Max Unit 0.5 +5.5 V 0.5 +5.5 V 0.5 +5.5 V VI input voltage VSW switch voltage IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.5 V 50 +50 mA ISW switch current 100 +100 mA ICC supply current - +50 mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 533 mW [1] pins S and OE Min Tamb = 40 C to +85 C The minimum input voltage rating may be exceeded if the input current rating is observed. 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage VSW switch voltage Tamb ambient temperature [1] Conditions Min pins S and OE [1] Max Unit 2.65 4.3 V 0 4.3 V 0 4.5 V 40 +85 C To avoid sinking GND current from terminals CLKn, 1Dn and 2Dn when switch current flows in terminals CLK1n, CLK2n, 1D1n 1D2n, 2D1n and 2D2n (n = + or ), the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminals CLKn, 1Dn and 2Dn, no GND current flows from terminals CLK1n, CLK2n, 1D1n 1D2n, 2D1n and 2D2n. In this case, there is no limit for the voltage drop across the switch. NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 4 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter HIGH-level input voltage VIH Tamb = 40 C to +85 C Conditions Unit Min Typ[1] Max VCC = 2.65 V to 2.775 V 1.3 - - V VCC = 4.3 V 1.7 - - V LOW-level input voltage VCC = 2.65 V to 2.775 V - - 0.5 V VCC = 4.3 V - - 0.7 V VIK input clamping voltage VCC = 2.775 V; II = 18 mA 1.2 - - V II input leakage current pins S and OE; VI = GND to 4.3 V; VCC = 4.3 V - - 1 A IS(OFF) OFF-state leakage current VCC = 4.3 V; see Figure 4 - - 2 A IOFF power-off leakage current VI or VO = 0 V to 4.3 V; VCC = 0 V - - 2 A ICC supply current VI = VCC or GND; VSW = GND or VCC; VCC = 4.3 V - - 2 A ICC additional supply current VI = 1.8 V; VSW = GND or VCC; VCC = 2.775 V - - 1.5 A CI input capacitance pins S and OE VIL CS(OFF) OFF-state capacitance pins CLK1n, CLK2n, 1D1n 1D2n, 2D1n and 2D2n; VI = 0 V to 3.3 V [2] CS(ON) ON-state capacitance pins CLKn, 1Dn and 2Dn; VI = 0 V to 3.3 V [2] [1] Typical values are measured at Tamb = 25 C and VCC = 2.775 V. [2] n = + or . - 1.3 - pF - 3.0 - pF - 8.4 - pF 11.1 Test circuits VCC VIL or VIH S 1D1n 1 1Dn 1D2n 2 switch switch S 1 VIL 2 VIH IS OE GND VIH VI VO aaa-002570 VI = VCC or GND and VO = GND or VCC. Test circuit also applies for 2Dn, 2D1n, 2D2n CLKn, CLK1n and CLK2n (n = + or ). Fig 4. Test circuit for measuring OFF-state leakage current NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 5 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 11.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 40 C to +85 C Conditions Unit Min Typ[1] Max - 7.5 14  - 0.65 -  - 5.5 9.5  - 0.65 -  low speed mode RON ON resistance VI = 1.2 V; ISW = 10 mA; see Figure 5 VCC = 2.65 V RON ON resistance mismatch between channels [2] VI = 1.2 V; ISW = 10 mA VCC = 2.65 V High speed mode RON ON resistance VI = 0.1 V; ISW = 10 mA; see Figure 5 RON ON resistance mismatch between channels VI = 0.1 V; ISW = 10 mA VCC = 2.65 V [2] VCC = 2.65 V [1] Typical values are measured at Tamb = 25 C. [2] Measured at identical VCC, temperature and input voltage. 11.3 ON resistance test circuit and graphs V VSW VCC VIL or VIH S 1D1n 1 1Dn 1D2n 2 switch S 1 VIL 2 VIH switch OE GND VIL ISW VI aaa-002571 RON = VSW / ISW. Test circuit also applies for 2Dn, 2D1n, 2D2n CLKn, CLK1n and CLK2n (n = + or ). Fig 5. Test circuit for measuring ON resistance NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 6 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 9. Symbol Parameter propagation delay tpd Tamb = 40 C to +85 C Conditions CLKn to CLK1n or CLK2n; 1Dn to 1D1n or 1D2n or 2Dn to 2D1n or 2D2n; see Figure 6 enable time S or OE to CLKn, 1Dn or 2Dn; see Figure 7 tdis disable time S or OE to CLKn, 1Dn or 2Dn; see Figure 7 tsk(p) pulse skew time tsk(pr) output skew time process skew time - ns - 13.5 37 ns - 5.5 27 ns 3 7 - ns VCC = 2.65 V to 2.775 V; VSW = 0.2 V (p-p) [4] - 10 - ps VCC = 2.65 V to 2.775 V; VSW = 0.2 V (p-p) [4] - 15 - ps VCC = 2.65 V to 2.775 V; VSW = 0.2 V (p-p) [4] - 40 - ps [1] Typical values are measured at Tamb = 25 C, CL = 5 pF and VCC = 2.775 V. [2] n = + or . [3] 0.25 [4] VCC = 2.65 V to 2.775 V tsk(o) - [2][3] VCC = 2.65 V to 2.775 V break-before-make time see Figure 8 Max [2][3] VCC = 2.65 V to 2.775 V tb-m Min [2][3][4] VCC = 2.775 V ten Unit Typ[1] tpd is the same as tPLH and tPHL. ten is the same as tPZH tdis is the same as tPHZ [4] Guaranteed by design. 12.1 Waveform and test circuits 400 mV input 50% GND tPLH tPHL VOH 50% output VOL aaa-001359 Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. tr = tf  500 ps. Fig 6. The data input to output propagation delay times NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 7 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch VI S, OE input VM GND tPHZ VOH output HIGH to OFF OFF to HIGH tPZH VX VX GND switch enabled switch disabled switch enabled aaa-002572 Measurement points are given in Table 10. Logic level: VOH and VOLare typical output voltage levels that occur with the output load. Fig 7. Table 10. Enable and disable times Measurement points Supply voltage Input Output VCC VM VI VX 2.65 V to 2.775 V 0.5VCC VCC 0.9VOH VCC S 1D1n 1Dn 1D2n OE VIL VI G V VO RL CL VEXT = 1.2 V GND aaa-002573 a. Test circuit. VI 0.5VI 0.9VO 0.9VO VO tb-m 001aag572 b. Input and output measurement points Test circuit also applies for 2Dn, 2D1n, 2D2n CLKn, CLK1n and CLK2n (n = + or ). Fig 8. Test circuit for measuring break-before-make timing NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 8 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch VCC S 1D1n 1Dn 1D2n OE VIL VI G RL CL VEXT = 1.2 V GND aaa-002574 Test circuit also applies for 2Dn, 2D1n, 2D2n CLKn, CLK1n and CLK2n (n = + or ). Test data is given in Table 11. Definitions test circuit: RT = Termination resistance (should be equal to output impedance Zo of the pulse generator). RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. VI may be connected to S or OE. Fig 9. Table 11. Test circuit for measuring switching times Test data Supply voltage Input VCC VI tr, tf Load CL RL 2.65 V to 2.775 V VCC  2.5 ns 5 pF 50  12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf 2.5 ns. Symbol Parameter f(3dB) iso Tamb = 25 C Conditions 3 dB frequency response RL = 50 ; see Figure 10 isolation (OFF-state) fi = 100 MHz; RL = 50 ; see Figure 11 crosstalk CL = 0 pF; VCC = 2.775 V between switches; fi = 100 MHz; RL = 50 ; see Figure 12 VCC = 2.775 V [1] Typ Max - 950 - MHz - 35 - dB - 55 - [1] [1] VCC = 2.775 V Xtalk Unit Min [1] dB fi is biased at 0.5VCC. NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 9 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 12.3 Test circuits VCC 0.5 VCC switch S 1 VIL 2 VIH RL S VIL or VIH 1Dn 1D1n 1 1D2n 2 switch OE GND VIL fi dB CL aaa-002575 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Test circuit also applies for 2Dn, 2D1n, 2D2n CLKn, CLK1n and CLK2n (n = + or ). Fig 10. Test circuit for measuring the frequency response when channel is in ON-state 0.5 VCC VCC 0.5 VCC S VIL or VIH switch S 1 VIH 2 VIL RL RL 1Dn 1D1n 1 1D2n 2 switch OE GND VIH dB fi aaa-002576 Adjust fi voltage to obtain 0 dBm level at input. Test circuit also applies for 2Dn, 2D1n, 2D2n CLKn, CLK1n and CLK2n (n = + or ). Fig 11. Test circuit for measuring isolation (OFF-state) NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 10 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 0.5 VCC CLK+, nD+ fi CHANNEL ON RL CLK1+ or nD1+ V 50 Ω S VIL VO1 0.5 VCC RL CLK-, nDRi 50 Ω CLK2- or nD2CHANNEL OFF V VO2 aaa-002577 20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2). Fig 12. Test circuit for measuring crosstalk between switches NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 11 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 13. Package outline XQFN24: plastic, extremely thin quad flat package; no leads; 24 terminals; body 2.5 x 3.4 x 0.5 mm B D SOT1310-1 A terminal 1 index area E A A1 A3 detail X e1 1/2 e C A B C v w b C y y1 C e 7 12 L 13 6 1/2 e e2 e 1 18 terminal 1 index area 24 L1 19 X 0 2 mm scale Dimensions Unit mm A max nom min 0.5 A1 b A3 D 0.05 0.25 2.6 0.20 0.127 2.5 0.00 0.15 2.4 E e e1 e2 3.5 3.4 3.3 0.4 2.0 2.0 L L1 v w y y1 0.45 0.55 0.40 0.50 0.10 0.05 0.05 0.05 0.35 0.45 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included Outline version SOT1310-1 References IEC JEDEC JEITA sot1310-1_po European projection Issue date 11-07-19 11-08-18 MO-288 Fig 13. Package outline SOT1310-1 (XQFN24) NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 12 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes NX3DV642 v.1 20120820 Product data sheet - - NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 13 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. NX3DV642 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 14 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NX3DV642 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 20 August 2012 © NXP B.V. 2012. All rights reserved. 15 of 16 NX3DV642 NXP Semiconductors 3-lane high-speed MIPI compatible switch 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Waveform and test circuits . . . . . . . . . . . . . . . . 7 Additional dynamic characteristics . . . . . . . . . . 9 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 August 2012 Document identifier: NX3DV642