NX3L1G53GD

NX3L1G53 Low-ohmic single-pole double-throw analog switch Rev. 04 — 27 January 2010 Product data sheet 1. General description The NX3L1G53 is a low-ohmic single-pole double-throw analog switch suitable for use as an analog or digital 2:1 multiplexer/demultiplexer. It has a digital select input (S), two independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an active LOW enable input (E). When pin E is HIGH, the switch is turned off. Schmitt-trigger action at the digital inputs makes the circuit tolerant to slower input rise and fall times. The NX3L1G53 allows signals with amplitude up to VCC to be transmitted from Z to Y0 or Y1; or from Y0 or Y1 to Z. Its low ON resistance (0.5 Ω) and flatness (0.13 Ω) ensures minimal attenuation and distortion of transmitted signals. 2. Features Wide supply voltage range from 1.4 V to 4.3 V Very low ON resistance (peak): 1.6 Ω (typical) at VCC = 1.4 V 1.0 Ω (typical) at VCC = 1.65 V 0.55 Ω (typical) at VCC = 2.3 V 0.50 Ω (typical) at VCC = 2.7 V 0.50 Ω (typical) at VCC = 4.3 V Break-before-make switching High noise immunity ESD protection: HBM JESD22-A114E Class 3A exceeds 7500 V MM JESD22-A115-A exceeds 200 V CDM AEC-Q100-011 revision B exceeds 1000 V IEC61000-4-2 contact discharge exceeds 8000 V for switch ports CMOS low-power consumption Latch-up performance exceeds 100 mA per JESD 78 Class II Level A Direct interface with TTL levels at 3.0 V Control input accepts voltages above supply voltage High current handling capability (350 mA continuous current under 3.3 V supply) Specified from −40 °C to +85 °C and from −40 °C to +125 °C NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 3. Applications Cell phone PDA Portable media player 4. Ordering information Table 1. Ordering information Package Temperature range NX3L1G53GT NX3L1G53GD NX3L1G53GM −40 °C to +125 °C −40 °C to +125 °C −40 °C to +125 °C Name XSON8 Description plastic extremely thin small outline package; no leads; 8 terminals; body 1 × 1.95 × 0.5 mm Version SOT833-1 SOT996-2 SOT902-1 Type number XSON8U plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 × 2 × 0.5 mm XQFN8U plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 × 1.6 × 0.5 mm 5. Marking Table 2. Marking codes[1] Marking code D53 D53 D53 Type number NX3L1G53GT NX3L1G53GD NX3L1G53GM [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram 6 Y1 7 Y0 E 2 S5 Z1 001aad386 Fig 1. Logic symbol NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 2 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch Y0 S Z Y1 E 001aad387 Fig 2. Logic diagram 7. Pinning information 7.1 Pinning NX3L1G53 Z 1 8 VCC NX3L1G53 Z E 1 2 3 4 8 7 6 5 VCC Y0 Y1 S E 2 7 Y0 GND 3 6 Y1 GND GND 4 5 S GND 001aah454 001aaj534 Transparent top view Transparent top view Fig 3. Pin configuration SOT833-1 (XSON8) Fig 4. Pin configuration SOT996-2 (XSON8U) NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 3 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch NX3L1G53 terminal 1 index area Y0 1 VCC 8 7 Z Y1 2 6 E S 3 4 5 GND GND 001aah455 Transparent top view Fig 5. Pin configuration SOT902-1 (XQFN8U) 7.2 Pin description Table 3. Symbol Z E GND GND S Y1 Y0 VCC Pin description Pin SOT833-1 and SOT996-2 1 2 3 4 5 6 7 8 SOT902-1 7 6 5 4 3 2 1 8 common output or input enable input (active LOW) ground (0 V) ground (0 V) select input independent input or output independent input or output supply voltage Description 8. Functional description Table 4. Input S L H X [1] Function table[1] Channel E L L H Y0 to Z or Z to Y0 Y1 to Z or Z to Y1 switch off H = HIGH voltage level; L = LOW voltage level; X = don’t care. NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 4 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VSW IIK ISK ISW Parameter supply voltage input voltage switch voltage input clamping current switch clamping current switch current VI < −0.5 V VI < −0.5 V or VI > VCC + 0.5 V VSW > −0.5 V or VSW < VCC + 0.5 V; source or sink current VSW > −0.5 V or VSW < VCC + 0.5 V; pulsed at 1 ms duration, < 10 % duty cycle; peak current Tstg Ptot [1] [2] [3] Conditions select input S and enable input E [1] [2] Min −0.5 −0.5 −0.5 −50 - Max +4.6 +4.6 ±50 ±350 ±500 Unit V V mA mA mA mA VCC + 0.5 V storage temperature total power dissipation Tamb = −40 °C to +125 °C [3] −65 - +150 250 °C mW The minimum input voltage rating may be exceeded if the input current rating is observed. The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not exceed 4.6 V. For XSON8, XSON8U and XQFN8U packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K. 10. Recommended operating conditions Table 6. VCC VI VSW Tamb Δt/ΔV [1] Recommended operating conditions Conditions select input S and enable input E [1] Symbol Parameter supply voltage input voltage switch voltage ambient temperature input transition rise and fall rate Min 1.4 0 0 −40 - Max 4.3 4.3 VCC +125 200 Unit V V V °C ns/V VCC = 1.4 V to 4.3 V [2] To avoid sinking GND current from terminal Z when switch current flows in terminal Yn, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal Z, no GND current will flow from terminal Yn. In this case, there is no limit for the voltage drop across the switch. Applies to control signals. [2] NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 5 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions Min VIH HIGH-level input voltage VCC = 1.4 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V VIL LOW-level input voltage VCC = 1.4 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V II input leakage current OFF-state leakage current select input S and enable input E; VI = GND to 4.3 V; VCC = 1.4 V to 4.3 V Y0 and Y1 port; see Figure 6 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V IS(ON) ON-state leakage current Z port; see Figure 7 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V ±5 ±10 ±50 ±50 ±500 ±500 nA nA ±5 ±10 ±50 ±50 ±500 ±500 nA nA 0.65VCC 1.7 2.0 0.7VCC 25 °C Typ Max 0.35VCC 0.7 0.8 0.3VCC −40 °C to +125 °C Min 0.65VCC 1.7 2.0 0.7VCC Max Max (85 °C) (125 °C) 0.7 0.8 0.3VCC ±0.5 0.7 0.8 ±1 V V V V V V μA Unit 0.35VCC 0.35VCC V 0.3VCC V IS(OFF) ICC supply current VI = VCC or GND; VSW = GND or VCC VCC = 3.6 V VCC = 4.3 V 1.0 35 130 100 150 690 800 6000 7000 nA nA pF pF pF CI CS(OFF) CS(ON) input capacitance OFF-state capacitance ON-state capacitance NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 6 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 11.1 Test circuits VCC switch 1 2 switch IS S VIL VIH E VIH VIH VIL or VIH S Z E Y0 Y1 GND 1 2 VIH VI VO 001aad390 VI = 0.3 V or VCC − 0.3 V; VO = VCC − 0.3 V or 0.3 V. Fig 6. Test circuit for measuring OFF-state leakage current VCC switch 1 2 switch S VIL VIH E VIL VIL VIL or VIH IS VIL VI S Z E Y0 Y1 GND 1 2 VO 001aad391 VI = 0.3 V or VCC − 0.3 V; VO = open circuit. Fig 7. Test circuit for measuring ON-state leakage current NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 7 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 11.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15. Symbol RON(peak) Parameter ON resistance (peak) Conditions VI = GND to VCC; ISW = 100 mA; see Figure 8 VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 4.3 V ΔRON ON resistance mismatch VI = GND to VCC; between channels ISW = 100 mA VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 4.3 V RON(flat) ON resistance (flatness) VI = GND to VCC; ISW = 100 mA VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V VCC = 2.7 V VCC = 4.3 V [1] [2] [3] Typical values are measured at Tamb = 25 °C. Measured at identical VCC, temperature and input voltage. Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. [3] [2] −40 °C to +85 °C Min Typ[1] Max −40 °C to +125 °C Min Max Unit - 1.6 1.0 0.55 0.5 0.5 3.7 1.6 0.8 0.75 0.75 - 4.1 1.7 0.9 0.9 0.9 Ω Ω Ω Ω Ω - 0.04 0.04 0.02 0.02 0.02 0.3 0.2 0.08 0.075 0.075 - 0.3 0.3 0.1 0.1 0.1 Ω Ω Ω Ω Ω - 1.0 0.5 0.15 0.13 0.2 3.3 1.2 0.3 0.3 0.4 - 3.6 1.3 0.35 0.35 0.45 Ω Ω Ω Ω Ω NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 8 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 11.3 ON resistance test circuit and waveforms VCC V VSW Y0 Y1 1 2 switch 1 2 switch S VIL VIH E VIL VIL VIL or VIH S Z E VIL VI GND ISW 001aah456 RON = VSW / ISW. Fig 8. Test circuit for measuring ON resistance 1.6 RON (Ω) 1.2 001aag564 (1) 0.8 (2) (3) 0.4 (4) (5) (6) 0 0 1 2 3 4 VI (V) 5 (1) VCC = 1.5 V. (2) VCC = 1.8 V. (3) VCC = 2.5 V. (4) VCC = 2.7 V. (5) VCC = 3.3 V. (6) VCC = 4.3 V. Measured at Tamb = 25 °C. Fig 9. ON resistance as a function of input voltage NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 9 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 1.6 RON (Ω) 1.2 001aag565 1.0 RON (Ω) 0.8 (1) (2) (3) (4) 001aag566 0.6 0.8 (1) (2) (3) (4) 0.4 0.4 0.2 0 0 1 2 VI (V) 3 0 0 1 2 VI (V) 3 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 10. ON resistance as a function of input voltage; VCC = 1.5 V Fig 11. ON resistance as a function of input voltage; VCC = 1.8 V 1.0 RON (Ω) 0.8 001aag567 1.0 RON (Ω) 0.8 001aaj896 0.6 (1) (2) (3) (4) 0.6 (1) (2) (3) (4) 0.4 0.4 0.2 0.2 0 0 1 2 VI (V) 3 0 0 1 2 3 4 VI (V) 5 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 12. ON resistance as a function of input voltage; VCC = 2.5 V Fig 13. ON resistance as a function of input voltage; VCC = 2.7 V NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 10 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 1.0 RON (Ω) 0.8 001aag569 1.0 RON (Ω) 0.8 001aaj896 0.6 (1) (2) (3) (4) 0.6 (1) (2) (3) (4) 0.4 0.4 0.2 0.2 0 0 1 2 3 VI (V) 4 0 0 1 2 3 4 VI (V) 5 (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. (1) Tamb = 125 °C. (2) Tamb = 85 °C. (3) Tamb = 25 °C. (4) Tamb = −40 °C. Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V Fig 15. ON resistance as a function of input voltage; VCC = 4.3 V 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter Conditions Min ten enable time S or E to Z or Yn; see Figure 16 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 3.6 V to 4.3 V tdis disable time S or E to Z or Yn; see Figure 16 VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 4.3 V 10 7 5 4 4 19 14 9 8 8 21 16 10 9 9 23 17 11 9 9 ns ns ns ns ns 28 23 17 15 15 42 34 27 24 24 45 37 29 26 26 50 41 31 28 28 ns ns ns ns ns 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) Unit NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 11 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch Table 9. Dynamic characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18. Symbol Parameter Conditions Min tb-m break-before-make see Figure 17 time VCC = 1.4 V to 1.6 V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 2.7 V to 4.3 V [1] [2] [2] 25 °C Typ[1] Max −40 °C to +125 °C Min Max (85 °C) Max (125 °C) - Unit - 19 17 13 10 10 - 9 7 5 3 2 ns ns ns ns ns Typical values are measured at Tamb = 25 °C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively. Break-before-make guaranteed by design. 12.1 Waveform and test circuits VI S, E input GND ten VOH output OFF to HIGH HIGH to OFF GND tdis VOH output HIGH to OFF OFF to HIGH GND VX ten VX VX VX tdis VM VM 001aah457 Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 16. Enable and disable times Table 10. VCC 1.4 V to 4.3 V Measurement points Input VM 0.5VCC Output VX 0.9VOH Supply voltage NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 12 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch VCC S Z E VIL VI G GND 001aah458 Y0 Y1 V VO RL CL VEXT = 1.5 V a. Test circuit VI 0.5VI 0.9VO VO tb-m 0.9VO 001aag572 b. Input and output measurement points Fig 17. Test circuit for measuring break-before-make timing VCC S Z E VIL VI G GND 001aah459 Y0 Y1 1 2 switch V VO RL CL VEXT = 1.5 V Test data is given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. VI may be connected to S or E. Fig 18. Load circuit for switching times NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 13 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch Table 11. VCC Test data Input VI VCC tr, tf ≤ 2.5 ns Load CL 35 pF RL 50 Ω Supply voltage 1.4 V to 4.3 V 12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf ≤ 2.5 ns; Tamb = 25 °C. Symbol Parameter THD total harmonic distortion Conditions fi = 20 Hz to 20 kHz; RL = 32 Ω; see Figure 19 VCC = 1.4 V; VI = 1 V (p-p) VCC = 1.65 V; VI = 1.2 V (p-p) VCC = 2.3 V; VI = 1.5 V (p-p) VCC = 2.7 V; VI = 2 V (p-p) VCC = 4.3 V; VI = 2 V (p-p) f(−3dB) αiso Vct −3 dB frequency response isolation (OFF-state) crosstalk voltage RL = 50 Ω; see Figure 20 VCC = 1.4 V to 4.3 V fi = 100 kHz; RL = 50 Ω; see Figure 21 VCC = 1.4 V to 4.3 V between digital inputs and switch; fi = 1 MHz; CL = 50 pF; RL = 50 Ω; see Figure 22 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V Xtalk crosstalk between switches; fi = 100 kHz; RL = 50 Ω; see Figure 23 VCC = 1.4 V to 4.3 V Qinj charge injection fi = 1 MHz; CL = 0.1 nF; RL = 1 MΩ; Vgen = 0 V; Rgen = 0 Ω; see Figure 24 VCC = 1.5 V VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 4.3 V [1] fi is biased at 0.5VCC. [1] [1] [1] [1] Min - Typ 0.15 0.10 0.02 0.02 0.02 60 −90 Max - Unit % % % % % MHz dB - 0.2 0.3 - V V - −90 - dB - 3 4 6 9 15 - pC pC pC pC pC NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 14 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 12.3 Test circuits VCC 0.5VCC switch RL S VIL VIH E VIL VIL 1 2 VIL or VIH S Z E Y0 Y1 1 2 switch VIL fi D GND 001aah460 Fig 19. Test circuit for measuring total harmonic distortion VCC 0.5VCC switch RL S VIL VIH E VIL VIL 1 2 VIL or VIH S Z E Y0 Y1 1 2 switch VIL fi dB GND 001aah461 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads −3 dB. Fig 20. Test circuit for measuring the frequency response when switch is in ON-state 0.5VCC VCC 0.5VCC switch S VIH VIL E VIH VIH 1 2 RL RL VIL or VIH S Z E Y0 Y1 1 2 switch VIH fi dB GND 001aah462 Adjust fi voltage to obtain 0 dBm level at input. Fig 21. Test circuit for measuring isolation (OFF-state) NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 15 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch VCC VIL or VIH S Z E Y0 Y1 VI G logic input RL RL CL V VO 0.5VCC 0.5VCC 001aah452 a. Test circuit logic input (S, E) off on off VO Vct 001aah453 b. Input and output pulse definitions VI may be connected to S or E. Fig 22. Test circuit for measuring crosstalk voltage between digital inputs and switch VCC 0.5VCC 0.5VCC RL RL VIL or VIH S Z E Y0 Y1 1 2 VIH fi dB GND 001aah463 Fig 23. Test circuit for measuring crosstalk NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 16 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch VCC S Z E VIL VI G Rgen Y0 Y1 1 2 switch VO RL CL Vgen GND 001aad398 a. Test circuit logic input (S, E) off on off VO ΔVO 001aah451 b. Input and output pulse definitions Qinj = ΔVO × CL. ΔVO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. VI may be connected to S or E. Fig 24. Test circuit for measuring charge injection NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 17 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 13. Package outline XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm SOT833-1 1 2 3 b 4 4× L (2) L1 e 8 e1 7 e1 6 e1 5 8× (2) A A1 D E terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 25. Package outline SOT833-1 (XSON8) NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 18 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 3 x 2 x 0.5 mm SOT996-2 D B A E A A1 detail X terminal 1 index area e1 L1 1 e b 4 v w M M CAB C C y1 C y L2 L 8 5 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.35 0.15 D 2.1 1.9 E 3.1 2.9 e 0.5 e1 1.5 L 0.5 0.3 L1 0.15 0.05 L2 0.6 0.4 v 0.1 w 0.05 y 0.05 y1 0.1 OUTLINE VERSION SOT996-2 REFERENCES IEC --JEDEC JEITA --- EUROPEAN PROJECTION ISSUE DATE 07-12-18 07-12-21 Fig 26. Package outline SOT996-2 (XSON8U) NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 19 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm SOT902-1 D terminal 1 index area B A E A A1 detail X L1 L e 4 e ∅v M C A B ∅w M C 5 C y1 C y 3 metal area not for soldering 2 6 b e1 e1 7 1 terminal 1 index area 8 X 0 1 scale 2 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max 0.5 A1 0.05 0.00 b 0.25 0.15 D 1.65 1.55 E 1.65 1.55 e 0.55 e1 0.5 L 0.35 0.25 L1 0.15 0.05 v 0.1 w 0.05 y 0.05 y1 0.05 OUTLINE VERSION SOT902-1 REFERENCES IEC --JEDEC MO-255 JEITA --- EUROPEAN PROJECTION ISSUE DATE 05-11-25 07-11-14 Fig 27. Package outline SOT902-1 (XQFN8U) NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 20 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 14. Abbreviations Table 13. Acronym CDM CMOS ESD HBM MM TTL Abbreviations Description Charged Device Model Complementary Metal Oxide Semiconductor ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic 15. Revision history Table 14. Revision history Release date 20100127 Data sheet status Product data sheet Change notice Supersedes NX3L1G53_3 Document ID NX3L1G53_4 Modifications: NX3L1G53_3 NX3L1G53_2 NX3L1G53_1 • • Section 2: IEC61000-4-2 added. Table 8: ON resistance (flattness) changed at VCC = 4.3 V. Product data sheet Product data sheet Product data sheet NX3L1G53_2 NX3L1G53_1 - 20090417 20080718 20080408 NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 21 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NX3L1G53_4 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 27 January 2010 22 of 23 NXP Semiconductors NX3L1G53 Low-ohmic single-pole double-throw analog switch 18. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 12.3 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ON resistance test circuit and waveforms . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 11 Waveform and test circuits . . . . . . . . . . . . . . . 12 Additional dynamic characteristics . . . . . . . . . 14 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 January 2010 Document identifier: NX3L1G53_4