NX3L2467
Dual low-ohmic double-pole double-throw analog switch
Rev. 5.1 — 18 May 2021
1
Product data sheet
General description
The NX3L2467 is a dual low-ohmic double-pole double-throw analog switch suitable for
use as an analog or digital multiplexer/demultiplexer. It consists of four switches, each
with two independent input/outputs (nY0 and nY1) and a common input/output (nZ).
The two digital inputs (1S and 2S) are used to select the switch position. 1S is used
in selecting the independent inputs/outputs switched to 1Z and 2Z, and 2S is used in
selecting the independent inputs/outputs switched to 3Z and 4Z. Schmitt trigger action
at the digital inputs makes the circuit tolerant to slower input rise and fall times. Low
threshold digital inputs allows this device to be driven by 1.8 V logic levels in 3.3 V
applications without significant increase in supply current ICC. This makes it possible
for the NX3L467 to switch 4.3 V signals with a 1.8 V digital controller, eliminating the
need for logic level translation. The NX3L2467 allows signals with amplitude up to VCC
to be transmitted from nZ to nY0 or nY1; or from nY0 or nY1 to nZ. Its low ON resistance
(0.5 Ω) and flatness (0.13 Ω) ensures minimal attenuation and distortion of transmitted
signals.
2
Features and benefits
• Wide supply voltage range from 1.4 V to 4.3 V
• Very low ON resistance (peak):
– 1.7 Ω (typical) at VCC = 1.4 V
– 1.0 Ω (typical) at VCC = 1.65 V
– 0.6 Ω (typical) at VCC = 2.3 V
– 0.5 Ω (typical) at VCC = 2.7 V
– 0.5 Ω (typical) at VCC = 4.3 V
• Break-before-make switching
• High noise immunity
• ESD protection:
– HBM JESD22-A114F Class 3A exceeds 4000 V
– MM JESD22-A115-A exceeds 200 V
– CDM AEC-Q100-011 revision B exceeds 1000 V
– IEC61000-4-2 contact discharge exceeds 6000 V for switch ports
• CMOS low-power consumption
• Latch-up performance exceeds 100 mA per JESD 78B Class II Level A
• 1.8 V control logic at VCC = 3.6 V
• Control input accepts voltages above supply voltage
• Very low supply current, even when input is below VCC
• High current handling capability (350 mA continuous current under 3.3 V supply)
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
3
Applications
• Cell phone
• PDA
• Portable media player
4
Ordering information
Table 1. Ordering information
Type number
Topside
mark
Package
Name
Description
Version
NX3L2467PW
X3L2467
TSSOP16
plastic thin shrink small outline package; 16
leads; body width 4.4 mm
SOT403-1
NX3L2467HR
D67
HXQFN16
plastic thermal enhanced extremely thin quad
flat package; no leads; 16 terminals; body 3 × 3
× 0.5 mm
SOT1039-2
NX3L2467GU
D67
XQFN16
plastic, extremely thin quad flat package; no
SOT1161-1
leads; 16 terminals; body 1.80 × 2.60 × 0.50 mm
4.1 Ordering options
Table 2. Ordering options
Type number Orderable part number
Package
Packing method
Minimum
order
quantity
Temperature
NX3L2467PW NX3L2467PW,118
TSSOP16
Reel 13" Q1/T1 NDP
2500
Tamb = -40 °C to +125 °C
NX3L2467HR NX3L2467HRZ
HXQFN16
Reel 7" Q1/T1 NDP
[1]
SSB
1500
Tamb = -40 °C to +125 °C
HXQFN16
Reel 7" Q1/T1 NDP
1500
Tamb = -40 °C to +125 °C
XQFN16
Reel 7" Q1/T1 NDP
4000
Tamb = -40 °C to +125 °C
NX3L2467HR,115
NX3L2467GU NX3L2467GU,115
[1]
[2]
[2]
This packing method uses a Static Shielding Bag (SSB) solution. Material is to be kept in the sealed bag between uses.
Will go EOL - migrate to new leadframe NX3L2467HRZ orderable part number.
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
2 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
5
Functional diagram
1Y1
1Z
1Y0
1Y1
2Y0
2Y1
3Y0
3Y1
4Y0
4Y1
1Z
1Y0
1S
2Z
1S
2Y1
3Z
2Z
4Z
2Y0
2S
001aak175
001aak174
Figure 1. Logic symbol
6
Figure 2. Logic diagram
Pinning information
NX3L2467
1Y1
1
16 VCC
1Z
2
15 4Y0
1Y0
3
14 4Z
1Y1
VCC
4Y0
15
14
13
2Z
6
11 3Y0
8
4
2Y0
7
10 3Z
3Z
2Z
7
3
GND
8
3Y1
2Y1
NX3L2467
6
12 2S
2
GND
13 4Y1
5
1S
5
4
1
2Y0
1S
2Y1
1Y0
1Z
terminal 1
index area
16
6.1 Pinning
9
3Y1
Figure 3. Pin configuration SOT403-1 (TSSOP16)
Product data sheet
4Z
11
4Y1
10
2S
9
3Y0
001aak176
Transparent top view
001aak177
NX3L2467
12
Figure 4. Pin configuration SOT1039-2 (HXQFN16)
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
3 / 24
NX3L2467
NXP Semiconductors
13 4Y0
14 VCC
terminal 1
index area
15 1Y1
16 1Z
Dual low-ohmic double-pole double-throw analog switch
1Y0 1
12 4Z
1S 2
11 4Y1
NX3L2467
2Y1 3
10 2S
3Z 8
3Y1 7
GND 6
9 3Y0
2Y0 5
2Z 4
001aam031
Transparent top view
Figure 5. Pin configuration SOT1161-1 (XQFN16)
6.2 Pin description
Table 3. Pin description
Symbol
Pin
Description
SOT1039-2 and SOT1161-1
SOT403-1
1Y0, 2Y0, 3Y0, 4Y0
1, 5, 9, 13
3, 7, 11, 15
independent input or output
1S, 2S
2, 10
4, 12
select input
1Y1, 2Y1, 3Y1, 4Y1
15, 3, 7, 11
1, 5, 9, 13
independent input or output
1Z, 2Z, 3Z, 4Z
16, 4, 8, 12
2, 6, 10, 14
common output or input
GND
6
8
ground (0 V)
VCC
14
16
supply voltage
7
Functional description
Table 4. Function table
[1]
Input nS
Channel on
L
nY0
H
nY1
[1]
H = HIGH voltage level; L = LOW voltage level.
8
Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
VI
VSW
input voltage
Conditions
select input nS
switch voltage
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
Min
Max
Unit
-0.5
+4.6
V
[1]
-0.5
+4.6
V
[2]
-0.5
VCC + 0.5 V
© NXP B.V. 2021. All rights reserved.
4 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
Table 5. Limiting values...continued
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
IIK
input clamping current
VI < -0.5 V
-50
-
mA
ISK
switch clamping current
VI < -0.5 V or VI > VCC + 0.5 V
-
±50
mA
ISW
switch current
VSW > -0.5 V or VSW < VCC + 0.5 V; source or
sink current
-
±350
mA
VSW > -0.5 V or VSW < VCC + 0.5 V; pulsed at 1
ms duration, < 10 % duty cycle; peak current
-
±500
mA
-65
+150
°C
Tstg
storage temperature
Ptot
total power dissipation
[1]
[2]
[3]
[4]
[5]
Tamb = -40 °C to +125 °C
TSSOP16
[3]
-
500
mW
HXQFN16
[4]
-
250
mW
XQFN16
[5]
-
250
mW
The minimum input voltage rating may be exceeded if the input current rating is observed.
The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not exceed 4.6 V.
For TSSOP16 package: above 60 °C the value of Ptot derates linearly with 5.5 mW/K above.
For HXQFN16 package: above 135 °C the value of Ptot derates linearly with 16.9 mW/K.
For XQFN16 package: above 133 °C the value of Ptot derates linearly with 14.5 mW/K.
9
Recommended operating conditions
Table 6. Recommended operating conditions
Symbol Parameter
VCC
supply voltage
VI
input voltage
VSW
switch voltage
Tamb
ambient temperature
Δt/ΔV
[1]
[2]
input transition rise and fall rate
Conditions
select input nS
[1]
VCC = 1.4 V to 4.3 V
[2]
Min
Max
Unit
1.4
4.3
V
0
4.3
V
0
VCC
V
-40
+125
°C
-
200
ns/V
To avoid sinking GND current from terminal nZ when switch current flows in terminal nYn, the voltage drop across the bidirectional switch must not exceed
0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nYn. In this case, there is no limit for the voltage drop across the
switch.
Applies to control signal levels.
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
5 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
10 Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground 0 V).
Symbol
VIH
VIL
Parameter
Conditions
Tamb = 25 °C
Unit
Min
Typ
Max
Min
Max
(85 °C)
Max
(125 °C)
0.9
-
-
0.9
-
-
V
0.9
-
-
0.9
-
-
V
VCC = 2.3 V to 2.7 V
1.1
-
-
1.1
-
-
V
VCC = 2.7 V to 3.6 V
1.3
-
-
1.3
-
-
V
VCC = 3.6 V to 4.3 V
1.4
-
-
1.4
-
-
V
VCC = 1.4 V to 1.6 V
-
-
0.3
-
0.3
0.3
V
VCC = 1.65 V to 1.95 V
-
-
0.4
-
0.4
0.3
V
VCC = 2.3 V to 2.7 V
-
-
0.4
-
0.4
0.4
V
VCC = 2.7 V to 3.6 V
-
-
0.5
-
0.5
0.5
V
HIGH-level input VCC = 1.4 V to 1.6 V
voltage
VCC = 1.65 V to 1.95 V
LOW-level input
voltage
Tamb = -40 °C to +125 °C
VCC = 3.6 V to 4.3 V
-
-
0.6
-
0.6
0.6
V
II
input leakage
current
select input nS; VI = GND to
4.3 V; VCC = 1.4 V to 4.3 V
-
-
-
-
±0.5
±1
μA
IS(OFF)
OFF-state
leakage current
nY0 and nY1 port; see
Figure 6
VCC = 1.4 V to 3.6 V
-
-
±5
-
±50
±500
nA
VCC = 3.6 V to 4.3 V
-
-
±10
-
±50
±500
nA
VCC = 1.4 V to 3.6 V
-
-
±5
-
±50
±500
nA
VCC = 3.6 V to 4.3 V
-
-
±10
-
±50
±500
nA
VCC = 3.6 V
-
-
100
-
500
5000
nA
VCC = 4.3 V
-
-
150
-
800
6000
nA
additional supply VSW = GND or VCC
current
VI = 2.6 V; VCC = 4.3 V
-
2.0
4.0
-
7
7
μA
VI = 2.6 V; VCC = 3.6 V
-
0.35
0.7
-
1
1
μA
VI = 1.8 V; VCC = 4.3 V
-
7.0
10.0
-
15
15
μA
VI = 1.8 V; VCC = 3.6 V
-
2.5
4.0
-
5
5
μA
VI = 1.8 V; VCC = 2.5 V
-
50
200
-
300
500
nA
IS(ON)
ICC
ΔICC
ON-state
leakage current
supply current
nZ port; VCC = 1.4 V to 3.6 V;
see Figure 7
VI = VCC or GND; VSW = GND
or VCC
CI
input
capacitance
-
1.0
-
-
-
-
pF
CS(OFF)
OFF-state
capacitance
-
35
-
-
-
-
pF
CS(ON)
ON-state
capacitance
-
130
-
-
-
-
pF
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
6 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
10.1 Test circuits
VCC
nS
VIL or VIH
nY0 1
nZ
switch
nY1 2
switch
nS
1
VIH
2
VIL
IS
VI
VO
GND
012aaa000
VI = 0.3 V or VCC - 0.3 V; VO = VCC - 0.3 V or 0.3 V.
Figure 6. Test circuit for measuring OFF-state leakage current
VCC
VIL or VIH
IS
nS
nY0 1
nZ
nY1 2
switch
nS
1
VIH
2
VIL
switch
VI
VO
GND
012aaa001
VI = 0.3 V or VCC - 0.3 V; VO = VCC - 0.3 V or 0.3 V.
Figure 7. Test circuit for measuring ON-state leakage current
10.2 ON resistance
Table 8. ON resistance
[1]
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15.
Symbol
Parameter
Conditions
Tamb = -40 °C to +85 °C
Min
RON(peak)
ON resistance
(peak)
Product data sheet
Max
Min
Max
Unit
VCC = 1.4 V
-
1.7
3.7
-
4.1
Ω
VCC = 1.65 V
-
1.0
1.6
-
1.7
Ω
VCC = 2.3 V
-
0.6
0.8
-
0.9
Ω
VCC = 2.7 V
-
0.5
0.75
-
0.9
Ω
-
0.5
0.75
-
0.9
Ω
-
0.18
0.3
-
0.3
Ω
VI = GND to VCC; ISW = 100 mA
ON resistance
mismatch
VCC = 1.4 V; VSW = 0.4 V
between channels
VCC = 1.65 V; VSW = 0.5 V
NX3L2467
Tamb = -40 °C to +125 °C
VI = GND to VCC; ISW = 100 mA;
see Figure 8
VCC = 4.3 V
ΔRON
Typ
[2]
[3]
-
0.18
0.2
-
0.3
Ω
VCC = 2.3 V; VSW = 0.7 V
-
0.07
0.1
-
0.13
Ω
VCC = 2.7 V; VSW = 0.8 V
-
0.07
0.1
-
0.13
Ω
VCC = 4.3 V; VSW = 0.8 V
-
0.07
0.1
-
0.13
Ω
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
7 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
Table 8. ON resistance
[1]
...continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15.
Symbol
Parameter
Conditions
Tamb = -40 °C to +85 °C
Min
RON(flat)
[1]
[2]
[3]
[4]
VI = GND to VCC; ISW = 100 mA
ON resistance
(flatness)
Typ
[2]
Tamb = -40 °C to +125 °C
Unit
Max
Min
Max
1.0
3.3
-
3.6
Ω
[4]
VCC = 1.4 V
-
VCC = 1.65 V
-
0.5
1.2
-
1.3
Ω
VCC = 2.3 V
-
0.15
0.3
-
0.35
Ω
VCC = 2.7 V
-
0.13
0.3
-
0.35
Ω
VCC = 4.3 V
-
0.2
0.4
-
0.45
Ω
For NX3L2467PW (TSSOP16 package), all ON resistance values are up to 0.05 Ω higher.
Typical values are measured at Tamb = 25 °C.
Measured at identical VCC, temperature and input voltage.
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature.
10.3 ON resistance test circuit and graphs
001aag564
1.6
RON
(Ω)
1.2
(1)
0.8
(2)
(3)
(4)
0.4
VSW
V
VCC
nS
VIL or VIH
nZ
nY0 1 switch
nY1 2
VI
0
switch
nS
1
VIL
2
VIH
ISW
GND
012aaa002
RON = VSW / ISW.
Figure 8. Test circuit for measuring ON resistance
NX3L2467
Product data sheet
0
1
2
(5)
(6)
3
4
VI (V)
5
1. VCC = 1.5 V.
2. VCC = 1.8 V.
3. VCC = 2.5 V.
4. VCC = 2.7 V.
5. VCC = 3.3 V.
6. VCC = 4.3 V.
Measured at Tamb = 25 °C.
Figure 9. Typical ON resistance as a function of input
voltage
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
8 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
001aag565
1.6
RON
(Ω)
RON
(Ω)
0.8
1.2
0.4
0.4
0
0.2
0
1
2
VI (V)
0
3
Tamb = 125 °C.
Tamb = 85 °C.
Tamb = 25 °C.
Tamb = -40 °C.
1.
2.
3.
4.
Figure 10. ON resistance as a function of input voltage;
VCC = 1.5 V
0
1
2
3
VI (V)
Tamb = 125 °C.
Tamb = 85 °C.
Tamb = 25 °C.
Tamb = -40 °C.
Figure 11. ON resistance as a function of input voltage;
VCC = 1.8 V
001aag567
1.0
001aag568
1.0
RON
(Ω)
RON
(Ω)
0.8
0.8
0.6
0.6
(1)
(2)
(3)
(4)
0.4
0
(1)
(2)
(3)
(4)
0.4
0.2
1.
2.
3.
4.
(1)
(2)
(3)
(4)
0.6
(1)
(2)
(3)
(4)
0.8
1.
2.
3.
4.
001aag566
1.0
0.2
0
1
2
VI (V)
Tamb = 125 °C.
Tamb = 85 °C.
Tamb = 25 °C.
Tamb = -40 °C.
1.
2.
3.
4.
Figure 12. ON resistance as a function of input voltage;
VCC = 2.5 V
NX3L2467
Product data sheet
0
3
0
1
2
VI (V)
3
Tamb = 125 °C.
Tamb = 85 °C.
Tamb = 25 °C.
Tamb = -40 °C.
Figure 13. ON resistance as a function of input voltage;
VCC = 2.7 V
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
9 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
001aag569
1.0
RON
(Ω)
RON
(Ω)
0.8
0.8
0.6
0.6
(1)
(2)
(3)
(4)
0.4
0
(1)
(2)
(3)
(4)
0.4
0.2
1.
2.
3.
4.
001aaj896
1.0
0.2
0
1
2
3
VI (V)
0
4
Tamb = 125 °C.
Tamb = 85 °C.
Tamb = 25 °C.
Tamb = -40 °C.
1.
2.
3.
4.
Figure 14. ON resistance as a function of input voltage;
VCC = 3.3 V
0
1
2
3
4
VI (V)
5
Tamb = 125 °C.
Tamb = 85 °C.
Tamb = 25 °C.
Tamb = -40 °C.
Figure 15. ON resistance as a function of input voltage;
VCC = 4.3 V
11 Dynamic characteristics
Table 9. Dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol
Parameter
Conditions
Tamb = 25 °C
Min
ten
tdis
enable time
disable time
NX3L2467
Product data sheet
Typ
[1]
Tamb = -40 °C to +125 °C
Max
Min
Max
(85 °C)
Max
(125 °C)
Unit
nS to nZ or nYn; see
Figure 16
VCC = 1.4 V to 1.6 V
-
41
90
-
120
120
ns
VCC = 1.65 V to 1.95 V
-
30
70
-
80
90
ns
VCC = 2.3 V to 2.7 V
-
20
45
-
50
55
ns
VCC = 2.7 V to 3.6 V
-
19
40
-
45
50
ns
VCC = 3.6 V to 4.3 V
-
19
40
-
45
50
ns
VCC = 1.4 V to 1.6 V
-
24
70
-
80
90
ns
VCC = 1.65 V to 1.95 V
-
15
55
-
60
65
ns
VCC = 2.3 V to 2.7 V
-
9
25
-
30
35
ns
VCC = 2.7 V to 3.6 V
-
8
20
-
25
30
ns
VCC = 3.6 V to 4.3 V
-
8
20
-
25
30
ns
nS to nZ or nYn; see
Figure 16
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
10 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
Table 9. Dynamic characteristics...continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 18.
Symbol
Parameter
Conditions
Tamb = 25 °C
Min
tb-m
[1]
[2]
break-before-make
time
Typ
[1]
Tamb = -40 °C to +125 °C
Max
Min
Max
(85 °C)
Max
(125 °C)
Unit
[2]
see Figure 17
VCC = 1.4 V to 1.6 V
-
20
-
9
-
-
ns
VCC = 1.65 V to 1.95 V
-
17
-
7
-
-
ns
VCC = 2.3 V to 2.7 V
-
13
-
4
-
-
ns
VCC = 2.7 V to 3.6 V
-
11
-
3
-
-
ns
VCC = 3.6 V to 4.3 V
-
11
-
2
-
-
ns
Typical values are measured at Tamb = 25 °C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively.
Break-before-make guaranteed by design.
11.1 Waveform and test circuits
VI
VM
nS input
GND
ten
nZ output
nY1 connected to VEXT OFF to HIGH
HIGH to OFF
VOH
tdis
VX
GND
tdis
nZ output
nY0 connected to VEXT HIGH to OFF
OFF to HIGH
VX
VOH
ten
VX
VX
012aaa003
GND
Measurement points are given in Table 10.
Logic level: VOH is typical output voltage level that occurs with the output load.
Figure 16. Enable and disable times
Table 10. Measurement points
Supply voltage
Input
Output
VCC
VM
VX
1.4 V to 4.3 V
0.5VCC
0.9VOH
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
11 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
VCC
nS
nY0
nZ
G
V
VI
VO
RL
nY1
VEXT = 1.5 V
CL
GND
012aaa004
a. Test circuit
VI
0.5VI
0.9VO
0.9VO
VO
tb-m
001aag572
b. Input and output measurement points
Figure 17. Test circuit for measuring break-before-make timing
VCC
G
VI
V
VO
RL
nS
nY0
1
nZ
nY1
2
switch
VEXT = 1.5 V
CL
GND
012aaa005
Test data is given in Table 11.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
VEXT = External voltage for measuring switching times.
Figure 18. Test circuit for measuring switching times
Table 11. Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
1.4 V to 4.3 V
VCC
≤ 2.5 ns
35 pF
50 Ω
NX3L2467
Product data sheet
Load
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
12 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
11.2 Additional dynamic characteristics
Table 12. Additional dynamic characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise
specified); tr = tf ≤ 2.5 ns; Tamb = 25 °C.
Symbol Parameter
THD
total harmonic
distortion
Conditions
Min
fi = 20 Hz to 20 kHz; RL = 32 Ω; see Figure 19
αiso
-3 dB frequency
response
isolation (OFF-state)
crosstalk voltage
0.15
-
%
VCC = 1.65 V; VI = 1.2 V (p-p)
-
0.10
-
%
VCC = 2.3 V; VI = 1.5 V (p-p)
-
0.02
-
%
VCC = 2.7 V; VI = 2 V (p-p)
-
0.02
-
%
-
0.02
-
%
-
60
-
MHz
-
-90
-
dB
-
0.2
-
V
-
0.3
-
V
-
-90
-
dB
VCC = 1.5 V
-
3
-
pC
VCC = 1.8 V
-
4
-
pC
VCC = 2.5 V
-
6
-
pC
VCC = 3.3 V
-
9
-
pC
VCC = 4.3 V
-
15
-
pC
RL = 50 Ω; see Figure 20
[1]
VCC = 1.4 V to 4.3 V
fi = 100 kHz; RL = 50 Ω; see Figure 21
[1]
between digital inputs and switch; fi = 1 MHz; CL =
50 pF; RL = 50 Ω; see Figure 22
VCC = 1.4 V to 3.6 V
VCC = 3.6 V to 4.3 V
Xtalk
crosstalk
between switches; fi = 100 kHz; RL = 50 Ω; see
Figure 23
VCC = 1.4 V to 4.3 V
Qinj
[1]
charge injection
Unit
-
VCC = 1.4 V to 4.3 V
Vct
Max
VCC = 1.4 V; VI = 1 V (p-p)
VCC = 4.3 V; VI = 2 V (p-p)
f(-3dB)
Typ
[1]
[1]
fi = 1 MHz; CL = 0.1 nF; RL = 1 MΩ; Vgen = 0 V; Rgen
= 0 Ω; see Figure 24
fi is biased at 0.5VCC.
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
13 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
11.3 Test circuits
VCC
0.5VCC
RL
nS
VIL or VIH
switch
nS
1
VIL
2
VIH
nY0 1 switch
nY1 2
nZ
D
fi
GND
012aaa006
Figure 19. Test circuit for measuring total harmonic distortion
VCC
0.5VCC
RL
nS
VIL or VIH
nZ
nY0 1 switch
nY1 2
switch
nS
1
VIL
2
VIH
dB
fi
GND
012aaa007
Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads -3 dB.
Figure 20. Test circuit for measuring the frequency response when channel is in ON-state
0.5VCC
VCC
0.5VCC
RL
RL
nS
VIL or VIH
nZ
nY0 1 switch
nY1 2
switch
nS
1
VIH
2
VIL
dB
fi
GND
012aaa008
Adjust fi voltage to obtain 0 dBm level at input.
Figure 21. Test circuit for measuring isolation (OFF-state)
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
14 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
VCC
VI
G
logic
input
nS
nY0 1
nZ
nY1 2
switch
nS
1
VIL
2
VIH
switch
RL
RL
0.5VCC
0.5VCC
V
CL
VO
012aaa009
a. Test circuit
logic
input (nS)
off
on
off
Vct
VO
012aaa010
b. Input and output pulse definitions
Figure 22. Test circuit for measuring crosstalk voltage between digital inputs and switch
0.5VCC
nY0 or nZ
fi
CHANNEL
ON
RL
nZ or nY0
V
50 Ω
0.5VCC
nS
VIL
VO1
RL
nY0 or nZ
Ri
50 Ω
nZ or nY0
CHANNEL
OFF
V
VO2
001aak178
20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2).
Figure 23. Test circuit for measuring crosstalk between switches
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
15 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
VCC
nS
nY0 1
nZ
nY1 2
switch
Rgen
VI
G
VO
RL
CL
Vgen
GND
012aaa011
a. Test circuit
logic
(nS) off
input
on
VO
off
ΔVO
012aaa012
b. Input and output pulse definitions
Definition: Qinj = ΔVO × CL.
ΔVO = output voltage variation.
Rgen = generator resistance.
Vgen = generator voltage.
Figure 24. Test circuit for measuring charge injection
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
16 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
12 Package outline
HXQFN16 (U): plastic thermal enhanced extremely thin quad flat package; no
leads; 16 terminals; body 3 x 3 x 0.5 mm
B
D
SOT1039-2
A
terminal 1
index area
E
A
A1
c
detail X
e1
1/2 e
e
v
w
b
5
8
C
C A B
C
y1 C
y
L
4
9
e
e2
Eh
1/2 e
1
12
terminal 1
index area
16
X
13
Dh
0
1
Dimensions
Unit
mm
max
nom
min
2 mm
scale
A
0.5
A1
b
c
D
0.05 0.35
3.1
0.30 0.127 3.0
0.00 0.25
2.9
Dh
E
Eh
e
e1
e2
L
v
1.95
1.85
1.75
3.1
3.0
2.9
1.95
1.85
1.75
0.5
1.5
1.5
0.40
0.35
0.30
0.1
w
y
0.05 0.05
y1
0.1
sot1039-2_po
References
Outline
version
IEC
SOT1039-2
---
JEDEC
JEITA
---
European
projection
Issue date
11-03-30
17-10-31
Figure 25. Package outline SOT1039-2 (HXQFN16)
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
17 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
D
SOT403-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Figure 26. Package outline SOT403-1 (TSSOP16)
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
18 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
XQFN16: plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 x 2.60 x 0.50 mm
SOT1161-1
X
B
D
A
terminal 1
index area
E
A
A1
A3
detail X
e1
e
b
5
v
w
8
C
C A B
C
y1 C
y
L
4
9
e
e2
1
terminal 1
index area
12
16
L1
13
0
1
Dimensions
Unit(1)
mm
max
nom
min
2 mm
scale
A
A1
0.5
0.05
A3
b
0.25
0.127 0.20
0.00
0.15
D
E
e
e1
e2
1.9
1.8
1.7
2.7
2.6
2.5
0.4
1.2
1.2
L
L1
0.45 0.55
0.40 0.50
0.35 0.45
v
0.1
w
y
y1
0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT1161-1
---
---
---
sot1161-1_po
European
projection
Issue date
09-12-28
09-12-29
Figure 27. Package outline SOT1161-1 (XQFN16)
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
19 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
13 Abbreviations
Table 13. Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
PDA
Personal Digital Assistant
14 Revision history
Table 14. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NX3L2467 v.5.1
20210518
Product data sheet
-
NX3L2467 v.5
Modifications:
• Updated Section 4 "Ordering information"
NX3L2467 v.5
20120702
Product data sheet
-
NX3L2467 v.4
NX3L2467 v.4
20111108
Product data sheet
-
NX3L2467 v.3
NX3L2467 v.3
20101229
Product data sheet
-
NX3L2467 v.2
NX3L2467 v.2
20100519
Product data sheet
-
NX3L2467 v.1
NX3L2467 v.1
20090623
Product data sheet
-
-
NX3L2467
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
20 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
15 Legal information
15.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
15.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
NX3L2467
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
21 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor
tested in accordance with automotive testing or application requirements.
NXP Semiconductors accepts no liability for inclusion and/or use of nonautomotive qualified products in automotive equipment or applications. In
the event that customer uses the product for design-in and use in automotive
applications to automotive specifications and standards, customer (a) shall
use the product without NXP Semiconductors’ warranty of the product for
such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own
risk, and (c) customer fully indemnifies NXP Semiconductors for any liability,
damages or failed product claims resulting from customer design and use
of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
NX3L2467
Product data sheet
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Security — Customer understands that all NXP products may be subject
to unidentified or documented vulnerabilities. Customer is responsible
for the design and operation of its applications and products throughout
their lifecycles to reduce the effect of these vulnerabilities on customer’s
applications and products. Customer’s responsibility also extends to other
open and/or proprietary technologies supported by NXP products for use
in customer’s applications. NXP accepts no liability for any vulnerability.
Customer should regularly check security updates from NXP and follow up
appropriately. Customer shall select products with security features that best
meet rules, regulations, and standards of the intended application and make
the ultimate design decisions regarding its products and is solely responsible
for compliance with all legal, regulatory, and security related requirements
concerning its products, regardless of any information or support that may
be provided by NXP. NXP has a Product Security Incident Response Team
(PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation,
reporting, and solution release to security vulnerabilities of NXP products.
15.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
22 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Ordering information ..........................................2
Ordering options ................................................2
Pin description ...................................................4
Function table ....................................................4
Limiting values .................................................. 4
Recommended operating conditions ................. 5
Static characteristics ......................................... 6
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
ON resistance ................................................... 7
Dynamic characteristics .................................. 10
Measurement points ........................................11
Test data ..........................................................12
Additional dynamic characteristics .................. 13
Abbreviations ...................................................20
Revision history ...............................................20
Fig. 15.
ON resistance as a function of input
voltage; VCC = 4.3 V ...................................... 10
Enable and disable times ................................11
Test circuit for measuring break-beforemake timing .....................................................12
Test circuit for measuring switching times ....... 12
Test circuit for measuring total harmonic
distortion .......................................................... 14
Test circuit for measuring the frequency
response when channel is in ON-state ............14
Test circuit for measuring isolation (OFFstate) ................................................................14
Test circuit for measuring crosstalk voltage
between digital inputs and switch ....................15
Test circuit for measuring crosstalk
between switches ............................................ 15
Test circuit for measuring charge injection .......16
Package outline SOT1039-2 (HXQFN16) ........17
Package outline SOT403-1 (TSSOP16) ..........18
Package outline SOT1161-1 (XQFN16) .......... 19
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Logic symbol ..................................................... 3
Logic diagram ....................................................3
Pin configuration SOT403-1 (TSSOP16) ...........3
Pin configuration SOT1039-2 (HXQFN16) ........ 3
Pin configuration SOT1161-1 (XQFN16) ........... 4
Test circuit for measuring OFF-state
leakage current ................................................. 7
Test circuit for measuring ON-state leakage
current ............................................................... 7
Test circuit for measuring ON resistance ...........8
Typical ON resistance as a function of input
voltage ............................................................... 8
ON resistance as a function of input
voltage; VCC = 1.5 V ........................................9
ON resistance as a function of input
voltage; VCC = 1.8 V ........................................9
ON resistance as a function of input
voltage; VCC = 2.5 V ........................................9
ON resistance as a function of input
voltage; VCC = 2.7 V ........................................9
ON resistance as a function of input
voltage; VCC = 3.3 V ...................................... 10
NX3L2467
Product data sheet
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
All information provided in this document is subject to legal disclaimers.
Rev. 5.1 — 18 May 2021
© NXP B.V. 2021. All rights reserved.
23 / 24
NX3L2467
NXP Semiconductors
Dual low-ohmic double-pole double-throw analog switch
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
8
9
10
10.1
10.2
10.3
11
11.1
11.2
11.3
12
13
14
15
General description ............................................ 1
Features and benefits .........................................1
Applications .........................................................2
Ordering information .......................................... 2
Ordering options ................................................ 2
Functional diagram ............................................. 3
Pinning information ............................................ 3
Pinning ............................................................... 3
Pin description ................................................... 4
Functional description ........................................4
Limiting values .................................................... 4
Recommended operating conditions ................ 5
Static characteristics .......................................... 6
Test circuits ........................................................7
ON resistance ....................................................7
ON resistance test circuit and graphs ................8
Dynamic characteristics ...................................10
Waveform and test circuits .............................. 11
Additional dynamic characteristics ...................13
Test circuits ......................................................14
Package outline .................................................17
Abbreviations .................................................... 20
Revision history ................................................ 20
Legal information .............................................. 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 18 May 2021
Document identifier: NX3L2467
工商网监
湘ICP备2023018690号
