NX3L2G384GT,115

NX3L2G384 Dual low-ohmic single-pole single-throw analog switch Rev. 7 — 26 March 2013 Product data sheet 1. General description The NX3L2G384 is a dual low-ohmic single-pole single-throw analog switch. Each switch has two input/output terminals (nY and nZ) and an active LOW enable input (nE). When pin nE is HIGH, the analog switch is turned off. Schmitt trigger action at the enable input (nE) makes the circuit tolerant to slower input rise and fall times. The NX3L2G384 allows signals with amplitude up to VCC to be transmitted from nY to nZ; or from nZ to nY. Its low ON resistance (0.5 ) and flatness (0.13 ) ensures minimal attenuation and distortion of transmitted signals. 2. Features and benefits  Wide supply voltage range from 1.4 V to 4.3 V  Very low ON resistance (peak):  1.6  (typical) at VCC = 1.4 V  1.0  (typical) at VCC = 1.65 V  0.55  (typical) at VCC = 2.3 V  0.50  (typical) at VCC = 2.7 V  0.50  (typical) at VCC = 4.3 V  High noise immunity  ESD protection:  HBM JESD22-A114F Class 3A exceeds 7500 V  MM JESD22-A115-A exceeds 200 V  CDM AEC-Q100-011 revision B exceeds 1000 V  IEC61000-4-2 contact discharge exceeds 4000 V for switch ports  CMOS low-power consumption  Latch-up performance exceeds 100 mA per JESD 78 Class II Level A  Direct interface with TTL levels at 3.0 V  Control input accepts voltages above the supply voltage  High current handling capability (350 mA continuous current under 3.3 V supply)  Specified from 40 C to +85 C and from 40 C to +125 C 3. Applications  Cell phone  PDA  Portable media player NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version NX3L2G384GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 1  1.95  0.5 mm SOT833-1 NX3L2G384GD 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads; 8 terminals; body 3  2  0.5 mm SOT996-2 NX3L2G384GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6  1.6  0.5 mm SOT902-2 5. Marking Table 2. Marking codes[1] Type number Marking code NX3L2G384GT ML2 NX3L2G384GD ML2 NX3L2G384GM ML2 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram 1Y 1Z 1E 2Z 2Y Y 2E E 001aai598 001aai828 Fig 1. Logic symbol NX3L2G384 Product data sheet Z Fig 2. Logic diagram (one switch) All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 2 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 7. Pinning information 7.1 Pinning NX3L2G384 1Y 1 8 VCC 1Z 2 7 1E 2E 3 6 2Z GND 4 5 NX3L2G384 2Y 1Y 1 8 VCC 1Z 2 7 1E 2E 3 6 2Z GND 4 5 2Y 001aai831 001aaj531 Transparent top view Transparent top view Fig 3. Pin configuration SOT833-1 (XSON8) Fig 4. Pin configuration SOT996-2 (XSON8) NX3L2G384 1E 1 2Z 2Y 8 VCC terminal 1 index area 1Y 2 6 1Z 3 5 2E GND 4 7 001aai830 Transparent top view Fig 5. Pin configuration SOT902-2 (XQFN8) NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 3 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 7.2 Pin description Table 3. Symbol Pin description Pin Description SOT833-1 and SOT996-2 SOT902-2 1Y, 2Y 1, 5 7, 3 independent input or output 1Z, 2Z 2, 6 6, 2 independent input or output GND 4 4 ground (0 V) 1E, 2E 7, 3 1, 5 enable input (active LOW) VCC 8 8 supply voltage 8. Functional description Table 4. Function table[1] Input nE Switch L ON-state H OFF-state [1] H = HIGH voltage level; L = LOW voltage level. 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Max Unit 0.5 +4.6 V [1] 0.5 +4.6 V [2] 0.5 VCC + 0.5 V VI input voltage VSW switch voltage IIK input clamping current VI < 0.5 V 50 - mA ISK switch clamping current VI < 0.5 V or VI > VCC + 0.5 V - 50 mA ISW switch current VSW > 0.5 V or VSW < VCC + 0.5 V; source or sink current - 350 mA VSW > 0.5 V or VSW < VCC + 0.5 V; pulsed at 1 ms duration, < 10 % duty cycle; peak current - 500 mA 65 +150 C - 250 mW Tstg enable input nE Min storage temperature total power dissipation Ptot Tamb = 40 C to +125 C [3] [1] The minimum input voltage rating may be exceeded if the input current rating is observed. [2] The minimum and maximum switch voltage ratings may be exceeded if the switch clamping current rating is observed but may not exceed 4.6 V. [3] For XSON8 and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K. NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 4 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 10. Recommended operating conditions Table 6. Recommended operating conditions Symbol Parameter VCC supply voltage VI input voltage Conditions enable input nE [1] VSW switch voltage Tamb ambient temperature t/V input transition rise and fall rate [2] VCC = 1.4 V to 4.3 V Min Typ Max Unit 1.4 - 4.3 V 0 - 4.3 V 0 - VCC V 40 - +125 C - - 200 ns/V [1] To avoid sinking GND current from terminal nZ when switch current flows in terminal nY, the voltage drop across the bidirectional switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no GND current will flow from terminal nY. In this case, there is no limit for the voltage drop across the switch. [2] Applies to control signal levels. 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Tamb = 25 C Conditions Min VIH VIL HIGH-level input voltage LOW-level input voltage Min Max Max (85 C) (125 C) VCC = 1.4 V to 1.95 V 0.65VCC - - 0.65VCC - - V 1.7 - - 1.7 - - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - - V VCC = 3.6 V to 4.3 V 0.7VCC - - 0.7VCC - - V VCC = 1.4 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 0.8 V VCC = 3.6 V to 4.3 V - - 0.3VCC - 0.3VCC - - - - 0.5 1 A VCC = 1.4 V to 3.6 V - - 5 - 50 500 nA VCC = 3.6 V to 4.3 V - - 10 - 50 500 nA VCC = 1.4 V to 3.6 V - - 5 - 50 500 nA VCC = 3.6 V to 4.3 V - - 10 - 50 500 nA VCC = 3.6 V - - 100 - 690 6000 nA VCC = 4.3 V - - 150 - 800 7000 nA input leakage current enable input nE; VI = GND to 4.3 V; VCC = 1.4 V to 4.3 V IS(OFF) OFF-state leakage current nY port; see Figure 6 ON-state leakage current nZ port; see Figure 7 ICC Max Unit VCC = 2.3 V to 2.7 V II IS(ON) Typ Tamb = 40 C to +125 C 0.35VCC 0.35VCC V 0.3VCC V supply current VI = VCC or GND; VSW = GND or VCC NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 5 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch Table 7. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Tamb = 25 C Conditions Tamb = 40 C to +125 C Min Typ Max Min Unit Max Max (85 C) (125 C) CI input capacitance - 1.0 - - - - pF CS(OFF) OFF-state capacitance - 35 - - - - pF CS(ON) ON-state capacitance - 110 - - - - pF 11.1 Test circuits VCC VCC nE VIH nZ VI nE VIL nY IS IS GND nZ nY GND VI VO VO 001aaj519 001aaj520 VI = 0.3 V or VCC  0.3 V; VO = VCC  0.3 V or 0.3 V. Fig 6. Test circuit for measuring OFF-state leakage current VI = 0.3 V or VCC  0.3 V; VO = open circuit. Fig 7. Test circuit for measuring ON-state leakage current 11.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15. Symbol RON(peak) Parameter ON resistance (peak) NX3L2G384 Product data sheet Tamb = 40 C to +85 C Conditions Tamb40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.4 V - 1.6 3.7 - 4.1  VCC = 1.65 V - 1.0 1.6 - 1.7  VCC = 2.3 V - 0.55 0.8 - 0.9  VCC = 2.7 V - 0.5 0.75 - 0.9  VCC = 4.3 V - 0.5 0.75 - 0.9  VI = GND to VCC; ISW = 100 mA; see Figure 8 All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 6 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch Table 8. ON resistance …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Figure 9 to Figure 15. Symbol RON Parameter Tamb = 40 C to +85 C Conditions Unit Min Typ[1] Max Min Max VCC = 1.4 V - 0.04 0.3 - 0.3  VCC = 1.65 V - 0.04 0.2 - 0.3  VCC = 2.3 V - 0.02 0.08 - 0.1  VCC = 2.7 V - 0.02 0.075 - 0.1  - 0.02 0.075 - 0.1  VCC = 1.4 V - 1.0 3.3 - 3.6  VCC = 1.65 V - 0.5 1.2 - 1.3  VCC = 2.3 V - 0.15 0.3 - 0.35  VCC = 2.7 V - 0.13 0.3 - 0.35  VCC = 4.3 V - 0.2 0.4 - 0.45  ON resistance mismatch VI = GND to VCC; between channels ISW = 100 mA [2] VCC = 4.3 V RON(flat) Tamb40 C to +125 C ON resistance (flatness) VI = GND to VCC; ISW = 100 mA [3] [1] Typical values are measured at Tamb = 25 C. [2] Measured at identical VCC, temperature and input voltage. [3] Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and temperature. NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 7 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 11.3 ON resistance test circuit and graphs 001aag564 1.6 RON (Ω) 1.2 VSW (1) V 0.8 VCC (2) (3) nE VIL (4) 0.4 nZ Vl (5) (6) nY GND ISW 0 0 1 2 RON = VSW / ISW. 3 4 5 VI (V) 001aaj521 (1) VCC = 1.5 V. (2) VCC = 1.8 V. (3) VCC = 2.5 V. (4) VCC = 2.7 V. (5) VCC = 3.3 V. (6) VCC = 4.3 V. Measured at Tamb = 25 C. Fig 8. Test circuit for measuring ON resistance NX3L2G384 Product data sheet Fig 9. Typical ON resistance as a function of input voltage All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 8 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 001aag565 1.6 001aag566 1.0 RON (Ω) RON (Ω) 0.8 1.2 (1) (2) (3) (4) 0.6 (1) (2) (3) (4) 0.8 0.4 0.4 0.2 0 0 0 1 2 3 0 1 2 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 10. ON resistance as a function of input voltage; VCC = 1.5 V 001aag567 1.0 3 VI (V) RON (Ω) Fig 11. ON resistance as a function of input voltage; VCC = 1.8 V 001aag568 1.0 RON (Ω) 0.8 0.8 0.6 0.6 (1) (2) (3) (4) 0.4 0.4 0.2 0.2 0 (1) (2) (3) (4) 0 0 1 2 3 0 VI (V) (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 12. ON resistance as a function of input voltage; VCC = 2.5 V Product data sheet 2 3 VI (V) (1) Tamb = 125 C. NX3L2G384 1 Fig 13. ON resistance as a function of input voltage; VCC = 2.7 V All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 9 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 001aag569 1.0 001aaj896 1.0 RON (Ω) RON (Ω) 0.8 0.8 0.6 0.6 (1) (2) (3) (4) 0.4 (1) (2) (3) (4) 0.4 0.2 0.2 0 0 0 1 2 3 4 0 1 2 3 4 VI (V) 5 VI (V) (1) Tamb = 125 C. (1) Tamb = 125 C. (2) Tamb = 85 C. (2) Tamb = 85 C. (3) Tamb = 25 C. (3) Tamb = 25 C. (4) Tamb = 40 C. (4) Tamb = 40 C. Fig 14. ON resistance as a function of input voltage; VCC = 3.3 V Fig 15. ON resistance as a function of input voltage; VCC = 4.3 V 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Figure 17. Symbol Parameter enable time ten disable time tdis Tamb = 25 C Conditions Unit Min Max VCC = 1.4 V to 1.6 V - 27 41 - 44 48 ns VCC = 1.65 V to 1.95 V - 23 35 - 37 40 ns VCC = 2.3 V to 2.7 V - 17 26 - 28 31 ns VCC = 2.7 V to 3.6 V - 14 24 - 25 27 ns VCC = 3.6 V to 4.3 V - 14 24 - 25 27 ns - 9 17 - 19 21 ns Min Max (85 C) Max (125 C) nE to nZ or nY; see Figure 16 nE to nZ or nY; see Figure 16 VCC = 1.4 V to 1.6 V [1] Tamb = 40 C to +125 C Typ[1] VCC = 1.65 V to 1.95 V - 7 13 - 14 15 ns VCC = 2.3 V to 2.7 V - 4 8 - 9 10 ns VCC = 2.7 V to 3.6 V - 3 7 - 8 9 ns VCC = 3.6 V to 4.3 V - 3 7 - 8 9 ns Typical values are measured at Tamb = 25 C and VCC = 1.5 V, 1.8 V, 2.5 V, 3.3 V and 4.3 V respectively. NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 10 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 12.1 Waveform and test circuits VI VM nE input VM GND ten tdis VOH nY or nZ output LOW to OFF OFF to LOW VX VX GND switch disabled switch enabled switch disabled 001aaj522 Measurement points are given in Table 10. Logic level: VOH is the typical output voltage that occurs with the output load. Fig 16. Enable and disable times Table 10. Measurement points Supply voltage Input Output VCC VM VX 1.4 V to 4.3 V 0.5VCC 0.9VOH VCC nE nY/nZ G V I V VO RL nZ/nY VEXT = 1.5 V CL 001aaj523 Test data is given in Table 11. Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. VEXT = External voltage for measuring switching times. Fig 17. Test circuit for measuring switching times Table 11. Test data Supply voltage Input VCC VI tr, tf CL RL 1.4 V to 4.3 V VCC  2.5 ns 35 pF 50  NX3L2G384 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 11 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); VI = GND or VCC (unless otherwise specified); tr = tf  2.5 ns. Tamb = 25 C Symbol Parameter Conditions THD fi = 20 Hz to 20 kHz; RL = 32 ; see Figure 18 total harmonic distortion Min Typ Max VCC = 1.4 V; VI = 1 V (p-p) - 0.15 - % VCC = 1.65 V; VI = 1.2 V (p-p) - 0.10 - % [1] VCC = 2.3 V; VI = 1.5 V (p-p) - 0.02 - % VCC = 2.7 V; VI = 2 V (p-p) - 0.02 - % - 0.02 - % - 60 - MHz - 90 - dB - 0.2 - V - 0.2 - V - 90 - dB VCC = 1.5 V - 3 - pC VCC = 1.8 V - 3 - pC VCC = 2.5 V - 3 - pC VCC = 3.3 V - 3 - pC VCC = 4.3 V - 6 - pC VCC = 4.3 V; VI = 2 V (p-p) f(3dB) 3 dB frequency response RL = 50 ; see Figure 19 iso isolation (OFF-state) fi = 100 kHz; RL = 50 ; see Figure 20 [1] VCC = 1.4 V to 4.3 V [1] VCC = 1.4 V to 4.3 V crosstalk voltage Vct between digital inputs and switch; fi = 1 MHz; CL = 50 pF; RL = 50 ; see Figure 21 VCC = 1.4 V to 3.6 V VCC = 3.6 V to 4.3 V Xtalk crosstalk [1] between switches; fi = 100 kHz; RL = 50 ; see Figure 22 VCC = 1.4 V to 4.3 V charge injection Qinj [1] Unit fi = 1 MHz; CL = 0.1 nF; RL = 1 M; Vgen = 0 V; Rgen = 0 ; see Figure 23 fi is biased at 0.5VCC. 13. Test circuits VCC 0.5VCC nE VIL RL nY/nZ nZ/nY fi D 001aaj524 Fig 18. Test circuit for measuring total harmonic distortion NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 12 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch VCC 0.5VCC nE VIL RL nY/nZ nZ/nY fi dB 001aaj525 Adjust fi voltage to obtain 0 dBm level at output. Increase fi frequency until dB meter reads 3 dB. Fig 19. Test circuit for measuring the frequency response when channel is in ON-state VCC 0.5VCC RL VIH 0.5VCC nE RL nY/nZ nZ/nY fi dB 001aaj526 Adjust fi voltage to obtain 0 dBm level at input. Fig 20. Test circuit for measuring isolation (OFF-state) VCC nE nY/nZ G VI nZ/nY RL RL 0.5VCC 0.5VCC CL V VO 001aaj527 a. Test circuit logic input (nE) off on VO off Vct 001aaj528 b. Input and output pulse definitions Fig 21. Test circuit for measuring crosstalk voltage between digital inputs and switch NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 13 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 0.5VCC 1E VIL RL 1Z or 1Y 1Y or 1Z fi CHANNEL ON 50 Ω V VO1 0.5VCC 2E VIH RL 2Y or 2Z 2Z or 2Y CHANNEL OFF Ri 50 Ω V VO2 001aai832 20 log10 (VO2 / VO1) or 20 log10 (VO1 / VO2). Fig 22. Test circuit for measuring crosstalk between switches VCC nE nY/nZ G VI V VO RL nZ/nY Rgen Vgen CL GND 001aaj529 a. Test circuit logic off input (nE) on off VO VO 001aaj530 b. Input and output pulse definitions Definition: Qinj = VO  CL. VO = output voltage variation. Rgen = generator resistance. Vgen = generator voltage. Fig 23. Test circuit for measuring charge injection NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 14 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 14. Package outline XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm 1 2 SOT833-1 b 4 3 4× (2) L L1 e 8 7 6 e1 5 e1 e1 8× A (2) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max A1 max b D E e e1 L L1 mm 0.5 0.04 0.25 0.17 2.0 1.9 1.05 0.95 0.6 0.5 0.35 0.27 0.40 0.32 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT833-1 --- MO-252 --- EUROPEAN PROJECTION ISSUE DATE 07-11-14 07-12-07 Fig 24. Package outline SOT833-1 (XSON8) NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 15 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm B D SOT996-2 A E A A1 detail X terminal 1 index area e1 1 4 8 5 C C A B C v w b e L1 y y1 C L2 L X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit(1) mm max nom min A A1 b 0.05 0.35 D E 2.1 3.1 0.5 0.00 0.15 1.9 e e1 0.5 1.5 2.9 L L1 L2 0.5 0.15 0.6 0.3 0.05 0.4 v 0.1 w y 0.05 0.05 y1 0.1 sot996-2_po Outline version References IEC JEDEC JEITA European projection Issue date 07-12-21 12-11-20 SOT996-2 Fig 25. Package outline SOT996-2 (XSON8) NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 16 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch XQFN8: plastic, extremely thin quad flat package; no leads; 8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2 X A B D terminal 1 index area E A A1 detail X e v w b 4 3 C C A B C y y1 C 5 e1 2 6 1 7 terminal 1 index area 8 L metal area not for soldering L1 0 1 Dimensions Unit(1) mm max nom min 2 mm scale A 0.5 A1 b D E e e1 0.05 0.25 1.65 1.65 0.20 1.60 1.60 0.55 0.00 0.15 1.55 1.55 0.5 L L1 v 0.35 0.15 0.30 0.10 0.25 0.05 0.1 w y y1 0.05 0.05 0.05 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT902-2 --- MO-255 --- sot902-2_po European projection Issue date 10-11-02 11-03-31 Fig 26. Package outline SOT902-2 (XQFN8) NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 17 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 15. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model PDA Personal Digital Assistant TTL Transistor-Transistor Logic 16. Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes NX3L2G384 v.7 20130326 Product data sheet - NX3L2G384 v.6 Modifications: • For type number NX3L2G384GD XSON8U has changed to XSON8. NX3L2G384 v.6 20120617 Product data sheet - NX3L2G384 v.5 NX3L2G384 v.5 20111107 Product data sheet - NX3L2G384 v.4 NX3L2G384 v.4 20101228 Product data sheet - NX3L2G384 v.3 NX3L2G384 v.3 20090828 Product data sheet - NX3L2G384 v.2 NX3L2G384 v.2 20090415 Product data sheet - NX3L2G384 v.1 NX3L2G384 v.1 20080918 Product data sheet - - NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 18 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. NX3L2G384 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 19 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NX3L2G384 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 26 March 2013 © NXP B.V. 2013. All rights reserved. 20 of 21 NX3L2G384 NXP Semiconductors Dual low-ohmic single-pole single-throw analog switch 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 11.1 11.2 11.3 12 12.1 12.2 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ON resistance test circuit and graphs. . . . . . . . 8 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 Waveform and test circuits . . . . . . . . . . . . . . . 11 Additional dynamic characteristics . . . . . . . . . 12 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 26 March 2013 Document identifier: NX3L2G384