NX5DV4885E
Dual supply 1-of-2 VGA switch
Rev. 2 — 4 November 2011
Product data sheet
1. General description
The NX5DV4885E is a dual supply 1-to-2 VGA switch. It integrates high-bandwidth SPDT
switches with level translating switches and level translating buffers to provide switching
of input RGB signals and switching and level translation of input DDC signals to either of
two output channels as well as level translation of input H-sync and V-sync signals
The NX5DV4885E is characterized for operation from 40 C to +85 C.
2. Features and benefits
RGB switches:
Low ON resistance (4 typical)
Low ON capacitance (12 pF typical)
Low output skew (50 ps)
Low power consumption (< 2 A)
Level translation of sync and DDC signals
Over-voltage tolerant inputs
ESD protection:
HBM JESD22-A114F Class 3A exceeds 4 kV
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101D exceeds 1000 V
IEC61000-4-2 contact discharge exceeds 4 kV for I/Os
Latch-up performance exceeds 100 mA per JESD78 Class II Level A
Specified from 40 C to +85 C
3. Applications
Notebook Computers
Docking stations
Digital projectors
Computer monitors
Servers
Storage
NX5DV4885E
NXP Semiconductors
Dual supply 1-of-2 VGA switch
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
NX5DV4885EHF 40 C to +85 C
Description
HVQFN24
Version
plastic thermal enhanced very thin quad flat package; no SOT616-3
leads; 24 terminals; body 4 4 0.85 mm
5. Marking
Table 2.
Marking codes
Type number
Marking[1]
NX5DV4885EHF
x5E
[1]
The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
VCC(B)
R0
R1
R2
G0
G1
G2
B0
B1
B2
VCC(A)
EN
CONTROL LOGIC
SEL
SDA1
SDA0
SCL0
LEVEL
TRANSLATING
SWITCH
SCL1
SDA2
SCL2
H0
H1
LEVEL
TRANSLATOR
V0
V1
001aao279
Fig 1.
Logic symbol
NX5DV4885E
Product data sheet
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7. Pinning information
19 SCL2
20 SCL1
21 SDA2
22 SDA1
terminal 1
index area
23 EN
24 SEL
7.1 Pinning
SDA0
1
18 R1
SCL0
2
17 R2
R0
3
G0
4
B0
5
H0
6
16 G1
NX5DV4885E
15 G2
14 B1
V1 12
9
VCC(A)
13 B2
H1 11
8
GND 10
7
V0
VCC(B)
GND(1)
001aao280
Transparent top view
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 2.
Pin configuration SOT616-3 (HVQFN24)
7.2 Pin description
Table 3.
Pin description
Symbol
Pin
Description
R0, G0, B0
3, 4, 5
RGB input or output
GND
10
ground (0 V)
VCC(A)
9
supply voltage A
H0
6
horizontal sync input
V0
7
vertical sync input
EN
23
enable input (active HIGH)
SDA0
1
SDA0 input or output
SCL0
2
SCL0 input or output
SDA1, SDA2
22, 21
SDA input or output
SCL1, SCL2
20, 19
SCL input or output
VCC(B)
8
supply voltage B
V1
12
vertical sync output
H1
11
horizontal sync output
R1, G1, B1, R2, G2, B2
18, 16, 14, 17, 15, 13
RGB input or output
SEL
24
select input
NX5DV4885E
Product data sheet
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Dual supply 1-of-2 VGA switch
8. Functional description
The NX5DV4885E integrates high-bandwidth SPDT switches, level-translating buffers
and level translating SPDT switches to provide a complete solution for 1-to-2 switching of
VGA signals. An enable input (EN) is used to enable or disable the device and a select
input (SEL) is used to determine which output is selected. When EN = LOW the device is
disabled; all switches will be off and H1, V1 will be forced LOW.
8.1 RGB switches
The NX5DV4885E provides three identical single pole double throw high-bandwidth
switches to route standard VGA RGB signals (see Table 4).
Table 4.
Function table RGB
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Input
Switch
EN
SEL
H
L
R0 to R1; G0 to G1; B0 to B1
H
H
R0 to R2; G0 to G2; B0 to B2
L
X
switches Rn, Gn, Bn off
8.2 H-Sync/V-Sync level translator
The horizontal and vertical synchronization buffers have inputs (H0, V0) referenced to
VCC(A) and outputs (H1 and V1) that are referenced to VCC(B). This allows level translation
of synchronization signals from as low as 2.0 V up to 5.5 V and supports low-voltage
CMOS or TTL-compatible graphics controllers meeting the VESA specification for output
drive of 8 mA. The EN input also controls the level shifter (See Table 5).
Table 5.
Function table HV
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Input
Switch
EN
NX5DV4885E
Product data sheet
H
H1 = H0; V1 = V0
L
H1, V1 = L
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Dual supply 1-of-2 VGA switch
8.3 Display-Data Channel Multiplexer
The NX5DV4885E provides two identical SPDT active-level translating switches to route
DDC signals (See Table 6). The switch outputs are limited to a diode drop below the
voltage applied on VCC(A). To provide VESA I2C-compatible signals 3.3 V should be
applied to VCC(A). If voltage translation is not required VCC(A) should be connected to
VCC(B).
Table 6.
Function table DDC
H = HIGH voltage level; L = LOW voltage level; X = Don’t care.
Input
Switch
EN
SEL
H
L
SDA0 to SDA1, SCL0 to SCL1
H
H
SDA0 to SDA2, SCL0 to SCL2
L
X
switches SDAn, SCLn off
9. Limiting values
Table 7.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC(A)
supply voltage A
VCC(B)
supply voltage B
Conditions
Min
Max
Unit
0.5
+6
V
0.5
+6
V
input voltage
[1]
0.5
+6
V
VSW
switch voltage
[1]
0.5
+6
V
IIK
input clamping current
VI < 0.5 V
50
-
mA
ISK
switch clamping current
VI < 0.5 V
50
-
mA
IOK
output clamping current
VO < 0 V
50
-
mA
VI
IO
output current
VO = 0 V to VCC(B)
-
50
mA
ICC
supply current
ICC(A) or ICC(B)
-
100
mA
IGND
ground current
100
-
mA
ISW
switch current
VSW > 0.5 V or VSW < 6 V;
source or sink current
-
30
mA
VSW > 0.5 V or VSW < 6 V;
pulsed at 1 ms duration, < 10 % duty cycle;
peak current
-
90
mA
65
+150
C
-
300
mW
Tstg
storage temperature
Ptot
total power dissipation
Tamb = 40 C to +85 C
[1]
The minimum input voltage rating may be exceeded if the input current rating is observed.
[2]
For HVQFN24 package: above 134.5C the value of Ptot derates linearly with 19.3 mW/K.
NX5DV4885E
Product data sheet
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Rev. 2 — 4 November 2011
[2]
© NXP B.V. 2011. All rights reserved.
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Dual supply 1-of-2 VGA switch
10. Recommended operating conditions
Table 8.
Recommended operating conditions
Symbol
Parameter
VCC(A)
VCC(B)
Conditions
Min
Typ
Max
Unit
supply voltage A
2
3.3
5.5
V
supply voltage B
4.5
5.0
5.5
V
Tamb
ambient temperature
operating in free-air
40
+25
+85
C
t/V
input transition rise and fall rate
VCC(A) = 2.3 V to 2.7 V
[1]
-
20
-
ns/V
VCC(A) = 3 V to 3.6 V
[1]
-
10
-
ns/V
VCC(A) = 4.5 V to 5.5 V
[1]
-
5
-
ns/V
[1]
Applies to control signal levels.
11. Static characteristics
Table 9.
Static characteristics
VCC(B) = 4.5 V to 5.5 V; VCC(A) = 2 V to 5.5 V, unless otherwise specified; Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
Tamb = 40 C to +85 C
Conditions
Min
Typ[1]
Max
Unit
General
ICC(A)
supply current A
VCC(A) = 3.3 V; EN = VCC(A) or GND;
for H1, V1: IO = 0 A
-
-
2.0
A
ICC(B)
supply current B
VCC(B) = 5.0 V; EN = VCC(A) or GND;
for H1, V1: IO = 0 A
-
-
2.0
A
VIH
HIGH-level input voltage
VCC(A) = 3 V to 3.6 V
2
-
-
V
VIL
LOW-level input voltage
VCC(A) = 3 V to 3.6 V
-
-
0.8
V
VH
hysteresis voltage
-
50
-
mV
II
input leakage current
-
-
1
A
VOH
HIGH-level output voltage IO = 8 mA
VCC(B)
0.5
-
-
V
VOL
LOW-level output voltage IO = 8 mA
-
-
0.5
V
IOFF
power-off leakage current VI or VO = 0 V to 5.5 V; VCC(B) = 0 V;
VCC(A) = 0 V to 5.5 V
-
-
1
A
HV buffer
VCC(B) = VCC(A) = 5.5 V;
VI = GND to VCC(A)
RGB switches
IS(OFF)
OFF-state leakage
current
VCC(B) = 5.5 V; VI = 0.3 V or 5.5 V;
VO = 0 V to VCC(B); EN = VCC(A) or GND;
See Figure 3
-
-
1
A
IS(ON)
ON-state leakage current
VCC(B) = 5.5 V; VI = 0.3 V or 5.5 V;
VO = 0 V to VCC(B); EN = VCC(A);
See Figure 4
-
-
1
A
RON
ON resistance
VI = 0.7 V; ISW = 10 mA; See Figure 5
and Figure 6
[4]
-
4
-
RON
ON resistance mismatch
between channels
VI = GND to 0.7 V; ISW = 10 mA
[2]
-
0.5
-
RON(flat)
ON resistance (flatness)
VI = GND to 0.7 V; ISW = 10 mA
[3]
-
0.5
-
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Product data sheet
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Dual supply 1-of-2 VGA switch
Table 9.
Static characteristics …continued
VCC(B) = 4.5 V to 5.5 V; VCC(A) = 2 V to 5.5 V, unless otherwise specified; Voltages are referenced to GND (ground = 0 V)
Symbol
Parameter
Tamb = 40 C to +85 C
Conditions
Min
Typ[1]
Max
Unit
CS(OFF)
OFF-state capacitance
-
4.5
-
pF
CS(ON)
ON-state capacitance
-
12
-
pF
-
-
1
A
-
9
-
-
15
-
pF
VCC(A) = 2.3 V to 2.7 V
1.7
-
V
VCC(A) = 3.0 V to 3.6 V
2.0
-
V
SDA, SCL
IS(OFF)
OFF-state leakage
current
VCC(B) = 5.5 V; VCC(A) = 3.6 V; SCL0,
SDA0, SCL1, SCL2, SDA1, SDA2 =
VCC(A) or GND; VO = 0 V to VCC(B);
EN = GND; See Figure 3
RON
ON resistance
VCC(A) = 2 V; VI = 0.4 V; ISW = 2 mA;
See Figure 5 and Figure 7
CS(ON)
ON-state capacitance
[5]
Control Logic (SEL, EN)
HIGH-level input voltage
VIH
LOW-level input voltage
VIL
VH
hysteresis voltage
II
input leakage current
VCC(A) = 4.5 V to 5.5 V
0.7VCC(A)
-
VCC(A) = 2.3 V to 2.7 V
-
-
0.7
V
VCC(A) = 3.0 V to 3.6 V
-
-
0.8
V
VCC(A) = 4.5 V to 5.5 V
-
-
0.3VCC(A)
V
-
50
-
mV
-
-
1
A
VCC(A) = 5.5 V; VI = GND to VCC(A)
[1]
All typical values are measured at VCC(B) = 5 V, VCC(A) = 3.3 V and Tamb = 25 C unless otherwise specified.
V
[2]
Measured at identical VCC, temperature and input voltage.
[3]
Flatness is defined as the difference between the maximum and minimum value of ON resistance measured at identical VCC and
temperature.
[4]
Guarantees the LOW level.
[5]
Guarantees the HIGH level.
11.1 Test circuits and waveforms
VCC(A)
VIH or VIL
VCC(B)
SEL
x1
1
x0
x2
2
switch
switch
SEL
1
VIH
2
VIL
IS
EN
GND
VIH or VIL
VI
VO
001aan176
x0 refers to R0, G0, B0, SCL0 or SDA0
x1 refers to R1, G1, B1, SCL1 or SDA1
x2 refers to R2, G2, B2, SCL2 or SDA2
Fig 3.
Test circuit for measuring OFF-state leakage current
NX5DV4885E
Product data sheet
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Dual supply 1-of-2 VGA switch
VCC(A)
VIH or VIL
IS
VCC(B)
SEL
x1
1
x0
x2
2
switch
SEL
1
VIH
2
VIL
switch
EN
GND
VIH or VIL
VI
VO
001aan177
x0 refers to R0, G0, B0, SCL0 or SDA0
x1 refers to R1, G1, B1, SCL1 or SDA1
x2 refers to R2, G2, B2, SCL2 or SDA2
Fig 4.
Test circuit for measuring ON-state leakage current
VCC(A)
VIL or VIH
V
VCC(B)
VSW
SEL
x1
1
x0
x2
2
switch
SEL
EN
1
VIL
VIH
2
VIH
VIH
switch
EN
GND
VIH
VI
ISW
001aan175
x0 refers to R0, G0, B0, SCL0 or SDA0
x1 refers to R1, G1, B1, SCL1 or SDA1
x2 refers to R2, G2, B2, SCL2 or SDA2
RON = VSW / ISW.
Fig 5.
Test circuit for measuring ON resistance
NX5DV4885E
Product data sheet
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Dual supply 1-of-2 VGA switch
001aan178
10
RON
(Ω)
8
6
(1)
(2)
4
(3)
2
0
0
0.2
0.4
0.6
0.8
1.0
VI (V)
(1) Tamb = 85 C
(2) Tamb = 25 C
(3) Tamb = 40C
Fig 6.
ON resistance as a function of input voltage (RGB switches)
001aan179
60
VCC(A) = 3.3 V
RON
(Ω)
VCC(A) = 5.0 V
45
30
(1)
(2)
(3)
(1)
(2)
(3)
15
0
0
1
2
3
4
VI (V)
(1) Tamb = 85 C
(2) Tamb = 25 C
(3) Tamb = 40C
Fig 7.
ON resistance as a function of input voltage (DDC switches)
NX5DV4885E
Product data sheet
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Dual supply 1-of-2 VGA switch
12. Dynamic characteristics
Table 10. Dynamic characteristics
At recommended operating conditions; Voltages are referenced to GND (ground = 0 V; VCC(B) = 4.5 V to 5.5 V;
VCC(A) = 2 V to 5.5 V.
Symbol
Parameter
Tamb = 40 C to +85 C
Conditions
Unit
Min
Typ[1]
Max
-
3
-
ns
[2]
tpd
propagation delay
H0 to H1 and V0 to V1; See Figure 8
and Figure 9
ten
enable time
EN and SEL to all other outputs;
See Figure 10 and Figure 11
-
15
-
ns
tdis
disable time
EN and SEL to all other outputs;
See Figure 10 and Figure 11
-
5
-
ns
tb-m
break-before-make
time
See Figure 12
-
10
-
ns
tsk(o)
output skew time
Skew between any Rn, Gn and Bn
ports; see Figure 8
-
50
-
ps
[1]
[3]
All typical values are measured at VCC(B) = 5 V; VCC(A) = 3.3 V; Tamb = 25 C.
[2]
tpd is the same as tPLH and tPHL.
[3]
Guaranteed by design.
12.1 Test circuits and waveforms
VI
input
VM
VM
GND
tPLH
tPHL
VOH
output 1
VM
VM
VM
VM
VOL
VOH
output 2
VOL
001aan180
Measurement points are given in Table 11.
tsk(o) =tPLH1 tPLH2.
Fig 8.
Table 11.
Test circuit for measuring propagation delay times
Measurement points
Input
Output
VM
VI
VX
VM
0.5VCC(A)
GND to VCC(A)
0.9VOH
0.5VCC(B)
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Dual supply 1-of-2 VGA switch
VCC
VI
VO
G
DUT
RT
CL
RL
001aan183
Test data is given in Table 12.
Definitions:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including test jig and probe.
RL = Load resistance.
Fig 9.
Table 12.
Test circuit for measuring propagation delay times
Test data
Input
Load
tr, tf
CL
RL
2.5 ns
10 pF
1 k
VI
EN, SEL input
VM
VM
GND
ten
VOH
tdis
VX
output
OFF to HIGH
HIGH to OFF
VX
GND
tdis
VOH
output
HIGH to OFF
OFF to HIGH
ten
VX
VX
GND
001aan181
Measurement points are given in Table 11.
Logic level: VOH is typical output voltage level that occurs with the output load.
Fig 10. Enable and disable times
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Dual supply 1-of-2 VGA switch
VIH or VIL
VCC(A)
VCC(B)
SEL
x1
1
x0
x2
2
switch
EN
VI
G
V
VO
RL
CL
VEXT = 1 V
GND
001aan184
a. EN to switch outputs
VCC(A)
VCC(B)
SEL
x1
1
x0
x2
2
switch
EN
VIH
VI
G
V
VO
RL
CL
VEXT = 1 V
GND
001aan185
b. SEL to switch outputs
Test data is given in Table 13.
x0 refers to R0, G0, B0, SCL0 or SDA0
x1 refers to R1, G1, B1, SCL1 or SDA1
x2 refers to R2, G2, B2, SCL2 or SDA2
Fig 11. Test circuit for measuring enable and disable times
Table 13.
Test data
Input
Load
tr, tf
VI
CL
RL
2.5 ns
GND to VCC(A)
10 pF
100
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VCC(A)
VCC(B)
SEL
x1
x0
x2
EN
VIH
VI
G
V
VO
RL
CL
VEXT = 1 V
GND
001aan182
a. Test circuit
VI
0.5VI
0.9VO
0.9VO
VO
tb-m
001aag572
b. Input and output measurement points
Test data is given in Table 13.
x0 refers to R0, G0, B0, SCL0 or SDA0
x1 refers to R1, G1, B1, SCL1 or SDA1
x2 refers to R2, G2, B2, SCL2 or SDA2
Fig 12. Test circuit for measuring break-before-make timing
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13. Additional dynamic characteristics
Table 14. Additional dynamic characteristics
VCC(B) = 5.0 V 10 %, VCC(A) = 2 V to 5.5 V, unless otherwise specified; Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Tamb = 40 C to +85 C
Conditions
f(3dB)
3 dB frequency response
RL = 50 ; see Figure 13
ins
Insertion loss
fi = 1 MHz; RL = RS =
50 ; see Figure 13
Xtalk
crosstalk
between switches; fi = 50 MHz;
RL = 50 ; see Figure 13
[1]
Unit
Min
Typ
Max
-
850
-
MHz
-
0.6
-
dB
-
50
-
dB
[1]
[1]
fi is biased at 0.5VCC.
13.1 Test circuits
5V
10 nF
VCC(A)
VCC(B)
R0, G0, B0
GND or VCC
SEL
NETWORK
ANALYZER
VI
50 Ω
fi
NX5DV4885E
R2, G2, B2
R1, G1, B1
50 Ω
VO
measurement
50 Ω
reference
50 Ω
50 Ω
GND
001aao281
Insertion loss is measured between R0 and R1 or R2 on each switch; crosstalk is measured from one channel to the other
channel.
Fig 13. Test circuit for measuring crosstalk and insertion loss
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14. Application information
The NX5DV4885E provides the level shifting necessary to drive two standard VGA ports
from a graphic controller as low as 2.2 V. Internal buffers drive the HSYNC and VSYNC
signals to VGA standard TTL levels. The DDC multiplexer provides level shifting by
clamping signals to a diode drop below the voltage applied on VCC(A) (See figure
Figure 14). Connect VCC(A) to 3.3 V for normal operation, or to VCC(B) to disable voltage
clamping for DDC signals
+3.3 V
+5.0 V
VCC(A)
0.1 μF
3
GRAPHICS
CONTROLLER
R0, B0, G0
2
H0, V0
2
SDA0, SCL0
+3.3 V
GND or VCC
EN
SEL
VCC(B)
0.1 μF
R1, B1, G1
3
SDA1, SCL1
2
H1, V1
2
R2, B2, G2
3
SDA2, SCL2
2
2
VGA
PORT
VGA
PORT2
GND
001aao282
Fig 14. Typical operating circuit
NX5DV4885E
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 November 2011
© NXP B.V. 2011. All rights reserved.
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Dual supply 1-of-2 VGA switch
15. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT616-3
terminal 1
index area
A
A1
E
c
detail X
e1
C
1/2
e
e
7
12
y
y1 C
v M C A B
w M C
b
L
13
6
e
e2
Eh
1/2
e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.75
2.45
4.1
3.9
2.75
2.45
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT616-3
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
04-11-19
05-03-10
Fig 15. Package outline SOT616-3 (HVQFN24)
NX5DV4885E
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 November 2011
© NXP B.V. 2011. All rights reserved.
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16. Abbreviations
Table 15.
Abbreviations
Acronym
Description
CDM
Charged Device Model
DDC
Display Data Channel
ESD
ElectroStatic Discharge
HBM
Human Body Model
KVM
Keyboard Video Mouse
MM
Machine Model
RGB
Red Green Blue
SPDT
Single Pole Double Throw
TTL
Transistor-Transistor Logic
VESA
Video Electronics Standards Association
17. Revision history
Table 16.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NX5DV4885E v.2
20111104
Product data sheet
-
NX5DV4885E v.1
-
-
Modifications:
NX5DV4885E v.1
NX5DV4885E
Product data sheet
•
Legal pages updated.
20110719
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 November 2011
© NXP B.V. 2011. All rights reserved.
17 of 20
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Dual supply 1-of-2 VGA switch
18. Legal information
18.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
18.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
NX5DV4885E
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 November 2011
© NXP B.V. 2011. All rights reserved.
18 of 20
NX5DV4885E
NXP Semiconductors
Dual supply 1-of-2 VGA switch
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
19. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NX5DV4885E
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 November 2011
© NXP B.V. 2011. All rights reserved.
19 of 20
NX5DV4885E
NXP Semiconductors
Dual supply 1-of-2 VGA switch
20. Contents
1
2
3
4
5
6
7
7.1
7.2
8
8.1
8.2
8.3
9
10
11
11.1
12
12.1
13
13.1
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
RGB switches . . . . . . . . . . . . . . . . . . . . . . . . . . 4
H-Sync/V-Sync level translator . . . . . . . . . . . . . 4
Display-Data Channel Multiplexer . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Test circuits and waveforms . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . 10
Test circuits and waveforms . . . . . . . . . . . . . . 10
Additional dynamic characteristics . . . . . . . . 14
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Application information. . . . . . . . . . . . . . . . . . 15
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Contact information. . . . . . . . . . . . . . . . . . . . . 19
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 November 2011
Document identifier: NX5DV4885E
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