NX5P3001UKZ

NX5P3001 Bidirectional high-side power switch for charger and USB-OTG combined applications Rev. 1 — 11 September 2013 Product data sheet 1. General description The NX5P3001 is an advanced bidirectional power switch and ESD-protection device for combined USB-OTG and charger port applications. It includes undervoltage lockout, overvoltage lockout and overtemperature protection circuits designed to automatically isolate the power switch terminals when a fault condition occurs. The device features two power switch input/output terminals (VBUSI and VBUSO), an open-drain acknowledge output (ACK), an enable input which includes logic level translation (EN) and low capacitance Transient Voltage Suppression (TVS) type ESD-clamps for USB data and ID pins. When EN is set HIGH the device enters a low-power mode, disabling all protection circuits. When used in combined charger and USB-OTG applications the 30 V tolerant VBUSI switch terminal is used as the supply and switch input when charging, for USB-OTG the VBUSO switch terminal is used as the supply and switch input. Designed for operation from 3.2 V to 6.35 V, it is used in battery charging and power domain isolation applications to reduce power dissipation and extend battery life. 2. Features and benefits         30 V tolerant VBUSI supply pin Wide supply voltage range from 3.2 V to 6.35 V Automatic switch operation for charging within the supply range ISW maximum 3 A continuous current Low ON resistance: 62 m (typical) at a supply voltage of 5.0 V 1.8 V control logic input to open the switch Soft start turn-on slew rate Protection circuitry  Overtemperature protection  Overvoltage lockout  Undervoltage lockout  ESD protection:  HBM ANSI/ESDA/JEDEC JS-001 Class 2 exceeds 2 kV  CDM AEC standard Q100-01 (JESD22-C101E)  IEC61000-4-2 contact discharge exceeds 8 kV for pins VBUSI, D, D+ and ID  Specified from 40 C to +85 C NX5P3001 NXP Semiconductors Bidirectional power switch for charger and USB-OTG combinations 3. Applications  Smart and feature phones  Tablets, eBooks 4. Ordering information Table 1. Ordering information Type number NX5P3001UK Package Temperature range Name Description Version 40 C to +85 C wafer level chip-scale package, 12 bumps; body 1.36  1.66  0.51 mm (Backside Coating included) NX5P3001 WLCSP12 5. Marking Table 2. Marking codes Type number Marking code NX5P3001UK X05P3 6. Functional diagram (1 9%86, 9%862 ' ' ,' $& . DDD Fig 1. Logic symbol 9%86, 9%862 29/2 89/2 ' 89/2 ' (1 &21752/ ,' $&. 273 DDD Fig 2. Logic diagram (simplified schematic) NX5P3001 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2013 © NXP B.V. 2013. All rights reserved. 2 of 20 NX5P3001 NXP Semiconductors Bidirectional power switch for charger and USB-OTG combinations 7. Pinning information 7.1 Pinning 1;3 EDOO$ LQGH[DUHD   1;3    $ $ 9%86, 9%86, 9%862 % % 9%86, 9%862 9%862 & & $&. *1' (1 ' ' ' ' ,' DDD DDD 7UDQVSDUHQWWRSYLHZ Fig 3.  7UDQVSDUHQWWRSYLHZ Pin configuration WLCSP12 package Fig 4. Ball mapping for WLCSP12 7.2 Pin description Table 3. Pin description Symbol Pin Description VBUSO A3, B2, B3 VBUSO (output/input supply) VBUSI A1, A2, B1 VBUSI (input supply/output) ACK C1 acknowledge condition indicator (open-drain output) GND C2 ground (0 V) EN C3 enable input (active LOW) D- D1 ESD-protection I/O D+ D2 ESD-protection I/O ID D3 ESD-protection I/O NX5P3001 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2013 © NXP B.V. 2013. All rights reserved. 3 of 20 NX5P3001 NXP Semiconductors Bidirectional power switch for charger and USB-OTG combinations 8. Functional description Table 4. Function table[1] EN VBUSI VBUSO ACK Operation mode L < 3.2 V < 3.2 V Z undervoltage lockout; switch open L 3.2 V < VBUSI < 6.35 V < 3.2 V Z enabled; switch closed; charging mode L < 3.2 V > 3.2 V Z enabled; switch closed; OTG mode L X X 0 overtemperature protection; switch open L > 6.35 V X 0 overvoltage lockout; switch open H X X Z disable; switch open [1] H = HIGH voltage level; L = LOW voltage level, Z = high-impedance OFF-state. 8.1 EN-input A HIGH on EN disables the N-channel MOSFET and all protection circuits putting the device into a low-power mode. A LOW on EN enables the protection circuits and then the N-channel MOSFET. 8.2 Undervoltage lockout When EN is LOW and VBUSI and VBUSO < 3.2 V, the UnderVoltage LockOut (UVLO) circuits disable the N-channel MOSFET. Once VBUSI or VBUSO > 3.3 V and no other protection circuits are active, the state of the N-channel MOSFET is controlled by the EN pin. 8.3 Overvoltage lockout When EN is LOW and VBUSI > 6.35 V, the OverVoltage LockOut (OVLO) circuit disables the N-channel MOSFET and sets the ACK output LOW. Once VBUSI < 6.25 V and no other protection circuits are active, ACK is set high impedance and the state of the N-channel MOSFET is controlled by the EN pin. 8.4 Overtemperature protection When EN is LOW and the device temperature exceeds 125 C the overtemperature protection (OTP) circuit disables the N-channel MOSFET and set the ACK output LOW. Once the device temperature decreases to below 115 C and no other protection circuits are active, ACK is set high impedance and the state of the N-channel MOSFET is controlled by the EN pin. 8.5 ACK output The ACK output is an open-drain output that requires an external pull-up resistor. If OVLO or OTP circuits are activated the ACK output is set LOW to indicate that a fault has occurred. The ACK output will return to high impedance state automatically once the fault condition is removed or EN is HIGH. NX5P3001 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 September 2013 © NXP B.V. 2013. All rights reserved. 4 of 20 NX5P3001 NXP Semiconductors Bidirectional power switch for charger and USB-OTG combinations 9. Application diagram The NX5P3001 typically connects a USB port in a portable, battery operated device. The ACK signal requires an additional external pull-up resistor which should be connected to a supply voltage matching the logic input pin supply level it is connected to. 99IURPV\VWHP9%862 9%86 86% 3257 $&. WRSURFHVVRU (1 IURPSURFHVVRU 1;3 9%86, ' 9%862 ' %$77(5