OM10088

PCF8562 Universal LCD driver for low multiplex rates Rev. 8 — 27 September 2021 1 Product data sheet General description The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal 1 Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments. The PCF8562 is compatible with most microcontrollers and communicates via the two-line 2 bidirectional I C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). 2 Features and benefits • • • • • • • • • • • • • • • • • AEC-Q100 compliant (PCF8562TT/S400/2) for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing 1 1 Selectable display bias configuration: static, ⁄2, or ⁄3 Internal LCD bias generation with voltage-follower buffers 32 segment drives: – Up to sixteen 7-segment numeric characters – Up to eight 14-segment alphanumeric characters – Any graphics of up to 128 elements 32 × 4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide logic LCD supply range: – From 2.5 V for low-threshold LCDs – Up to 6.5 V for guest-host LCDs and high-threshold twisted nematic LCDs Low power consumption 2 400 kHz I C-bus interface No external components required Manufactured in silicon gate CMOS process 1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17. PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 3 Ordering information Table 1. Ordering information Type number Topside mark Package [1] Name Description Version PCF8562TT/2 PCF8562TT TSSOP48 plastic thin shrink small outline package, 48 leads; body width 6.1 mm SOT362-1 PCF8562TT/ [2] S400/2 PCF8562TT/ S400 TSSOP48 plastic thin shrink small outline package, 48 leads; body width 6.1 mm SOT362-1 [1] [2] Not to be used for new designs. Replacement part is PCF85162T/1 for industrial applications. Not to be used for new designs. Replacement part is PCF85162T/Q900/1 for automotive applications. 3.1 Ordering options Table 2. Ordering options Type number Orderable part number PCF8562TT/2 PCF8562TT/2,118 [2] PCF8562TT/2,518 PCF8562TT/S400/2 Packing method TSSOP48 PCF8562TT/S400/2,1 [3] [1] Minimum order quantity Temperature reel 13 inch q1 non dry pack reel 13 inch q1 dry pack 2000 Tamb = -40 °C to +85 °C 2000 Tamb = -40 °C to +85 °C TSSOP48 reel 13 inch q1 non dry pack 2000 Tamb = -40 °C to +85 °C TSSOP48 reel 13 inch q1 dry pack 2000 Tamb = -40 °C to +85 °C TSSOP48 PCF8562TT/S400/2,5 [1] [2] [3] Package Standard packing quantities and other packaging data are available at www.nxp.com/packages/. Discontinuation Notice 202107021DN - drop in replacement is PCF8562TT/2,518 - this is documented in PCN202102010F01. Discontinuation Notice 202107021DN - drop in replacement is PCF8562TT/S400/2,5 - this is documented in PCN202102010F01. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 2 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 4 Block diagram BP0 BP2 BP1 BP3 22 VLCD 21 23 24 S0 to S31 26 to 48, 1 to 9 25 BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER LCD VOLTAGE SELECTOR VSS CLK SYNC OSC VDD SCL SDA 20 13 12 15 CLOCK SELECT AND TIMING BLINKER TIMEBASE OSCILLATOR POWER-ON RESET 14 11 10 INPUT FILTERS OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROLLER LCD BIAS GENERATOR PCF8562 COMMAND DECODER DISPLAY RAM WRITE DATA CONTROL I2C-BUS CONTROLLER DATA POINTER AND AUTO INCREMENT SUBADDRESS COUNTER 16 19 SA0 A0 17 A1 18 A2 001aac262 Figure 1. Block diagram of PCF8562 PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 3 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 5 Pinning information 5.1 Pinning S23 1 48 S22 S24 2 47 S21 S25 3 46 S20 S26 4 45 S19 S27 5 44 S18 S28 6 43 S17 S29 7 42 S16 S30 8 41 S15 S31 9 40 S14 SDA 10 39 S13 SCL 11 38 S12 SYNC 12 CLK 13 37 S11 PCF8562TT 36 S10 VDD 14 35 S9 OSC 15 34 S8 A0 16 33 S7 A1 17 32 S6 A2 18 31 S5 SA0 19 30 S4 VSS 20 29 S3 VLCD 21 28 S2 BP0 22 27 S1 BP2 23 26 S0 BP1 24 25 BP3 001aac263 Top view. For mechanical details, see Figure 22. Figure 2. Pinning diagram for TSSOP48 (PCF8562TT) 5.2 Pin description Table 3. Pin description PCF8562 Product data sheet Symbol Pin Type Description SDA 10 input/output I C-bus serial data line SCL 11 input I C-bus serial clock SYNC 12 input/output cascade synchronization CLK 13 input/output clock line VDD 14 supply supply voltage OSC 15 input internal oscillator enable A0 to A2 16 to 18 input subaddress inputs SA0 19 input I C-bus address input VSS 20 supply ground supply voltage VLCD 21 supply LCD supply voltage All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 2 2 2 © NXP B.V. 2021. All rights reserved. 4 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 3. Pin description...continued 6 Symbol Pin Type Description BP0 to BP3 22 to 25 output LCD backplane outputs S0 to S22, S23 to S31 26 to 48, 1 to 9 output LCD segment outputs Functional description The PCF8562 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 32 segments. dot matrix 7-segment with dot 14-segment with dot and accent 013aaa312 Figure 3. Example of displays suitable for PCF8562 The possible display configurations of the PCF8562 depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 4. Table 4. Selection of possible display configurations Number of Backplanes PCF8562 Product data sheet Icons Digits/Characters 7-segment 14-segment Dot matrix/ Elements 4 128 16 8 128 dots (4 × 32) 3 96 12 6 96 dots (3 × 32) 2 64 8 4 64 dots (2 × 32) 1 32 4 2 32 dots (1 × 32) All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 5 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates VDD R≤ tr 2Cb VDD SDA 10 HOST MICROPROCESSOR/ MICROCONTROLLER SCL OSC VLCD 14 21 32 segment drives LCD PANEL PCF8562 11 4 backplanes 15 16 A0 17 18 A1 A2 19 (up to 128 elements) 20 SA0 VSS 001aac264 VSS The resistance of the power lines must be kept to a minimum. Figure 4. Typical system configuration 2 The host microcontroller maintains the 2-line I C-bus communication channel with the PCF8562. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS, and VLCD) and the LCD panel chosen for the application. 6.1 Power-On Reset (POR) At power-on the PCF8562 resets to the following starting conditions: • • • • • • • All backplane and segment outputs are set to VLCD 1 The selected drive mode is: 1:4 multiplex with ⁄3 bias Blinking is switched off Input and output bank selectors are reset 2 The I C-bus interface is initialized The data pointer and the subaddress counter are cleared (set to logic 0) Display is disabled 2 Remark: Do not transfer data on the I C-bus for at least 1 ms after a power-on to allow the reset action to complete. 6.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of three impedances connected in series between VLCD and VSS. The center impedance 1 is bypassed by switch if the ⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is selected. The LCD voltage can be temperature compensated externally, using the supply to pin VLCD. 6.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 5. Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 6 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 5. Biasing characteristics LCD drive mode Number of: static 1 Backplanes Levels 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 LCD bias configuration 2 static 0 1 ∞ 3 1 0.354 0.791 2.236 4 1 0.333 0.745 2.236 4 1 0.333 0.638 1.915 4 1 0.333 0.577 1.732 ⁄2 ⁄3 ⁄3 ⁄3 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth(off). 1 Multiplex drive modes of 1:3 and 1:4 with ⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. Bias is calculated by , where the values for a are 1 a = 1 for ⁄2 bias 1 a = 2 for ⁄3 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: (1) where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: (2) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: (3) 1 Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with ⁄2 bias 1 is and the discrimination for an LCD drive mode of 1:4 multiplex with ⁄2 bias is . The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • • PCF8562 Product data sheet 1 1:3 multiplex ( ⁄2 bias): 1 1:4 multiplex ( ⁄2 bias): All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 7 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 1 These compare with when ⁄3 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. 6.3.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see Figure 5. For a good contrast performance, the following rules should be followed: (4) (5) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module manufacturer. It is important to match the module properties to those of the driver in order to achieve optimum performance. 100 % Relative Transmission 90 % 10 % Vth(off) OFF SEGMENT Vth(on) GREY SEGMENT VRMS [V] ON SEGMENT 013aaa494 Figure 5. Electro-optical characteristic: relative transmission curve of the liquid 6.4 LCD drive mode waveforms 6.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in Figure 6. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 8 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V - VLCD VLCD state 2 0V - VLCD (b) Resultant waveforms at LCD segment. 013aaa207 Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) - VBP0(t). Voff(RMS) = 0 V. Figure 6. Static drive mode waveforms 6.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The 1 1 PCF8562 allows the use of ⁄2 bias or ⁄3 bias in this mode as shown in Figure 7 and Figure 8. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 9 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V - VLCD/2 - VLCD VLCD VLCD/2 state 2 0V - VLCD/2 - VLCD (b) Resultant waveforms at LCD segment. Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.354VLCD. 013aaa208 1 Figure 7. Waveforms for the 1:2 multiplex drive mode with ⁄2 bias PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 10 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Tfr VLCD BP0 BP1 LCD segments 2VLCD/3 VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD Sn 2VLCD/3 VLCD/3 VSS VLCD Sn+1 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 state 1 VLCD/3 0V - VLCD/3 - 2VLCD/3 - VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V - VLCD/3 - 2VLCD/3 - VLCD (b) Resultant waveforms at LCD segment. Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. 013aaa209 1 Figure 8. Waveforms for the 1:2 multiplex drive mode with ⁄3 bias 6.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 9. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 11 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates BP0 VLCD 2VLCD/3 Tfr LCD segments VLCD/3 VSS state 1 VLCD BP1 BP2 Sn Sn+1 Sn+2 state 2 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD state 1 2VLCD/3 VLCD/3 0V - VLCD/3 - 2VLCD/3 - VLCD VLCD 2VLCD/3 state 2 VLCD/3 0V - VLCD/3 - 2VLCD/3 - VLCD (b) Resultant waveforms at LCD segment. Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. 013aaa210 1 Figure 9. Waveforms for the 1:3 multiplex drive mode with ⁄3 bias 6.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as shown in Figure 10. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 12 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates BP0 VLCD 2VLCD/3 VLCD/3 VSS BP1 VLCD 2VLCD/3 VLCD/3 VSS BP2 VLCD 2VLCD/3 VLCD/3 VSS BP3 VLCD 2VLCD/3 VLCD/3 VSS Sn VLCD 2VLCD/3 VLCD/3 VSS Sn+1 VLCD 2VLCD/3 VLCD/3 VSS Sn+2 VLCD 2VLCD/3 VLCD/3 VSS Sn+3 VLCD 2VLCD/3 VLCD/3 VSS state 1 VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD state 2 VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD Tfr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms at LCD segment. Vstate1(t) = VSn(t) - VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) - VBP1(t). Voff(RMS) = 0.333VLCD. 013aaa211 1 Figure 10. Waveforms for the 1:4 multiplex drive mode with ⁄3 bias PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 13 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 6.5 Oscillator 6.5.1 Internal clock The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. 6.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fclk). Remark: A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 6.6 Timing The PCF8562 timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock: . 6.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. 6.8 Segment outputs The LCD drive section includes 32 segment outputs S0 to S31 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 32 segment outputs are required, the unused segment outputs should be left open-circuit. 6.9 Backplane outputs The LCD drive section includes four backplane outputs BP0 to BP3 which must be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. • In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. • In the 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 carry the same signals and may also be paired to increase the drive capabilities. • In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 14 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 6.10 Display RAM The display RAM is a static 32 × 4-bit RAM which stores LCD data. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements • the RAM columns and the segment outputs • the RAM rows and the backplane outputs. A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element; similarly, a logic 0 indicates the off-state. The display RAM bit map Figure 11 shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 31 which correspond with the segment outputs S0 to S31. In multiplexed LCD applications the segment data of the first, second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. columns display RAM addresses/segment outputs (S) rows 0 1 2 3 4 27 28 29 30 31 0 display RAM rows/ 1 backplane outputs (BP) 2 3 001aac265 The display RAM bit map shows the direct relationship between the display RAM addresses and the segment outputs and between the bits in a RAM word and the backplane outputs. Figure 11. Display RAM bit map When display data is transmitted to the PCF8562, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and depending on the current multiplex drive mode the bits are stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 7segment numeric display showing all drive modes is given in Figure 12; the RAM filling organization depicted applies equally to other LCD types. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 15 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates drive mode LCD segments Sn+2 static Sn+3 a multiplex e c Sn Sn+1 BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 DP b f e Sn+2 BP1 c DP d Sn+1 b f Sn BP1 c a b BP0 g e BP1 c d n+4 n+5 n+6 n+7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x MSB LSB c b a f g e d DP rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n n+1 n+2 n+3 a b x x f g x x e c x x d DP x x MSB a b LSB f g e c d DP n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2 c 3 x n+1 n+2 a d g x f e x x MSB LSB b DP c a d g f e columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 f Sn+1 BP2 DP d multiplex n+3 columns display RAM address/segment outputs (s) byte1 byte2 byte3 g Sn n+2 BP0 a e n+1 columns display RAM address/segment outputs (s) byte1 byte2 g Sn+2 transmitted display byte n BP0 a multiplex 1:4 Sn+1 Sn Sn+7 d Sn+3 1:3 b g Sn+6 1:2 display RAM filling order columns display RAM address/segment outputs (s) byte1 f Sn+4 Sn+5 LCD backplanes DP BP2 n rows display RAM 0 a rows/backplane 1 c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB e g d 001aaj646 x = data bit unchanged. 2 Figure 12. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I C-bus PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 16 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates The following applies to Figure 12: • In static drive mode the eight transmitted data bits are placed in row 0 as one byte. • In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0 and 1 as two successive 4-bit RAM words. • In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is not recommended to use this bit in a display because of the difficult addressing. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overwriting adjacent data because always full bytes are transmitted (see Section 6.10.3). • In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples into row 0, 1, 2, and 3 as two successive 4-bit RAM words. 6.10.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 12). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 12. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: • • • • In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two 2 If an I C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer should be re-written prior to further RAM accesses. 6.10.2 Subaddress counter The storage of display data is determined by the content of the subaddress counter. Storage is allowed to take place only when the content of the subaddress counter matches with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined by the device-select command (see Table 13). If the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The hardware subaddress must not be changed while the device is being accessed on 2 the I C-bus interface. 6.10.3 RAM writing in 1:3 multiplex drive mode In 1:3 multiplex drive mode, the RAM is written as shown in Table 6 (see Figure 12 as well). PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 17 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 6. Standard RAM filling in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display. Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 3 4 5 6 7 8 9 : 0 a7 a4 a1 b7 b4 b1 c7 c4 c1 d7 : 1 a6 a3 a0 b6 b3 b0 c6 c3 c0 d6 : 2 a5 a2 - b5 b2 - c5 c2 - d5 : 3 - - - - - - - - - - : If the bit at position BP2/S2 would be written by a second byte transmitted, then the mapping of the segment bits would change as illustrated in Table 7. Table 7. Entire RAM filling by rewriting in 1:3 multiplex drive mode Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display. Display RAM bits (rows)/ backplane outputs (BPn) Display RAM addresses (columns)/segment outputs (Sn) 0 1 2 0 a7 a4 a1/b7 b4 b1/c7 c4 c1/d7 d4 d1/e7 e4 : 1 a6 a3 a0/b6 b3 b0/c6 c3 c0/d6 d3 d0/e6 e3 : 2 a5 a2 b5 b2 c5 c2 d5 d2 e5 e2 : 3 - - - - - - - - - - : 3 4 5 6 7 8 9 : In the case described in Table 7 the RAM has to be written entirely and BP2/S2, BP2/S5, BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a combination of writing and rewriting the RAM like follows: • In the first write to the RAM, bits a7 to a0 are written. • In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and b6. • In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6. Depending on the method of writing to the RAM (standard or entire filling by rewriting), some elements remain unused or can be used, but it has to be considered in the module layout process as well as in the driver software design. 6.10.4 Output bank selector The output bank selector (see Table 14) selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the particular LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by the content of row 1, 2, and then 3 • In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially • In 1:2 multiplex mode, rows 0 and 1 are selected • In static mode, row 0 is selected PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 18 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates The PCF8562 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the content of row 2 to be selected for display instead of the content of row 0. In the 1:2 multiplex mode, the content of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is assembled. 6.10.5 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. The bank-select command (see Table 14) can be used to load display data in row 2 in static drive mode or in rows 2 and 3 in 1:2 mode. The input bank selector functions are independent of the output bank selector. 6.11 Blinking The display blinking capabilities of the PCF8562 are very versatile. The whole display can blink at frequencies selected by the blink-select command (see Table 15). The blink frequencies are fractions of the clock frequency. The ratio between the clock and blink frequencies depends on the blink mode selected (see Table 8). An additional feature is for an arbitrary selection of LCD elements to blink. This applies to the static and 1:2 multiplex drive modes and can be implemented without any communication overheads. By means of the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blink frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups of LCD elements can blink by selectively changing the display RAM data at fixed time intervals. Table 8. Blinking frequencies [1] Blink mode Normal operating mode ratio Nominal blink frequency off - blinking off 1 2 Hz 2 1 Hz 3 0.5 Hz [1] Blink modes 1, 2, and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz, and 2 Hz correspond to an oscillator frequency (fclk) of 1 536 Hz (see Section 11). The entire display can blink at a frequency other than the nominal blink frequency. This can be effectively performed by resetting and setting the display enable bit E at the required rate using the mode-set command (see Table 11). 6.12 Command decoder 2 The command decoder identifies command bytes that arrive on the I C-bus. The commands available to the PCF8562 are defined in Table 9. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 19 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 9. Definition of PCF8562 commands Command Operation code Bit 7 6 5 Reference 4 [1] 3 2 1 E B M[1:0] mode-set C 1 0 - load-data-pointer C 0 0 P[4:0] device-select C 1 1 0 0 A[2:0] bank-select C 1 1 1 1 0 I blink-select C 1 1 1 0 AB BF[1:0] [1] 0 Table 11 Table 12 Table 13 O Table 14 Table 15 Not used. All available commands carry a continuation bit C in their most significant bit position as shown in Figure 18. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data (see Table 10). Table 10. C bit description Bit Symbol 7 C Value Description continue bit 0 last control byte in the transfer; next byte will be regarded as display data 1 control bytes continue; next byte will be a command too Table 11. Mode-set command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6, 5 - 10 fixed value 4 - - unused 3 E 2 PCF8562 Product data sheet [1] 0 disabled (blank) 1 enabled [2] LCD bias configuration B 1 to 0 [1] [2] display status 0 1 ⁄3 bias 1 1 ⁄2 bias LCD drive mode selection M[1:0] 01 static; BP0 10 1:2 multiplex; BP0, BP1 11 1:3 multiplex; BP0, BP1, BP2 00 1:4 multiplex; BP0, BP1, BP2, BP3 The possibility to disable the display allows implementation of blinking under external control. Not applicable for static drive mode. All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 20 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 12. Load-data-pointer command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6, 5 - 00 fixed value 4 to 0 P[4:0] 00000 to 11111 5 bit binary value, 0 to 31; transferred to the data pointer to define one of 32 display RAM addresses Table 13. Device-select command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6 to 3 - 1100 fixed value 2 to 0 A[2:0] 000 to 111 3 bit binary value, 0 to 7; transferred to the subaddress counter to define one of eight hardware subaddresses Table 14. Bank-select command bit description Bit Symbol Value Description Static 7 C 0, 1 see Table 10 6 to 2 - 11110 fixed value 1 I 0 [1] 1:2 multiplex [1] input bank selection; storage of arriving display data 0 RAM bit 0 RAM bits 0 and 1 1 RAM bit 2 RAM bits 2 and 3 output bank selection; retrieval of LCD display data O 0 RAM bit 0 RAM bits 0 and 1 1 RAM bit 2 RAM bits 2 and 3 The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes. Table 15. Blink-select command bit description Bit Symbol Value Description 7 C 0, 1 see Table 10 6 to 3 - 1110 fixed value 2 AB 1 to 0 PCF8562 Product data sheet blink mode selection [1] 0 normal blinking 1 alternate RAM bank blinking [2] blink frequency selection BF[1:0] 00 off 01 1 All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 21 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 15. Blink-select command bit description...continued Bit [1] [2] Symbol Value Description 10 2 11 3 Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected. Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes. 6.13 Display controller The display controller executes the commands identified by the command decoder. It contains the device’s status registers and coordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. 7 2 Characteristics of the I C-bus 2 The I C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta Line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 13). SDA SCL data line stable; data valid change of data allowed mba607 Figure 13. Bit transfer 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 14). PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 22 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates SDA SDA SCL SCL S P START condition STOP condition mbc 622 Figure 14. Definition of START and STOP conditions 7.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the controller and the devices which are controlled by the controller are the targets (see Figure 15). CONTROLLER TRANSMITTER/ RECEIVER TARGET RECEIVER TARGET TRANSMITTER/ RECEIVER CONTROLLER TRANSMITTER CONTROLLER TRANSMITTER/ RECEIVER SDA SCL mga807 Figure 15. System configuration 7.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A target receiver, which is addressed, must generate an acknowledge after the reception of each byte. • A controller receiver must generate an acknowledge after the reception of each byte that has been clocked out of the target transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). • A controller receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the target. In this event, the transmitter must leave the data line HIGH to enable the controller to generate a STOP condition. 2 Acknowledgement on the I C-bus is illustrated in Figure 16. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 23 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates data output by transmitter not acknowledge data output by receiver acknowledge SCL from controller 1 2 8 9 S clock pulse for acknowledgement START condition mbc602 2 Figure 16. Acknowledgement of the I C-bus 2 7.5 I C-bus controller 2 2 The PCF8562 acts as an I C-bus target receiver. It does not initiate I C-bus transfers or 2 transmit data to an I C-bus controller receiver. The only data output from the PCF8562 are the acknowledge signals of the selected devices. Device selection depends on 2 the I C-bus target address, on the transferred command data and on the hardware subaddress. 7.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 2 7.7 I C-bus protocol 2 Two I C-bus target addresses (0111 000 and 0111 001) are reserved for the PCF8562. The least significant bit of the target address that a PCF8562 will respond to is defined by the level tied to its SA0 input. The PCF8562 is a write-only device and will not respond to a read access. 2 The I C-bus protocol is shown in Figure 17. The sequence is initiated with a START 2 condition (S) from the I C-bus controller which is followed by one of two possible PCF8562 target addresses available. All PCF8562s whose SA0 inputs correspond to bit 2 0 of the target address respond by asserting an acknowledge in parallel. This I C-bus transfer is ignored by all PCF8562s whose SA0 inputs are set to the alternative level. R/W target address S S 0 1 1 1 0 0 A 0 A C 0 1 byte acknowledge acknowledge COMMAND A n ≥ 1 byte(s) DISPLAY DATA A P n ≥ 0 byte(s) update data pointers 001aac266 2 Figure 17. I C-bus protocol PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 24 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates After an acknowledgement, one or more command bytes follow, that define the status of each addressed PCF8562. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Figure 18). The command bytes are also acknowledged by all addressed PCF8562s on the bus. MSB C LSB REST OF OPCODE msa833 Figure 18. Format of command byte After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. An acknowledgement, after each byte, is asserted only by the PCF8562s that are 2 addressed via address lines A0, A1 and A2. After the last display byte, the I C-bus controller asserts a STOP condition (P). Alternately a START may be asserted to restart 2 an I C-bus access. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 25 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 8 Internal circuitry VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1, T1 VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VLCD S0 to S31 VSS VSS 001aac269 Figure 19. Device protection circuits 9 Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 26 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit VDD supply voltage -0.5 +6.5 V VLCD LCD supply voltage -0.5 +7.5 V VI input voltage on each of the pins CLK, SDA, SCL, SYNC, SA0, OSC, A0 to A2 -0.5 +6.5 V VO output voltage on each of the pins S0 to S31, BP0 to BP3 -0.5 +7.5 V II input current -10 +10 mA IO output current -10 +10 mA IDD supply current -50 +50 mA IDD(LCD) LCD supply current -50 +50 mA ISS ground supply current -50 +50 mA Ptot total power dissipation - 400 mW Po output power - 100 mW HBM [1] - ±5 000 V MM [2] - ±200 V CDM [3] - ±1 500 V latch-up current [4] - 300 mA Tstg storage temperature [5] -65 +150 °C Tamb ambient temperature -40 +85 °C Vesd Ilu [1] [2] [3] [4] [5] electrostatic discharge voltage operating device Pass level; Human Body Model (HBM), according to [1]. Pass level; Machine Model (MM), according to [2]. Pass level; Charged-Device Model (CDM), according to [3]. Pass level; latch-up testing according to [4] at maximum ambient temperature (Tamb(max)). According to the NXP store and transport requirements (see [5]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. 10 Static characteristics Table 17. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage VLCD IDD IDD(LCD) 1.8 - 5.5 V LCD supply voltage [1] 2.5 - 6.5 V supply current fclk(ext) = 1 536 Hz [2] - 3.5 7 μA fclk(ext) = 1 536 Hz [2] - 23 32 μA 1.0 1.3 1.6 V LCD supply current [3] Logic VP(POR) power-on reset supply voltage PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 27 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 17. Static characteristics...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA VSS - 0.3VDD V VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0 to A2, SA0, SCL, SDA 0.7VDD - VDD V IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V on pins CLK and SYNC 1 - - mA on pin SDA 3 - - mA [4][5] IOH(CLK) HIGH-level output current on pin CLK output source current; VOH = 4.6 V; VDD = 5 V 1 - - mA IL leakage current VI = VDD or VSS; on pins CLK, SCL, SDA, A0 to A2 and SA0 -1 - +1 μA IL(OSC) leakage current on pin OSC VI = VDD -1 - +1 μA - - 7 pF -100 - +100 mV on pins BP0 to BP3 - 1.5 - kΩ on pins S0 to S31 - 6.0 - kΩ CI [6] input capacitance LCD outputs ΔVO output voltage variation on pins BP0 to BP3 and S0 to S31 RO output resistance VLCD = 5 V [1] [2] [3] [4] [5] [6] [7] [7] 1 VLCD > 3 V for ⁄3 bias. 2 LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I C-bus inactive. 2 The I C-bus interface of PCF8562 is 5 V tolerant. 2 When tested, I C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 16 (see Figure 19 as well). Propagation delay of driver between clock (CLK) and LCD driving signals. Periodically sampled, not 100 % tested. Outputs measured one at a time. 11 Dynamic characteristics Table 18. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1 440 1 850 2 640 Hz Clock [1] fclk(int) internal clock frequency fclk(ext) external clock frequency 960 - 2 640 Hz tclk(H) HIGH-level clock time 60 - - μs tclk(L) LOW-level clock time 60 - - μs PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 28 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 18. Dynamic characteristics...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = -40 °C to +85 °C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Synchronization tPD(SYNC_N) SYNC propagation delay - 30 - ns tSYNC_NL SYNC LOW time 1 - - μs tPD(drv) driver propagation delay - - 30 μs 2 VLCD = 5 V [2] [3] I C-bus Pin SCL fSCL SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - μs tHIGH HIGH period of the SCL clock 0.6 - - μs tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - μs tSU;STO set-up time for STOP condition 0.6 - - μs tHD;STA hold time (repeated) START condition 0.6 - - μs tSU;STA set-up time for a repeated START condition 0.6 - - μs tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 μs fSCL < 125 kHz - - 1.0 μs tf fall time of both SDA and SCL signals - - 0.3 μs Cb capacitive load for each bus line - - 400 pF tw(spike) spike pulse width - - 50 ns [1] [2] [3] 2 on the I C-bus Typical output duty factor: 50 % measured at the CLK output pin. Not tested in production. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 29 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 1/fclk tclk(H) tclk(L) 0.7VDD CLK 0.3VDD 0.7VDD SYNC 0.3VDD tPD(SYNC_N) tPD(SYNC_N) tSYNC_NL 0.5 V BP0 to BP3, and S0 to S31 (VDD = 5 V) 0.5 V tPD(drv) 013aaa493 Figure 20. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA (1) Configured as Controller when OSC is connected to VSS (2) Configured as Target when OSC is connected to VDD tSU;STO mga728 2 Figure 21. I C-bus timing waveforms 12 Application information 12.1 Multiple chip operation For large display configurations or for more segments (> 128 elements) to drive please refer to the PCF8576D device. The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 19. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 30 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Table 19. SYNC contact resistance Number of devices Maximum contact resistance 2 6 000 Ω 3 to 5 2 200 Ω 6 to 10 1 200 Ω 10 to 16 700 Ω 13 Test information 13.1 Quality information This product has been qualified in accordance with the Automotive Electronics Council (AEC) standard Q100 - Failure mechanism based stress test qualification for integrated circuits, and is suitable for use in automotive applications. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 31 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 14 Package outline TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1 D E A X c v HE y A Z 48 25 Q A2 A1 (A3) pin 1 index A θ Lp 1 L 24 bp e detail X w 0 5 mm 2.5 scale Dimensions (mm are the original dimensions) Unit mm max nom min A 1.2 A1 A2 0.15 1.05 0.05 0.85 A3 0.25 bp c D(1) E(2) 0.28 0.2 12.6 6.2 0.17 0.1 12.4 6.0 e HE 0.5 8.3 7.9 L 1 Lp Q 0.8 0.50 0.4 0.35 v w 0.25 0.08 y 0.1 Z θ 0.8 8° 0.4 0° Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. Outline version SOT362-1 References IEC JEDEC JEITA sot362-1_po European projection Issue date 03-02-19 13-08-05 MO-153 Figure 22. Package outline SOT362-1 (TSSOP48) PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 32 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 15 Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC  61340-5 or equivalent standards. 16 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 33 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 20 and Table 21 Table 20. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 21. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23. PCF8562 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 34 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17 Abbreviations Table 22. Abbreviations PCF8562 Product data sheet Acronym Description CMOS Complementary Metal Oxide Semiconductor CDM Charged-Device Model HBM Human Body Model ITO Indium Tin Oxide LCD Liquid Crystal Display LSB Least Significant Bit MM Machine Model MSB Most Significant Bit MSL Moisture Sensitivity Level PCB Printed Circuit Board RAM Random Access Memory RMS Root Mean Square SCL Serial Clock Line SDA Serial Data line SMD Surface Mount Device All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 35 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 18 References [1] [2] [3] [4] [5] PCF8562 Product data sheet JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD22-C101 Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components JESD78 IC Latch-Up Test NX3-00092 NXP store and transport requirements All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 36 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 19 Revision history Table 23. Revision history Document ID Release date Data sheet status Change notice PCF8562 v.8 Modifications: 20210927 Product data sheet PCN202102010F01 PCF8562 v.7 PCF8562 v.7 20150721 Modifications: • Table 17: Replaced values (LCD) supply PCF8562 v.6 20110616 Modifications: • Added design-in and replacement part information • Added Section 7.10.3 PCF8562 v.5 20100519 Product data sheet - PCF8562 v.4 PCF8562 v.4 20090318 Product data sheet - PCF8562 v.3 PCF8562 v.3 20081202 Product data sheet - PCF8562 v.2 PCF8562 v.2 20070122 Product data sheet - PCF8562 v,1 PCF8562 v.1 20050801 Product data sheet - - PCF8562 Product data sheet Supersedes • Updated Section 3, Ordering information. See Change notice column. • Removed Marking section (formerly Section 4). • Global: The terms "master" and "slave" changed to "controller" and "target" to comply with NXP inclusive language policy. Product data sheet Product data sheet - PCF8562 v.6 - PCF8562 v.5 All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 37 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates 20 Legal information 20.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. notice. This document supersedes and replaces all information supplied prior to the publication hereof. 20.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 20.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without PCF8562 Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Suitability for use in automotive applications — This NXP product has been qualified for use in automotive applications. If this product is used by customer in the development of, or for incorporation into, products or services (a) used in safety critical applications or (b) in which failure could lead to death, personal injury, or severe physical or environmental damage (such products and services hereinafter referred to as “Critical Applications”), All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 38 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates then customer makes the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, safety, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. As such, customer assumes all risk related to use of any products in Critical Applications and NXP and its suppliers shall not be liable for any such use by customer. Accordingly, customer will indemnify and hold NXP harmless from any claims, liabilities, damages and associated costs and expenses (including attorneys’ fees) that NXP may incur related to customer’s incorporation of any product in a Critical Application. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. PCF8562 Product data sheet Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 20.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2 I C-bus — logo is a trademark of NXP B.V. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 39 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Ordering information ..........................................2 Ordering options ................................................2 Pin description ...................................................4 Selection of possible display configurations ...... 5 Biasing characteristics .......................................7 Standard RAM filling in 1:3 multiplex drive mode ............................................................... 18 Entire RAM filling by rewriting in 1:3 multiplex drive mode ....................................... 18 Blinking frequencies ........................................ 19 Definition of PCF8562 commands ...................20 C bit description .............................................. 20 Mode-set command bit description ................. 20 Tab. 12. Tab. 13. Tab. 14. Tab. 15. Tab. 16. Tab. 17. Tab. 18. Tab. 19. Tab. 20. Tab. 21. Tab. 22. Tab. 23. Load-data-pointer command bit description .... 21 Device-select command bit description ........... 21 Bank-select command bit description ..............21 Blink-select command bit description .............. 21 Limiting values ................................................ 27 Static characteristics ....................................... 27 Dynamic characteristics .................................. 28 SYNC contact resistance ................................ 31 SnPb eutectic process (from J-STD-020D) ..... 34 Lead-free process (from J-STD-020D) ............ 34 Abbreviations ...................................................35 Revision history ...............................................37 Fig. 11. Fig. 12. Display RAM bit map ...................................... 15 Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus ................... 16 Bit transfer .......................................................22 Definition of START and STOP conditions ...... 23 System configuration .......................................23 Acknowledgement of the I2C-bus ................... 24 I2C-bus protocol .............................................. 24 Format of command byte ................................ 25 Device protection circuits ................................ 26 Driver timing waveforms ..................................30 I2C-bus timing waveforms ...............................30 Package outline SOT362-1 (TSSOP48) ..........32 Temperature profiles for large and small components ..................................................... 35 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Block diagram of PCF8562 ............................... 3 Pinning diagram for TSSOP48 (PCF8562TT) .....................................................4 Example of displays suitable for PCF8562 ........5 Typical system configuration ............................. 6 Electro-optical characteristic: relative transmission curve of the liquid .........................8 Static drive mode waveforms ............................ 9 Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias .................................................... 10 Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias .................................................... 11 Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias .................................................... 12 Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias .................................................... 13 PCF8562 Product data sheet Fig. 13. Fig. 14. Fig. 15. Fig. 16. Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 September 2021 © NXP B.V. 2021. All rights reserved. 40 / 41 PCF8562 NXP Semiconductors Universal LCD driver for low multiplex rates Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.3 6.3.1 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.5 6.5.1 6.5.2 6.6 6.7 6.8 6.9 6.10 6.10.1 6.10.2 6.10.3 6.10.4 6.10.5 6.11 6.12 6.13 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 8 9 10 11 12 12.1 13 13.1 14 15 16 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 2 Ordering options ................................................ 2 Block diagram ..................................................... 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................5 Power-On Reset (POR) .....................................6 LCD bias generator ........................................... 6 LCD voltage selector ......................................... 6 Electro-optical performance ............................... 8 LCD drive mode waveforms .............................. 8 Static drive mode ...............................................8 1:2 Multiplex drive mode ................................... 9 1:3 Multiplex drive mode ................................. 11 1:4 Multiplex drive mode ................................. 12 Oscillator .......................................................... 14 Internal clock ................................................... 14 External clock .................................................. 14 Timing .............................................................. 14 Display register ................................................ 14 Segment outputs ............................................. 14 Backplane outputs ........................................... 14 Display RAM ....................................................15 Data pointer ..................................................... 17 Subaddress counter .........................................17 RAM writing in 1:3 multiplex drive mode ..........17 Output bank selector ....................................... 18 Input bank selector .......................................... 19 Blinking ............................................................ 19 Command decoder .......................................... 19 Display controller ............................................. 22 Characteristics of the I2C-bus ......................... 22 Bit transfer ....................................................... 22 START and STOP conditions .......................... 22 System configuration ....................................... 23 Acknowledge ....................................................23 I2C-bus controller ............................................ 24 Input filters ....................................................... 24 I2C-bus protocol .............................................. 24 Internal circuitry ................................................ 26 Limiting values .................................................. 26 Static characteristics ........................................ 27 Dynamic characteristics ...................................28 Application information .................................... 30 Multiple chip operation .....................................30 Test information ................................................ 31 Quality information ...........................................31 Package outline .................................................32 Handling information ........................................ 33 Soldering of SMD packages .............................33 16.1 16.2 16.3 16.4 17 18 19 20 Introduction to soldering .................................. 33 Wave and reflow soldering .............................. 33 Wave soldering ................................................ 33 Reflow soldering .............................................. 34 Abbreviations .................................................... 35 References ......................................................... 36 Revision history ................................................ 37 Legal information .............................................. 38 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 27 September 2021 Document identifier: PCF8562