OM13069UL

LPC81xM 32-bit ARM® Cortex®-M0+ microcontroller; up to 16 kB flash and 4 kB SRAM Rev. 4.6 — 4 April 2018 Product data sheet 1. General description The LPC81xM are an ARM Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 30 MHz. The LPC81xM support up to 16 kB of flash memory and 4 kB of SRAM. The peripheral complement of the LPC81xM includes a CRC engine, one I2C-bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate timer, self wake-up timer, and state-configurable timer, one comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, and up to 18 general-purpose I/O pins. 2. Features and benefits  System:  ARM Cortex-M0+ processor, running at frequencies of up to 30 MHz with single-cycle multiplier and fast single-cycle I/O port.  ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  System tick timer.  Serial Wire Debug (SWD) and JTAG boundary scan modes supported.  Micro Trace Buffer (MTB) supported.  Memory:  Up to 16 kB on-chip flash programming memory with 64 Byte page write and erase.  Up to 4 kB SRAM.  ROM API support:  Boot loader.  USART drivers.  I2C drivers.  Power profiles.  Flash In-Application Programming (IAP) and In-System Programming (ISP).  Digital peripherals:  High-speed GPIO interface connected to the ARM Cortex-M0+ IO bus with up to 18 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, input inverter, and glitch filter.  High-current source output driver (20 mA) on four pins.  High-current sink driver (20 mA) on two true open-drain pins.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function. LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller          State Configurable Timer/PWM (SCTimer/PWM) with input and output functions (including capture and match) assigned to pins through the switch matrix.  Multiple-channel multi-rate timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self Wake-up Timer (WKT) clocked from either the IRC or a low-power, low-frequency internal oscillator.  CRC engine.  Windowed Watchdog timer (WWDT). Analog peripherals:  Comparator with internal and external voltage references with pin functions assigned or enabled through the switch matrix. Serial interfaces:  Three USART interfaces with pin functions assigned through the switch matrix.  Two SPI controllers with pin functions assigned through the switch matrix.  One I2C-bus interface with pin functions assigned through the switch matrix. Clock generation:  12 MHz internal RC oscillator trimmed to 1.5 % accuracy that can optionally be used as a system clock.  Crystal oscillator with an operating range of 1 MHz to 25 MHz.  Programmable watchdog oscillator with a frequency range of 9.4 kHz to 2.3 MHz.  10 kHz low-power oscillator for the WKT.  PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator, the external clock input CLKIN, or the internal RC oscillator.  Clock output function with divider that can reflect the crystal oscillator, the main clock, the IRC, or the watchdog oscillator. Power control:  Integrated PMU (Power Management Unit) to minimize power consumption.  Reduced power modes: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode.  Wake-up from Deep-sleep and Power-down modes on activity on USART, SPI, and I2C peripherals.  Timer-controlled self wake-up from Deep power-down mode.  Power-On Reset (POR).  Brownout detect. Unique device serial number for identification. Single power supply. Operating temperature range 40 °C to 105 °C except for the DIP8 package, which is available for a temperature range of 40 °C to 85 °C. Available as DIP8, TSSOP16, SO20, TSSOP20, and XSON16 package. 3. Applications  8/16-bit applications  Consumer  Climate control LPC81XM Product data sheet  Lighting  Motor control  Fire and security applications All information provided in this document is subject to legal disclaimers. Rev. 4.6 — 4 April 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 2 of 78 LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC810M021FN8 DIP8 plastic dual in-line package; 8 leads (300 mil) SOT097-2 LPC811M001JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101JDH16 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 LPC812M101JD20 SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 LPC812M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 LPC812M101JTB16 XSON16 plastic extremely thin small outline package; no leads; 16 terminals; body 2.5  3.2  0.5 mm SOT1341-1 4.1 Ordering options Table 2. Ordering options Type number Flash/kB SRAM/kB USART I2C-bus SPI Comparator GPIO Package LPC810M021FN8 4 1 1 6 DIP8 LPC811M001JDH16 8 2 2 1 1 1 14 TSSOP16 LPC812M101JDH16 16 4 3 1 2 1 14 TSSOP16 LPC812M101JD20 16 4 2 1 1 1 18 SO20 LPC812M101JDH20 16 4 3 1 2 1 18 TSSOP20 LPC812M101JTB16 16 4 3 1 2 1 14 XSON16 LPC81XM Product data sheet 1 2 1 All information provided in this document is subject to legal disclaimers. Rev. 4.6 — 4 April 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 3 of 78 LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 5. Marking The LPC81xM devices typically have the following top-side marking: LPC81x xxxxx xxxxxxxx xxYWWxR[x] The last two letters in the last line (field ‘xR’) identify the boot code version and device revision. Table 3. Device revision table Revision identifier (xR) Revision description ‘1A’ Initial device revision with boot code version 13.1 ‘2A’ Device revision with boot code version 13.2 ’4C’ Device revision with boot code version 13.4 Field ‘Y’ states the year the device was manufactured. Field ‘WW’ states the week the device was manufactured during that year. Remark: On the TSSOP16 package, the last line includes only the date code xxYWW. LPC81XM Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 4.6 — 4 April 2018 © NXP Semiconductors N.V. 2018. All rights reserved. 4 of 78 LPC81xM NXP Semiconductors 32-bit ARM Cortex-M0+ microcontroller 6. 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