OM15020Z

516 9 JN5169 JN IEEE802.15.4 Wireless Microcontroller Rev. 1.3 1.2 — 22 September 2017 Product data sheet 1. General description The JN5169 is an ultra low power, high performance wireless microcontroller suitable for ZigBee applications. It features 512 kB embedded Flash, 32 kB RAM and 4 kB EEPROM memory, allowing OTA upgrade capability without external memory. The 32-bit RISC processor offers high coding efficiency through variable width instructions, a multi-stage instruction pipeline and low-power operation with programmable clock speeds. It also includes a 2.4 GHz IEEE802.15.4 compliant transceiver and a comprehensive mix of analog and digital peripherals. The best in class RX operating current (down to 13 mA and with a 0.7 A sleep timer mode) gives excellent battery life allowing operation direct from a coin cell. Radio transmit power is configurable up to +10 dBm output. The peripherals support a wide range of applications. They include a 2-wire compatible I2C-bus and SPI-bus which can operate as either master or slave, a 6-channel ADC with a battery monitor and a temperature sensor. It can support a large switch matrix of up to 100 elements, or alternatively a 40-key capacitive touch pad. 2. Features and benefits 2.1 Benefits             Single chip device to run stack and application Very low current solution for long battery life; over 10 years Very low RX current for low standby power of mains powered nodes Integrated power amplifier for long range and robust communication High tolerance to interference from other 2.4 GHz radio sources Supports multiple network stacks Highly featured 32-bit RISC CPU for high performance and low power Large embedded Flash memory to enable over-the-air firmware updates without external Flash memory System BOM is low in component count and cost Flexible sensor interfacing options Very thin quad flat 6 6 mm, 40 terminal package; lead-free and RoHS compliant Temperature range: 40 C to +125 C 2.2 Features: radio     2.4 GHz IEEE802.15.4 compliant RX current 14.7 mA, in low power receive mode 13 mA Receiver sensitivity 96 dBm Configurable transmit power, for example: JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller            10 dBm, 23.3 mA  8.5 dBm, 19.6 mA  3 dBm, 14 mA Radio link budget 106 dB Maximum input level of +10 dBm Compensation for temperature drift of crystal oscillator frequency 128-bit AES security processor MAC accelerator with packet formatting, CRCs, address check, auto-acks, timers Integrated ultra low-power RC sleep oscillator (0.7 A) 2.0 V to 3.6 V battery operation Deep sleep current 50 nA (wake-up from IO) < 0.15 $ external component cost Antenna diversity (Auto RX) 2.3 Features: microcontroller                   32-bit RISC CPU; 1 MHz to 32 MHz clock speed Variable instruction width for high coding efficiency Multi-stage instruction pipeline 512 kB Flash 32 kB RAM 4 kB EEPROM Data EEPROM with guaranteed 100 k write operations ZigBee PRO stack with Home Automation, Light Link and Smart Energy profiles 2-wire I2C-bus compatible serial interface; can operate as either master or slave 5  PWM (4 timers, 1 timer/counter) 2 low-power sleep counters 2UARTs SPI-bus master and slave port, 3 selects Supply voltage monitor with 8 programmable thresholds 6-input 10-bit ADC, comparator Battery and temperature sensors Watchdog and Supply Voltage Monitor (SVM) Up to 20 Digital IO (DIO) pins 3. Applications         JN5169 Product data sheet Robust and secure low-power wireless applications ZigBee 3.0 Internet of Things (IoT) ZigBee Smart Energy networks ZigBee Light Link networks ZigBee Home Automation networks Toys and gaming peripherals Energy harvesting - for example, self-powered light switch All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 2 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 4. Overview The JN5169 wireless microcontroller that provides a fully integrated solution for applications that use the IEEE802.15.4 standard in the 2.4 GHz to 2.5 GHz ISM frequency band, including ZigBee PRO applications based on the Smart Energy, Light Link and Home Automation profiles. The JN5169 features 512 kB embedded Flash, 32 kB RAM and 4 kB EEPROM memory and radio outputs up to 10 dBm. Applications that transfer data wirelessly tend to be more complex than applications for wired solutions. Wireless protocols make stringent demands on frequencies, data formats, timing of data transfers, security and other issues. Application development must consider the requirements of the wireless network in addition to the product functionality and user interfaces. To minimize this complexity, NXP provides a series of software libraries and interfaces that control the transceiver and peripherals of the JN5169. These libraries and interfaces remove the need for the developer to understand wireless protocols and greatly simplifies the programming complexities of power modes, interrupts and hardware functionality. In view of the above, we do not provide the JN5169 register details in this data sheet. The device includes a wireless transceiver, RISC CPU, on-chip memory and an extensive range of peripherals. 4.1 Wireless transceiver The wireless transceiver comprises a 2.45 GHz radio, a modem, a baseband controller and a security coprocessor. In addition, the radio also provides an output to control transmit-receive switching of external devices such as power amplifiers allowing applications that require increased transmit power to be realized very easily. Section 15.1 describes a complete reference design including Printed-Circuit Board (PCB) design and Bill Of Materials (BOM). The security coprocessor provides hardware-based 128-bit AES-CCM modes as specified by the IEEE802.15.4 2006 standard. Specifically this includes encryption and authentication covered by the MIC-32/-64/-128, ENC and ENC-MIC-32/-64/-128 modes of operation. The transceiver elements (radio, modem and baseband) work together to provide IEEE802.15.4 (2006) MAC and PHY functionality under the control of a protocol stack. Applications incorporating IEEE802.15.4 functionality can be developed rapidly by combining user-developed application software with a protocol stack library. 4.2 RISC CPU and memory A 32-bit RISC CPU allows software to be run on-chip, its processing power being shared between the IEEE802.15.4 MAC protocol, other higher layer protocols and the user application. The JN5169 has a unified memory architecture. Code memory, data memory, peripheral devices and I/O ports are organized within the same linear address space. The device contains up to 512 kB of Flash, 32 kB of RAM and 4 kB EEPROM. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 3 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 4.3 Peripherals The following peripherals are available on chip: • Master SPI-bus port with 3 select outputs • Slave SPI-bus port • 2 UARTs: one capable of hardware flow control (4-wire, includes RTS/CTS); the other just 2-wire (RX/TX) • 1 programmable timer/counter which supports Pulse Width Modulation (PWM) and capture/compare, plus 4 PWM timers which support PWM and Timer modes only • 2 programmable sleep timers and 1 tick timer • 2-wire serial interface (compatible with SMbus and I2C-bus) supporting master and slave operation • • • • • • • • • • 20 digital I/O lines (multiplexed with peripherals such as timers, SPI-bus and UARTs) 2 digital outputs (multiplexed with SPI-bus port) 10-bit, Analog-to-Digital Converter (ADC) with up to 6 input channels Programmable analog comparator Internal temperature sensor and battery monitor 2 low-power pulse counters Random number generator Watchdog timer and Supply Voltage Monitor JTAG hardware debug port Transmit and receive antenna diversity with automatic receive switching based on received energy detection User applications access the peripherals using the JN516x Integrated Peripherals API (Application Programming Interface). This allows applications to use a tested and easily understood view of the peripherals facilitating rapid system development. 5. Ordering information Table 1. Ordering information Type number JN5169 Package Name Description Version HVQFN40 Plastic thermal enhanced very thin quad flat package; no leads; 40 terminals; body 6  6  0.85 mm SOT618-8 For further details, refer to the Wireless Connectivity area of the NXP web site Ref. 1. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 4 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 6. Block diagram WATCHDOG TIMER 2.4 GHz RADIO INCLUDING DIVERSITY VOLTAGE BROWNOUT RAM 32 kB FLASH 512 kB 2-WIRE SERIAL (MASTER/SLAVE) 32-BIT RISC CPU O-QPSK MODEM 4 X PWM PLUS TIMER 2 X UART 4 kB EEPROM XTAL SPI-BUS MASTER AND SLAVE IEEE802.15.4 MAC ACCELERATOR 20 DIO PLUS 2 DO SLEEP COUNTER 6 CHAN 10 BIT ADC POWER MANAGEMENT 128-BIT AES ENCRYPTION ACCELERATOR BATTERY AND TEMP SENSORS aaa-013126 Fig 1. Block diagram JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 5 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 7. Functional diagram SPI-BUS SLAVE TICK TIMER PROGRAMMABLE INTERRUPT CONTROLLER 32-BIT RISC CPU FLASH 512 kB EEPROM 4 kB VDD UART0 1.8 V TIMER0 XTAL_IN XTAL_OUT RESET_N 32 MHz XTAL CLOCK GENERATOR CLOCK SOURCE AND RATE SELECT HIGHSPEED RC OSC RESET WATCHDOG TIMER WAKEUP TIMER0 VOLTAGE REGULATORS WAKEUP TIMER1 32 kHz CLOCK SELECT 32 kHz RC OSC 32 kHz XTAL OSC DIO4 DIO5 DIO6 DIO7 DIO8 DIO9 PWM1 PWM2 PWM3 PWM4 2-WIRE INTERFACE DIO14 DIO15 DIO16 DIO17 JTAG_TDI JTAG_TMS JTAG_TCK JTAG_TDO ANTENNA DIVERSITY DIO11 DIO13 PC0 PC1 PULSE COUNTERS DIO10 DIO12 SIF_D SIF_CLK 32KIN DIO18 DIO19 DO0 ADO ADE DO1 32KXTALIN 32KXTALOUT WIRELESS TRANSCEIVER SECURITY PROCESSOR SUPPLY MONITOR ADC1 VREF/ADC2 ADC3 ADC4 ADC5 ADC6 DIO3 TIM0CK_GT TIM0OUT MUX TIM0CAP PWMs JTAG DEBUG DIO2 TXD1 RXD1 UART1 VOLTAGE REGULATORS DIO1 TXD0 RXD0 RTS0 CTS0 CPU and 16 MHz system clock VB_XX(1) DIO0 SPICLK SPIMOSI SPIMISO SPISEL0 SPISEL1 SPISEL2 SPI-BUS MASTER from peripherals RAM 32 kB SPISCLK SPISMOSI SPISMISO SPISSEL DIGITAL BASEBAND MUX ADC RF_IO RADIO IBIAS TEMPERATURE SENSOR COMP1M COMP1P COMPARATOR1 aaa-013127 (1) With XX = SYNTH or VCO or RF2 or RF1 or DIG. Fig 2. Functional block diagram JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 6 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 8. Pinning information 31 DIO8/TIM0CK_GT/PC1/PWM4 32 DIO9/TIM0CAP/32KXTALIN/RXD1/32KIN 33 DIO10/TIM0OUT/32KXTALOUT 34 DIO11/PWM1/TXD1 35 VB_DIG 36 DIO12(1) 37 DIO13(2) 38 DIO14(3) terminal 1 index area 39 VSS 40 DIO15(4) 8.1 Pinning DIO16/SPISMOSI/SIF_CLK/COMP1P 1 30 VDDD DIO17/SPISMISO/SIF_D/COMP1M/PWM4 2 29 DIO7/RXD0/JTAG_TDI/PWM3 RESET_N 3 28 DIO6/TXD0/JTAG_TDO/PWM2 XTAL_OUT 4 27 DIO5/RTS0/JTAG_TMS/PWM1/PC1 XTAL_IN 5 26 DIO4/CTS0/JTAG_TCK/TIM0OUT/PC0 JN5169 VB_SYNTH 6 25 i.c. i.c. 7 24 DIO19/SPISEL0 VB_VCO 8 23 DIO18/SPIMOSI DO0/SPICLK/PWM2 20 DIO3/RFTX/TIM0CAP/ADC6 19 DIO2/RFRX/TIM0CK_GT/ADC5 18 DIO0/ADO/SPISEL1/ADC3 16 DIO1/ADE/SPISEL2/ADC4/PC0 17 ADC1 15 VB_RF1 14 21 VSS RF_IO 13 IBIAS 10 VB_RF2 12 22 DO1/SPIMISO/PWM3 VREF/ADC2 11 VDDA 9 aaa-013128 Transparent top view Refer to Section 15 for important applications information regarding the connection of the paddle to the PCB. (1) Multi-function: DIO12/PWM2/CTS0/JTAG_TCK/ADO/SPISMOSI. (2) Multi-function: DIO13/PWM3/RTS0/JTAG_TMS/ADE/SPISMISO. (3) Multi-function: DIO14/SIF_CLK/TXD0/TXD1/JTAG_TDO/SPISEL1/SPISSEL. (4) Multi-function: DIO15/SIF_D/RXD0/RXD1/JTAG_TDI/SPISEL2/SPISCLK. Fig 3. Pin configuration JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 7 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 8.2 Pin description Table 2. Pin description Symbol Pin Type[1] Description DIO16/SPISMOSI/SIF_CLK/COMP1P 1 DIO16 — DIO16 I/O COMP1P — comparator plus input SIF_CLK — Serial Interface clock SPISMOSI — SPI-bus slave Master Out Slave In input DIO17/SPISMISO/SIF_D/COMP1M/PWM4 2 I/O DIO17 — DIO17 COMP1M — comparator minus input SIF_D — Serial Interface Data SPISMISO — SPI-bus slave Master In Slave Out output PWM4 — PWM 4 output RESET_N 3 I RESET_N — reset input XTAL_OUT 4 O XTAL_OUT — system crystal oscillator XTAL_IN 5 I XTAL_IN — system crystal oscillator VB_SYNTH 6 P VB_SYNTH — regulated supply voltage i.c. 7 - internally connected; leave open VB_VCO 8 P VB_VCO — regulated supply voltage VDDA 9 P VDDA — analog supply voltage IBIAS 10 I IBIAS — bias current control VREF/ADC2 11 P VREF — analog peripheral reference voltage I ADC2 — ADC input 2 VB_RF2 12 P VB_RF2 — regulated supply voltage RF_IO 13 I/O RF_IO — RF antenna VB_RF1 14 P VB_RF1 — regulated supply voltage ADC1 15 I ADC1 — ADC input DIO0/ADO/SPISEL1/ADC3 16 I/O DIO0 — DIO0 ADO — antenna diversity odd output SPISEL1 — SPI-bus master select output 1 ADC3 — ADC input: ADC3 DIO1/ADE/SPISEL2/ADC4/PC0 17 I/O DIO1 — DIO1 ADE — antenna diversity even output SPISEL2 — SPI-bus master select output 2 ADC4 — ADC input: ADC4 PC0 — pulse counter 0 input DIO2/RFRX/TIM0CK_GT/ADC5 18 I/O DIO2 — DIO2 RFRX — radio receiver control output TIM0CK_GT — timer0 clock/gate input ADC5 — ADC input: ADC5 JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 8 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller Table 2. Pin description …continued Symbol Pin Type[1] Description DIO3/RFTX/TIM0CAP/ADC6 19 DIO3 — DIO3 I/O RFTX — radio transmitter control output TIM0CAP — timer0 capture input ADC6 — ADC input: ADC6 DO0/SPICLK/PWM2[2] 20 O DO0 — DO0 SPICLK — SPI-bus master clock output PWM2 — PWM2 output VSS 21 GND VSS — ground DO1/SPIMISO/PWM3[3] 22 I/O DO1 — DO1 SPIMISO — SPI-bus Master In, Slave Out input PWM3 — PWM3 output DIO18/SPIMOSI 23 I/O DIO18 — DIO18 SPIMOSI — SPI-bus Master Out Slave In output DIO19/SPISEL0 24 I/O DIO19 — DIO19 SPISEL0 — SPI-bus master Select Output 0 i.c. 25 - internally connected; leave open DIO4/CTS0/JTAG_TCK/TIM0OUT/PC0 26 I/O DIO4 — DIO4 CTS0 — UART 0 clear to send input JTAG_TCK — JTAG CLK input TIM0OUT — timer0 PWM output PC0 — pulse counter 0 input DIO5/RTS0/JTAG_TMS/PWM1/PC1 27 I/O DIO5 — DIO5 RTS0 — UART 0 request to send output JTAG_TMS — JTAG mode select input PWM1 — PWM1 output PC1 — pulse counter 1 input DIO6/TXD0/JTAG_TDO/PWM2 28 I/O DIO6 — DIO6 TXD0 — UART 0 transmit data output JTAG_TDO — JTAG data output PWM2 — PWM2 data output DIO7/RXD0/JTAG_TDI/PWM3 29 I/O DIO7 — DIO7 RXD0 — UART 0 receive data input JTAG_TDI — JTAG data input PWM3 — PWM 3 data output VDDD 30 P VDDD — digital supply voltage DIO8/TIM0CK_GT/PC1/PWM4 31 I/O DIO8 — DIO8 TIM0CK_GT — timer0 clock/gate input PC1 — pulse counter1 input PWM4 — PWM 4 output JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 9 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller Table 2. Pin description …continued Symbol Pin Type[1] Description DIO9/TIM0CAP/32KXTALIN/RXD1/32KIN 32 DIO9 — DIO9 I/O TIM0CAP — Timer0 Capture input 32KXTALIN — 32 kHz External Crystal input RXD1 — UART1 Receive Data input 32KIN — 32 kHz External clock input DIO10/TIM0OUT/32KXTALOUT 33 I/O DIO10 — DIO10 TIM0OUT — Timer0 PWM Output 32KXTALOUT — 32 kHz External Crystal output DIO11/PWM1/TXD1 34 I/O DIO11 — DIO11 PWM1 — PWM1 output TXD1 — UART1 Transmit Data output VB_DIG 35 P VB_DIG — regulated supply voltage DIO12[4] 36 I/O DIO12 — DIO12 PWM2 — PWM2 output CTS0 — UART0 clear to send input JTAG_TCK — JTAG CLK input ADO — antenna diversity odd output SPISMOSI — SPI-bus slave Master Out, Slave In input DIO13[5] 37 I/O DIO13 — DIO13 PWM3 — PWM3 output RTS0 — UART0 request to send output JTAG_TMS — JTAG mode select input ADE — antenna diversity even output SPISMISO — SPI-bus slave master in slave out output DIO14[6] 38 I/O DIO14 — DIO14 SIF_CLK — serial interface clock TXD0 — UART 0 transmit data output TXD1 — UART 1 transmit data output JTAG_TDO — JTAG data output SPISEL1 — SPI-bus master select output 1 SPISSEL — SPI-bus slave select input VSS 39 GND VSS — ground DIO15[7] 40 I/O DIO15 — DIO15 SIF_D — serial interface data RXD0 — UART 0 receive data input RXD1 — UART 1 receive data input JTAG_TDI — JTAG data input SPISEL2 — SPI-bus master select output 2 SPISCLK — SPI-bus slave clock input VSSA [1] - GND VSSA — Exposed die paddle P = power supply; G = ground; I = input, O = output; I/O = input/output. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 10 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller [2] JTAG programming mode: must be left floating high during reset to avoid entering JTAG programming mode. [3] UART programming mode: leave pin floating high during reset to avoid entering UART programming mode or hold it low to program. [4] Multi-function: DIO12/PWM2/CTS0/JTAG_TCK/ADO/SPISMOSI. [5] Multi-function: DIO13/PWM3/RTS0/JTAG_TMS/ADE/SPISMISO. [6] Multi-function: DIO14/SIF_CLK/TXD0/TXD1/JTAG_TDO/SPISEL1/SPISSEL. [7] Multi-function: DIO15/SIF_D/RXD0/RXD1/JTAG_TDI/SPISEL2/SPISCLK. The PCB schematic and layout rules detailed in Section 15.1 must be followed. Failure to do so will likely result in the JN5169 failing to meet the performance specification detailed in this data sheet and the worst case may result in the device not functioning in the end application. 8.2.1 Power supplies The device is powered from the VDDA and VDDD pins, each being decoupled with a 100 nF ceramic capacitor. VDDA is the power supply to the analog circuitry; it should be decoupled to ground. VDDD is the power supply for the digital circuitry; it should also be decoupled to ground. In addition, a common 10 F tantalum capacitor is required for low frequencies. Decoupling pins for the internal 1.8 V regulators are provided with each pin requiring a 100 nF capacitor located as close to the device as practical. VB_SYNTH and VB_DIG require only a 100 nF capacitor. VB_RF1 and VB_RF2 should be connected together as close to the device as practical, and require one 100 nF capacitor and one 47 pF capacitor. The pin VB_VCO requires a 10 nF capacitor. See Figure 48 for a schematic diagram. VSSA and VSS are the ground pins. Users are strongly discouraged from connecting their own circuits to the 1.8 V regulated supply pins, as the regulators have been optimized to supply only enough current for the internal circuits. Rising VDD voltage at power-up has to be done within 100 ms with a minimum IDD current of 20 mA to avoid any start up issue. 8.2.2 Reset RESET_N is an active-low reset input pin that is connected to a 500 k internal pull-up resistor. It may be pulled low by an external circuit. See Section 9.4.2 for more details. 8.2.3 32 MHz oscillator A crystal is connected between XTAL_IN and XTAL_OUT to form the reference oscillator, which drives the system clock. A capacitor to analog ground is required on each of these pins. See Section 9.3.1 for more details. The 32 MHz reference frequency is divided down to 16 MHz and this is used as the system clock throughout the device. 8.2.4 Radio The radio is a single-ended design, requiring two capacitors and just two inductors to match the 50  microstrip line to the RF_IO pin. In addition, extra-components are added on the line for filtering purpose. An external resistor (43 k) is required between IBIAS and analog ground (paddle) to set various bias currents and references within the radio. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 11 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 8.2.5 Analog peripherals The ADC requires a reference voltage to use as part of its operation. It can use either an internal reference voltage or an external reference connected to VREF. This voltage is referenced to analog ground and the performance of the analog peripherals is dependent on the quality of this reference. There are 6 ADC inputs and a pair of comparator inputs. ADC1 has a designated input pin but ADC2 uses the same pin as VREF, invalidating its use as an ADC pin when an external reference voltage is required. The remaining 4 ADC channels are shared with the digital I/Os DIO0, DIO1, DIO2 and DIO3. When these 4 ADC channels are selected, the corresponding DIOs must be configured as inputs with their pull-ups disabled. Similarly, the comparator shares pins 1 and 2 with DIO16 and DIO17, so when the comparator is selected these pins must be configured as inputs with their pull-ups disabled. The analog I/O pins on the JN5169 can have signals applied up to 0.3 V higher than VDDA. A schematic view of the analog I/O cell is shown in Figure 4. Figure 5 demonstrates a special case, where a digital I/O pin doubles as an input to analog devices. This applies to ADC3, ADC4, ADC5, ADC6, COMP1P and COMP1M. In reset, sleep and deep sleep, the analog peripherals are all OFF. In sleep, the comparator may optionally be used as a wake-up source. On platform with higher power (e.g. light Bulb, Smart Plug), unused ADC and comparator inputs should not be left unconnected, but connected to analog ground. VDDA ANALOG PERIPHERAL analog I/O pin VSSA Fig 4. aaa-017249 Analog I/O cell 8.2.6 Digital Input/Output For the DC properties of these pins, see Section 14.2. When used in their primary function, all Digital Input/Output pins are bidirectional and are connected to weak internal pull-up resistors (50 k nominal) that can be disabled. When used in their secondary function (selected when the appropriate peripheral block is enabled through software library calls), their direction is fixed by the function. The pull-up resistor is enabled or disabled independently of the function and direction; the default state from reset is enabled. A schematic view of the Digital I/O cell shown in Figure 5. The dotted lines through resistor RESD represent a path that exists only on DIO0, DIO1, DIO2, DIO3, DIO16 and DIO17 which are also inputs to the ADC (ADC3, ADC4, ADC5 and ADC6) and Comparator (COMP1P and COMP1M) respectively. To use these DIO pins for their analog functions, the DIO must be set as an input with its pull-up resistor, RPU, disabled. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 12 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller VDDD ADC or COMP1 input Pu IE RPU RESD RPROT DIOx(1) Pin I VSS VSS O OE aaa-015437 (1) With x = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 or 19. Fig 5. DIO equivalent schematic In reset, the digital peripherals are all off and the DIO pins are set as high-impedance inputs. During sleep and deep sleep, the DIO pins retain both their input/output state and the output level that was set at the start of sleep. If the DIO pins were enabled as inputs and the interrupts were enabled, then these pins may be used to wake up the JN5169 from sleep. 9. Functional description 9.1 CPU The CPU of the JN5169 is a 32-bit load and store RISC processor. It has been architected for 3 key requirements: • Low power consumption for battery powered applications • High performance to implement a wireless protocol at the same time as complex applications • Efficient coding of high-level languages such as C provided with the Software Developer’s Kit It features a linear 32-bit logical address space with unified memory architecture, accessing both code and data in the same address space. Registers for peripheral units, such as the timers, UART and the baseband processor, are also mapped into this space. The CPU has access to a block of 15  32-bit General-Purpose (GP) registers together with a small number of special purpose registers which are used to store processor state and control interrupt handling. The contents of any GP register can be loaded from or stored to memory. Arithmetic and logical operations, shift and rotate operations, and signed and unsigned comparisons can be performed either between two registers and stored in a third, or between registers and a constant carried in the instruction. Operations between general or special-purpose registers execute in one cycle while those that access memory requires a further cycle to allow the memory to respond. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 13 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller The instruction set manipulates 8-bit, 16-bit and 32-bit data; this means that programs can use objects of these sizes very efficiently. Manipulation of 32-bit quantities is particularly useful for protocols and high-end applications allowing algorithms to be implemented in fewer instructions than on smaller word-size processors, and allowing execution in fewer clock cycles. In addition, the CPU supports hardware Multiply that can be used to efficiently implement algorithms needed by Digital Signal Processing applications. The instruction set is designed for the efficient implementation of high-level languages such as C. Access to fields in complex data structures is very efficient due to the provision of several addressing modes, together with the ability to use any of the GP registers to contain the address of objects. Subroutine parameter passing is also made more efficient by using GP registers rather than pushing objects onto the stack. The recommended programming method for the JN5169 is to use C, which is supported by a software developer kit comprising a C compiler, linker and debugger. The CPU architecture also contains features that make the processor suitable for embedded, real-time applications. In some applications, it may be necessary to use a real-time operating system to allow multiple tasks to run on the processor. To provide protection for device-wide resources being altered by one task and affecting another, the processor can run in either supervisor or user mode, the former allowing access to all processor registers, while the latter only allows the GP registers to be manipulated. Supervisor mode is entered on reset or interrupt; tasks starting up would normally run in user mode in an RTOS environment. Embedded applications require efficient handling of external hardware events. Exception processing (including reset and interrupt handling) is enhanced by the inclusion of a number of shadow registers into which the PC and status register contents are copied as part of the operation of the exception hardware. This means that the essential registers for exception handling are stored in one cycle, rather than the slower method of pushing them onto the processor stack. The PC is also loaded with the vector address for the exception that occurred, allowing the handler to start executing in the next cycle. To improve power consumption, a number of power-saving modes are implemented in the JN5169, described more fully in Section 10. One of these modes is the CPU doze mode; under software control, the processor can be shut down and on an interrupt it will wake up to service the request. Additionally, it is possible under software control to set the speed of the CPU to 1 MHz, 2 MHz, 4 MHz, 8 MHz, 16 MHz or 32 MHz. This feature can be used to trade off processing power against current consumption. 9.2 Memory organization This section describes the different memories found within the JN5169. The device contains Flash, RAM and EEPROM memory, the wireless transceiver and peripherals all within the same linear address space. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 14 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller Unpopulated 0xFFFFFFFF 0xF0008000 RAM 0xF0000000 0x04008000 Shadow RAM 0x04000000 Peripherals 0x02000000 Flash and EEPROM Registers 0x01000000 0x00100000 Flash Applications Code (512 kB) 0x00080000 Flash Boot Code 8 kB 0x00000000 Fig 6. aaa-017150 JN5169 memory map 9.2.1 Flash The embedded Flash consists of 2 parts: an 8 kB region used for holding boot code and a 512 kB region used for application code. The maximum number of write cycles or endurance is 10 k guaranteed, and typically 50 k, while the data retention is guaranteed for at least 10 years. The boot code region is pre-programmed by NXP on supplied parts and contains code to handle reset, interrupts and other events (see Section 6). It also contains a Flash Programming interface to allow interaction with the PC-based Flash programming utility which allows user code compiled using the supplied toolchain to be programmed into the Application space. For further information, see the Application Note on the Wireless Connectivity area of the NXP web site Ref. 1. 9.2.2 RAM The JN5169 devices contain 32 kB of high-speed RAM, which can be accessed by the CPU in a single clock cycle. It is primarily used to hold the CPU Stack together with program variables and data. If necessary, the CPU can execute code contained within the RAM (although it would normally just execute code directly from the embedded Flash). Software can control the power supply to the RAM allowing the contents to be maintained during a sleep period when other parts of the device are unpowered, allowing a quicker resumption of processing once woken. JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 15 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller 9.2.3 OTP configuration memory The JN5169 devices contain a quantity of One Time Programmable (OTP) memory as part of the embedded Flash (Index Sector). This can be used to securely hold such things as a user 64-bit MAC address and a 128-bit AES security key. A limited number of further bits are available for customer use for storage of configuration or other information. By default, the 64-bit MAC address is pre-programmed by NXP on supplied parts; however, customers can use their own MAC address and override the default one. The user MAC address and other data can be written to the OTP memory using the Flash programmer. Details on how to obtain and install MAC addresses can be found in the dedicated Application Note. For further information on how to program and use this facility, see BeyondStudio for NXP User Guide (JN-UG-3098) on the Wireless Connectivity area of the NXP web site Ref. 1. 9.2.4 EEPROM The JN5169 devices contain 4 kB of EEPROM. The maximum number of write cycles or endurance is 100 k guaranteed, and 500 k typically, while the data retention is guaranteed for at least 10 years. This non-volatile memory is primarily used to hold persistent data generated from such things as the network stack software component (for example network topology, routing tables). As the EEPROM holds its contents through sleep and reset events, more stable operation and faster recovery is possible after outages. Access to the EEPROM is via registers mapped into the Flash and EEPROM registers region of the address map. The customer may use part of the EEPROM to store their own data by interfacing with the Persistent Data Manager (PDM). Optionally, the PDM can also store data in an external memory. For further information, see the Wireless Connectivity area of the NXP web site Ref. 1. 9.2.5 External memory An optional external serial non-volatile memory (for instance Flash or EEPROM) with a SPI-bus interface may be used to provide additional storage for program code, such as a new code image or further data for the device when external power is removed. The memory can be connected to the SPI-bus master interface using select line SPISEL0 (see Figure 7 for details). serial memory JN5169 SPISEL0 SS SPIMISO SDO SPIMOSI SDI SPICLK CLK aaa-013129 Fig 7. Connecting external serial memory The contents of the external serial memory may be encrypted. The AES security processor combined with a user programmable 128-bit encryption key is used to encrypt the contents of the external memory. The encryption key is stored in the Flash memory JN5169 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1.3 — 22 September 2017 © NXP Semiconductors N.V. 2017. All rights reserved. 16 of 95 JN5169 NXP Semiconductors IEEE802.15.4 Wireless Microcontroller index sector. When bootloading program code from external serial memory, the JN5169 automatically accesses the encryption key to execute the decryption process. The user program code does not need to handle any of the decryption processes; it is transparent. For more details, including the how the program code encrypts data for the external memory, see the Application Note JN51xx Boot Loader Operation (JN-AN-1003) on the Wireless Connectivity area of the NXP web site Ref. 1. 9.2.6 Peripherals All peripherals have their registers mapped into the memory space. Access to these registers requires three peripheral clock cycles. Applications have access to the peripherals through the software libraries that present a high-level view of the peripheral's functions through a series of dedicated software routines. These routines provide both a tested method for using the peripherals and allow bug-free application code to be developed more rapidly. For details, see JN516x Integrated Peripherals API User Guide (JN-UG-3087) on the Wireless Connectivity area of the NXP web site Ref. 1. 9.2.7 Unused memory address Any attempt to access an unpopulated memory area will result in a bus error exception (interrupt) being generated. 9.3 System clocks Two system clocks are used to drive the on-chip subsystems of the JN5169. The wake-up timers are driven from a low frequency clock (notionally 32 kHz). All other subsystems (transceiver, processor, memory and digital and analog peripherals) are driven by a high-speed clock (notionally 32 MHz), or a divided-down version of it. The high-speed clock is either generated by the accurate crystal-controlled oscillator (32 MHz) or the less accurate high-speed RC oscillator (27 MHz to 32 MHz calibrated). The low-speed clock is either generated by the accurate crystal-controlled oscillator (32 kHz to 768 kHz), the less accurate RC oscillator (centered on 32 kHz) or can be supplied externally. 9.3.1 High-speed (32 MHz) system clock The selected high-speed system clock is used directly by the radio subsystem, whereas a divided-by-two version is used by the remainder of the transceiver and the digital and analog peripherals. The direct or divided-down version of the clock is used to drive the processor and memories (32 MHz, 16 MHz, 8 MHz, 4 MHz, 2 MHz or 1 MHz). 0+]&5