OM40001UL

LPC804 32-bit Arm® Cortex®-M0+ microcontroller; up to 32 KB flash and 4 KB SRAM; 12-bit ADC; Comparator; 10-bit DAC; Capacitive Touch Interface; Programmable Logic Unit Rev. 2.0 — 21 September 2021 Product data sheet 1. General description The LPC804 are an ArmCortex-M0+ based, low-cost 32-bit MCU family operating at CPU frequencies of up to 15 MHz. The LPC804 supports 32 KB of flash memory and 4 KB of SRAM. The peripheral complement of the LPC804 includes a CRC engine, two I2C-bus interfaces, up to two USARTs, one SPI interface, Capacitive Touch Interface (Cap Touch), one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one 12-bit ADC, one 10-bit DAC, one analog comparator, function-configurable I/O ports through a switch matrix, an input pattern match engine, Programmable Logic Unit (PLU), and up to 30 general-purpose I/O pins. For additional documentation related to the LPC804 parts, see Section 19. 2. Features and benefits  System:  Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz with single-cycle multiplier and fast single-cycle I/O port.  Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).  System tick timer.  AHB multilayer matrix.  Serial Wire Debug (SWD) with four break points and two watch points. JTAG boundary scan (BSDL) supported.  Memory:  Up to 32 KB on-chip EEPROM based flash programming memory.  Code Read Protection (CRP).  4 KB SRAM.  Dual I/O power (LPC804M111JDH24):  Independent supplies on each package side permitting level-shifting signals from one off-chip voltage domain to another and/or interfacing directly to off-chip peripherals operating at different supply levels.  The switch matrix provides level shifter functionality to allow up to two selected signals to be routed from user-selected pins in one voltage domain to selected pins in the alternate domain. This feature can also be used on a single supply device if voltage level shifting is not required.  ROM API support:  Boot loader. LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller       LPC804 Product data sheet  Supports Flash In-Application Programming (IAP).  Supports In-System Programming (ISP) through USART.  On-chip ROM APIs for integer divide.  Free Running Oscillator (FRO) API. Digital peripherals:  High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 30 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors, programmable open-drain mode, and input inverter. GPIO direction control supports independent set/clear/toggle of individual bits.  High-current source output driver (20 mA) on five pins.  GPIO interrupt generation capability with boolean pattern-matching feature on eight GPIO inputs.  Switch matrix for flexible configuration of each I/O pin function.  CRC engine.  Capacitive Touch Interface.  Programmable Logic Unit (PLU) to create small combinatorial and/or sequential logic networks including simple state machines. Timers:  One 32-bit general purpose counter/timer, with four match outputs and three capture inputs. Supports PWM mode, and external count  Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to four programmable, fixed rates.  Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a low-power, low-frequency internal oscillator, or an external clock input.  Windowed Watchdog timer (WWDT). Analog peripherals:  One 12-bit ADC with up to 12 input channels with multiple internal and external trigger inputs and with sample rates of up to 480 Ksamples/s. The ADC supports two independent conversion sequences.  Comparator with five input pins and external or internal reference voltage.  One 10-bit DAC. Serial peripherals:  Two USART interfaces with pin functions assigned through the switch matrix and one fractional baud rate generators.  One SPI controllers with pin functions assigned through the switch matrix.  Two I2C-bus interface. It supports data rates up to 400 kbit/s on standard digital pins. Clock generation:  Free Running Oscillator (FRO). This oscillator provides a selectable 9 MHz, 12 MHz and 15 MHz outputs that can be used as a system clock. The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C to 70 C.  1 MHz low power oscillator can be used as a clock source.  Clock output function with divider that can reflect all internal clock sources. Power control:  Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and deep power-down mode. All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 2 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller     LPC804 Product data sheet  Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and I2C peripherals.  Wake-up from deep power-down mode on multiple pins.  Timer-controlled self wake-up from sleep, deep-sleep, and power-down modes.  Power-On Reset (POR).  Brownout detect (BOD). Unique device serial number for identification. Single power supply (1.71 V to 3.6 V). Operating temperature range -40 °C to +105 °C. Available in WLCSP20, TSSOP20, TSSOP24, and HVQFN33 packages. All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 3 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 3. Applications       Sensor gateways Industrial Gaming controllers 8/16-bit applications Consumer Climate control      Simple motor control Portables and wearables Lighting Motor control Fire and security applications 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC804M101JDH20 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 LPC804M101JDH24 TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 LPC804M111JDH24 TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 LPC804M101JHI33 HVQFN33 HVQFN: plastic thermal enhanced very thin quad flat package; no leads; SOT617-11 33 terminals; body 5  5  0.85 mm LPC804UK WLCSP20 wafer level chip-size package; 20 (5  4) bumps; 2.50 1.84  0.5 mm SOT1397-8 4.1 Ordering options Table 2. Ordering options Flash/KB SRAM/KB USART I2C SPI DAC Capacitive Touch PLU GPIO Dual I/O power supply Package Type number LPC804M101JDH20 32 4 2 2 1 - yes yes 17 - TSSOP20 LPC804M101JDH24 32 4 2 2 1 1 yes yes 21 - TSSOP24 LPC804M111JDH24 32 4 2 2 1 1 yes yes 20 yes TSSOP24 LPC804M101JHI33 32 4 2 2 1 1 yes yes 30 - HVQFN33 LPC804UK 32 4 2 2 1 - yes yes 17 - WLCSP20 LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 4 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 5. Marking 20 Terminal 1 index area NXP NXP Terminal 1 index area 1 aaa-014766 Fig 1. TSSOP20 and TSSOP24 package markings aaa-014382 Fig 2. HVQFN33 package marking Terminal 1 index area aaa-015675 Fig 3. WLCSP20 package marking The LPC804 HVQFN33 packages have the following top-side marking: • First line: 804M1 • Second line: xxxx • Third line with date code 2139 and before: yywwx[R] – yyww: Date code with yy = year and ww = week. – xR = Boot code version and device revision. • Third line with date code 2140 and after: nyywwx[R] – n = fab code. – yyww: Date code with yy = year and ww = week. – x[R] = Boot code version and device revision. The LPC804 TSSOP20 packages have the following top-side marking: • • • • LPC804 Product data sheet First line: LPC804 Second line: M101 Third line: xxxx Fourth line: xxywwx[R] All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 5 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller – yww: Date code with y = year and ww = week. – xR = Boot code version and device revision. The LPC804 TSSOP24 packages have the following top-side marking: • First line: LPC804 • Second line: xxxx • Third line: ywwx[R] – yww: Date code with y = year and ww = week. – xR = Boot code version and device revision. • Fourth line: M1y1J – y: 0 or 1 The LPC804 WLCSP20 packages have the following top-side marking: • First line: LPC804 • Second line: xxxxx • Third line: xyywwx[R] – yyww: Date code with ww = week and yy = year. – xR = Boot code version and device revision. • Fourth line: xxx - yyy Table 3. Device revision table Revision identifier (R) Revision description 1A Initial device revision with Boot ROM version 13.1 1B Initial device revision with Boot ROM version 13.1 1C Initial device revision with Boot ROM version 13.1 LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 6 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 6. Block diagram CLKIN ISP Access Port RESET DEBUG INTERFACE GPIOs GPIOs AND GPOINT IOP bus ARM Cortex M0+ Clock Generation, Power Control, and other System Functions CLKOUT Voltage Regulator Vdd M0 P0 Flash interface Flash 32 kB Boot ROM 8 kB P1 Multilayer AHB Matrix SRAM 4 kB P2 AHB to APB bridge APB slave group System control UART 0 and 1 IOCON Registers Capacitive Touch CAPT CTIMER0 SPI0 SPI0 Periph Input Mux Selects I2C 0 and 1 Comparator PLU T0 Match/ Capture COMP Inputs UART0,1 I2C0,1 PLU PMU Registers ADC inputs and Triggers 12-bit ADC DAC outputs 10-bit DAC GPIOs Switch Matrix Wakeup Timer Multi-Rate Timer LPOSc Windowed WDT aaa-029233 Fig 4. LPC804 block diagram LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 7 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 7. Pinning information 7.1 Pinning PIO0_16/ADC_3/ACMP_I4 1 20 PIO0_14/ADC_2/ACMP_I3 PIO0_17/ADC_9 2 19 PIO0_0/ACMP_I1/TDO PIO0_13/ADC_10 3 18 VREFP PIO0_12 4 17 PIO0_7/ADC_1/ACMPVREF RESET/PIO0_5 5 PIO0_4/ADC_11/TRST 6 16 VSS 15 VDD SWCLK/PIO0_3/TCK 7 14 PIO0_8/ADC_5 SWDIO/PIO0_2/TMS 8 13 PIO0_9/ADC_4 PIO0_11/ADC_6/WKTCLKIN 9 12 PIO0_1/ADC_0/ACMP_I2/CLKIN/TDI TSSOP20 PIO0_10/ADC_7 10 11 PIO0_15/ADC_8 aaa-026614 Fig 5. Pin configuration TSSOP20 package PIO0_18 1 24 PIO0_19/DACOUT PIO0_16/ACMP_I4/ADC_3 2 23 PIO0_14/ACMP_I3/ADC_2 PIO0_17/ADC_9 3 22 PIO0_0/ACMP_I1/TDO PIO0_13/ADC_10 4 21 VREFP PIO0_12 5 RESET/PIO0_5 6 PIO0_4/ADC_11/TRSTN 7 18 VDD SWCLK/PIO0_3/TCK 8 17 PIO0_8/ADC_5 SWDIO/PIO0_2/TMS 9 16 PIO0_9/ADC_4 PIO0_11/ADC_6/WKTCLKIN 10 PIO0_10/ADC_7 11 PIO0_21/ACMP_I5 12 TSSOP24 20 PIO0_7/ADC_1/ACMPVREF 19 VSS 15 PIO0_1/ADC_0/ACMP_I2/TDI/CLKIN 14 PIO0_15/ADC_8 13 PIO0_20 aaa-029244 Fig 6. Pin configuration TSSOP24 - 1 package (LPC804M101JDH24 - single supply device) LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 8 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller PIO0_18 1 24 PIO0_19/DACOUT PIO0_16/ACMP_I4/ADC_3 2 23 PIO0_14/ACMP_I3/ADC_2 VDDIO 3 22 PIO0_0/ACMP_I1/TDO PIO0_13/ADC_10 4 21 VREFP PIO0_12 5 RESET/PIO0_5 6 PIO0_4/ADC_11/TRSTN 7 18 VDD SWCLK/PIO0_3/TCK 8 17 PIO0_8/ADC_5 SWDIO/PIO0_2/TMS 9 16 PIO0_9/ADC_4 20 PIO0_7/ADC_1/ACMPVREF 19 VSS TSSOP-24 PIO0_11/ADC_6/WKTCLKIN 10 15 PIO0_1/ADC_0/ACMP_I2/TDI/CLKIN 14 PIO0_15/ADC_8 PIO0_10/ADC_7 11 13 PIO0_20 PIO0_21/ACMP_I5 12 aaa-029245 PIO0_16/ADC_3/ACMP_I4 PIO0_18 PIO0_22 PIO0_23 PIO0_24 PIO0_25 PIO0_19/DACOUT PIO0_14/ADC_2/ACMP_I3 31 30 29 28 27 26 25 terminal 1 index area 32 Pin configuration TSSOP24 - 2 package with VDDIO (LPC804M111JDH20 - dual supply device) PIO0_17/ADC_9 1 24 PIO0_13/ADC_10 2 23 VREFP PIO0_12 3 22 PIO0_7/ADC_1/ACMPVREF PIO0_0/ACMP_I1/TDO RESET/PIO0_5 4 21 PIO0_30 PIO0_4/ADC_11/TRSTN 5 20 VDD SWCLK/PIO0_3/TCK 6 19 PIO0_8/ADC_5 SWDIO/PIO0_2/TMS 7 18 PIO0_9/ADC_4 PIO0_11/ADC_6/WKTCLKIN 8 17 PIO0_1/ADC_0/ACMP_I2/TDI/CLKIN 9 10 11 12 13 14 15 16 PIO0_10/ADC_7 PIO0_29 PIO0_28 PIO0_27 PIO0_26 PIO0_20 PIO0_15/ADC_8 33 VSS PIO0_21/ACMP_I5 Fig 7. aaa-029246 Transparent top view Fig 8. Pin configuration HVQFN33 package LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 9 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 7.2 Pin description Table 4 shows the pin functions that are fixed to specific pins on each package. These fixed-pin functions are selectable through the switch matrix between GPIO and the comparator, ADC, SWD, and RESET pins. By default, the GPIO function is selected except on pins PIO0_2, PIO0_3, and PIO0_5. JTAG functions are available in boundary scan mode only. Movable functions for the I2C, USART, SPI, CTimer pins, Capacitive Touch, and other peripherals can be assigned through the switch matrix to any pin that is not power or ground in place of the pin’s fixed functions. The following exceptions apply: Do not assign more than one output to any pin. However, an output and/or one or more inputs can be assigned to a pin. Once any function is assigned to a pin, the pin’s GPIO functionality is disabled. Eight GPIO pins trigger a wake-up from deep power-down mode. If the part must wake up from deep power-down mode via an external pin, do not assign any movable function to this pin. The GPIO pins should be pulled HIGH externally before entering deep power-down mode. A LOW-going pulse as short as 50 ns causes the chip to exit deep power-down mode and wakes up the part. The JTAG functions TDO, TDI, TCK, TMS, and TRST are selected on pins PIO0_0 to PIO0_4 by hardware when the part is in boundary scan mode. PIO0_2, PIO0_3, PIO0_12, PIO0_18, and PIO0_20 are the high drive output pins. PIO0_4, PIO0_8, PIO0_9, PIO0_10, PIO0_11, PIO0_13, PIO0_15, and PIO0_17 are the WAKEUP pins. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 10 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Symbol TSSOP24-2 TSSOP20 HVQFN33 WLCSP20 Pin description TSSOP24-1 Table 4. PIO0_0/ACMP_I1/TDO 22 22 19 24 D3 [2] Reset Type state[1] Description I; PU PIO0_0 — General-purpose port 0 input/output 0. IO In ISP mode, this is the U0_RXD pin (for single supply devices). In boundary scan mode: TDO (Test Data Out). PIO0_1/ADC_0/ACMP_I2/ 15 TDI/CLKIN 15 12 17 A4 [2] I; PU A ACMP_I1 — Analog comparator input 1. IO PIO0_1 — General-purpose port 0 input/output 1. In boundary scan mode: TDI (Test Data In). SWDIO/PIO0_2/ TMS SWCLK/PIO0_3/ TCK 9 8 9 8 8 7 7 6 B2 B1 [3] [3] I; PU I; PU A ACMP_I2 — Analog comparator input 2. I CLKIN — External clock input. IO SWDIO — Serial Wire Debug I/O. SWDIO is enabled by default on this pin. In boundary scan mode: TMS (Test Mode Select). I/O PIO0_2 — General-purpose port 0 input/output 2. I SWCLK — Serial Wire Clock. SWCLK is enabled by default on this pin. In boundary scan mode: TCK (Test Clock). PIO0_4/ADC_11/ TRSTN 7 7 6 5 C2 [2] I; PU IO PIO0_3 — General-purpose port 0 input/output 3. IO PIO0_4 — General-purpose port 0 input/output 4. In ISP mode, this pin is the U0_TXD pin (for single supply devices). In boundary scan mode: TRST (Test Reset). RESET/PIO0_5 6 6 5 4 C1 [5] I; PU A ADC_11 — ADC input 11. IO RESET — External reset input: A LOW-going pulse as short as 50 ns on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. The RESET pin can be left unconnected or be used as a GPIO or for any movable function if an external RESET function is not needed. I LPC804 Product data sheet PIO0_5 — General-purpose port 0 input/output 5. All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 11 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Symbol TSSOP24-2 TSSOP20 HVQFN33 WLCSP20 Pin description TSSOP24-1 Table 4. PIO0_7/ADC_1/ ACMPVREF 20 20 17 22 D4 [2] Reset Type state[1] Description I; PU IO PIO0_7 — General-purpose port 0 input/output 7. A ADC_1 — ADC input 1. ACMPVREF — Alternate reference voltage for the analog comparator. PIO0_8/ADC_5 PIO0_9/ADC_4 17 16 17 16 14 13 19 18 C3 [2] B3 [2] PIO0_10/ADC_7 11 11 10 9 A2 [2] PIO0_11/ADC_6/ WKTCLKIN 10 10 9 8 A1 [2] I; PU IO PIO0_8 — General-purpose port 0 input/output 8. In ISP mode, this is the U0_RXD pin (for dual supply devices). A ADC_5 — ADC input 5. IO PIO0_9 — General-purpose port 0 input/output 9. In ISP mode, this is the U0_TXD pin (for dual supply devices). A ADC_4 — ADC input 4. I; PU I; F PIO0_10 — General-purpose port 0 input/output 10. I; PU I; F I; PU ADC_7 — ADC input 7. PIO0_11 — General-purpose port 0 input/output 11. ADC_6 — ADC input 6. WKTCKLKIN — This pin can host an external clock for the self-wake-up timer. To use the pin as a self-wake-up timer clock input, select the external clock in the wake-up timer CTRL register. The external clock input is active in sleep, deep-sleep, and power-down modes. PIO0_12 5 5 4 3 D1 [3] I; PU IO PIO0_12 — General-purpose port 0 input/output 12. ISP entry pin. A LOW level on this pin during reset starts the ISP command handler. PIO0_13/ADC_10 4 4 3 2 D2 [2] I; PU IO PIO0_13 — General-purpose port 0 input/output 13. A ADC_10 — ADC input 10. E3 [2] IO PIO0_14 — General-purpose port 0 input/output 14. A ACMP_I3 — Analog comparator common input 3. A ADC_2 — ADC input 2. IO PIO0_15 — General-purpose port 0 input/output 15. PIO0_14/ACMP_3/ ADC_2 PIO0_15/ADC_8 23 14 23 14 20 11 25 16 A3 [4] I; PU I; PU ADC_8 — ADC input 8. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 12 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Symbol TSSOP24-2 TSSOP20 HVQFN33 WLCSP20 Pin description TSSOP24-1 Table 4. PIO0_16/ACMP_I4/ ADC_3 2 2 1 32 E2 [3] Reset Type state[1] Description I; PU PIO0_16 — General-purpose port 0 input/output 16. IO ACMP_I4 — Analog comparator common input 4. ADC_3 — ADC input 3. PIO0_17/ADC_9 3 - 2 1 E1 [2] PIO0_18 1 1 - 31 - [3] I; PU PIO0_19/DACOUT 24 24 - 26 - [2] I; PU PIO0_20 13 13 - 15 - [3] PIO0_21/ACMP_I5 12 12 - 10 - [3] I; PU IO PIO0_17 — General-purpose port 0 input/output 17. A ADC_9 — ADC input 9. IO PIO0_18 — General-purpose port 0 input/output 18. IO PIO0_19 — General-purpose port 0 input/output 19. A DACOUT — DAC output. I; PU IO PIO0_20 — General-purpose port 0 input/output 20. I; PU IO PIO0_21 — General-purpose port 0 input/output 21. ACMP_15 — Analog comparator common input 5. PIO0_22 - - - 30 - [3] I; PU IO PIO0_22 — General-purpose port 0 input/output 22. PIO0_23 - - - 29 - [3] I; PU IO PIO0_23 — General-purpose port 0 input/output 23. PIO0_24 - - - 28 - [3] I; PU IO PIO0_24 — General-purpose port 0 input/output 24. PIO0_25 - - - 27 - [3] I; PU IO PIO0_25 — General-purpose port 0 input/output 25. PIO0_26 - - - 14 - [3] I; PU IO PIO0_26 — General-purpose port 0 input/output 26. PIO0_27 - - - 13 - [3] I; PU IO PIO0_27 — General-purpose port 0 input/output 27. PIO0_28 - - - 12 - [3] I; PU IO PIO0_28 — General-purpose port 0 input/output 28. PIO0_29 - - - 11 - [3] I; PU IO PIO0_29 — General-purpose port 0 input/output 29. PIO0_30 - - - 21 - [3] I; PU IO PIO0_30 — General-purpose port 0 input/output 30. VREFP 21 21 18 23 E4 A VREFP — ADC positive reference voltage. Must be equal or lower than VDD. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 13 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller WLCSP20 TSSOP20 HVQFN33 Symbol TSSOP24-2 Pin description TSSOP24-1 Table 4. Reset Type state[1] Description VDD 18 18 15 20 B4 - - If VDDIO is present, VDD is the supply voltage for the I/Os on the right side of the package and the core voltage regulator. If VDDIO is not present, VDD also supplies voltage to the I/Os on the left side of the package. VDDIO - 3 - - - - - If present, it is the supply voltage for the I/Os on the left side of the package. VSS 19 16 33[8] C4 - - Ground. [1] Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD level); IA = inactive, no pull-up/down enabled; F = floating. For pin states in the different power modes, see Section 15.5 “Pin states in different power modes”. For termination on unused pins, see Section 15.4 “Termination of unused pins”. [2] 5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant. [3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes high-current output driver. [4] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. [5] See Figure 16 for the reset pad configuration. This pin includes a 20 ns glitch filter (active in all power modes). RESET functionality is not available in deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from deep power-down mode. [6] The WKTCLKIN function is enabled in the PINENABLE0 register in the PMU. See the LPC804 user manual. [7] The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is disabled. [8] Thermal pad for HVQFN33. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 14 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 8. Movable functions Movable functions for the I2C, USART, SPI, CTimer pins, Capacitive Touch, and other peripherals can be assigned through the switch matrix to any pin that is not power or ground in place of the fixed functions of the pin. Table 5. LPC804 Product data sheet Movable functions (assign to pins PIO0_0 to PIO0_5, PIO0_7 to PIO0_30 through switch matrix) Function name Type Description Ux_TXD O Transmitter output for USART0 to USART1. Ux_RXD I Receiver input for USART0 to USART1. Ux_RTS O Request To Send output for USART0. Ux_CTS I Clear To Send input for USART0. Ux_SCLK I/O Serial clock input/output for USART0 to USART1 in synchronous mode. SPIx_SCK I/O Serial clock for SPI0. SPIx_MOSI I/O Master Out Slave In for SPI0. SPIx_MISO I/O Master In Slave Out for SPI0. SPIx_SSEL0 I/O Slave select 0 for SPI0. SPIx_SSEL1 I/O Slave select 1 for SPI0. I2Cx_SDA I/O I2C0 and I2C1 bus data input/output. I2Cx_SCL I/O I2C0 and I2C1 bus clock input/output. ACMP_O O Analog comparator output. CLKOUT O Clock output. GPIO_INT_BMAT O Output of the pattern match engine. T0_MAT0 O Timer Match channel 0. T0_MAT1 O Timer Match channel 1. T0_MAT2 O Timer Match channel 2. T0_MAT3 O Timer Match channel 3. T0_CAP0 I Timer Capture channel 0. T0_CAP1 I Timer Capture channel 1. T0_CAP2 I Timer Capture channel 2. CAPT_X0 O CAPT_X0 function. CAPT_X1 O CAPT_X1 function. CAPT_X2 O CAPT_X2 function. CAPT_X3 O CAPT_X3 function. CAPT_X4 O CAPT_X4 function. CAPT_YL O CAPT_YL function. CAPT_YH O CAPT_YH function. LVLSHFT_IN0 I Level shift input 0. LVLSHFT_IN1 I Level shift input 1. LVLSHFT_OUT0 O Level shift output 0. LVLSHFT_OUT1 O Level shift output 1. All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 15 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9. Functional description 9.1 Arm Cortex-M0+ core The Arm Cortex-M0+ core runs at an operating frequency of up to 15 MHz using a two-stage pipeline. The core revision is r0p1. Integrated in the core are the NVIC and Serial Wire Debug with four breakpoints and two watchpoints. The Arm Cortex-M0+ core supports a single-cycle I/O enabled port for fast GPIO access. The core includes a single-cycle multiplier and a system tick timer. 9.2 On-chip flash program memory The LPC804 contain up to 32 KB of on-chip EEPROM based flash program memory. 9.3 On-chip SRAM The LPC804 contain a total of 4 KB on-chip static RAM data memory. 9.4 On-chip ROM The on-chip ROM contains the bootloader: • • • • • Boot loader. Supports Flash In-Application Programming (IAP). Supports In-System Programming (ISP) through USART. On-chip ROM APIs for integer divide. Free Running Oscillator (FRO) API. 9.5 Memory map The LPC804 incorporates several distinct memory regions. Figure 9 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The Arm private peripheral bus includes the Arm core registers for controlling the NVIC, the system tick timer (SysTick), and the reduced power modes. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 16 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Memory space (reserved) private peripheral bus (reserved) GPIO interrupts GPIO (reserved) AHB perpherals 0xFFFF FFFF 0xE010 0000 0xA000 4000 0xA000 0000 0x5001 4000 APB perpherals 0x5000 0000 0x4008 0000 APB peripherals 0x4000 0000 (reserved) 0x1000 1000 RAM (reserved) Boot ROM (reserved) 0x5000 4000 0x5000 0000 CRC engine 0xA000 8000 AHB peripherals (reserved) 0x5001 4000 (reserved) 0xE000 0000 0x1000 0000 0x0F00 2000 0x0F00 0000 0x0000 8000 Flash memory (up to 32 KB) 0x0000 0000 active interrupt vectors 0x0000 00C0 0x0000 0000 31-30 (reserved) 29 (reserved) 28 (reserved) 27 (reserved) 26 USART1 25 24 USART0 CAPTouch 23 (reserved) 22 SPI 21 I2C1 20 I2C0 19 (reserved) 18 Syscon 17 16 IOCON (reserved) 15 (reserved) 14 CTIMER 0 13 (reserved) 12 (reserved) 11 (reserved) 10 PLU 9 Analog Comparator 8 PMU 7 ADC 6 (reserved) 5 DAC0 4 (reserved) 3 Switch Matrix 2 Wake-up Timer 1 Multi-Rate Timer 0 Watchdog timer 0x4007 FFFF 0x4007 8000 0x4007 4000 0x4007 0000 0x4006 C000 0x4006 8000 0x4006 4000 0x4006 0000 0x4005 C000 0x4005 8000 0x4005 4000 0x4005 0000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000 0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000 aaa-029247 Fig 9. LPC804 Memory mapping LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 17 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.6 Nested Vectored Interrupt Controller (NVIC) The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0+. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts. 9.6.1 Features • • • • • Nested Vectored Interrupt Controller is a part of the Arm Cortex-M0+. Tightly coupled interrupt controller provides low interrupt latency. Controls system exceptions and peripheral interrupts. Supports 32 vectored interrupts. In the LPC804, the NVIC supports vectored interrupts for each of the peripherals and the eight pin interrupts. • Four programmable interrupt priority levels with hardware priority level masking. • Software interrupt generation using the Arm exceptions SVCall and PendSV. • Supports NMI. 9.6.2 Interrupt sources Each peripheral device has at least one interrupt line connected to the NVIC but can have several interrupt flags. Individual interrupt flags can also represent more than one interrupt source. 9.7 System tick timer The Arm Cortex-M0+ includes a 24-bit system tick timer (SysTick) that is intended to generate a dedicated SysTick exception at a fixed time interval (typically 10 ms). 9.8 I/O configuration The IOCON block controls the configuration of the I/O pins. Each digital or mixed digital/analog pin with the PIO0_n designator in Table 4 can be configured as follows: • Enable or disable the weak internal pull-up and pull-down resistors. • Select a pseudo open-drain mode. The input cannot be pulled up above VDD. The pins are not 5 V tolerant when VDD is grounded. • Program the input glitch filter with different filter constants using one of the IOCON divided clock signals (IOCONCLKCDIV, see Figure 12 “LPC804 clock generation”). You can also bypass the glitch filter. • Invert the input signal. • Hysteresis can be enabled or disabled. • The switch matrix setting enables the analog input mode on pins with analog and digital functions. Enabling the analog mode disconnects the digital functionality. • The LPC804 uses a dual voltage I/O feature. The pins on one side of the package are supplied by VDDIO and the pins on the other side are supplied by VDD. Each of these two supplies can be connected to different voltages within the allowed Vdd range. This feature allows the device to level-shift signals from one off-chip voltage domain to another. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 18 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller • The switch matrix provides level shifter functionality to allow up to two selected signals to be routed from user-selected pins in one voltage domain to selected pins in the alternate domain. This feature can also be used on a single supply device if voltage level shifting is not required. Remark: The functionality of each I/O pin is flexible and is determined entirely through the switch matrix. See Section 9.9 for details. 9.8.1 Standard I/O pad configuration Figure 10 shows the possible pin modes for standard I/O pins with analog input function: • • • • • • Digital output driver with configurable open-drain output. Digital input: Weak pull-up resistor (PMOS device) enabled/disabled. Digital input: Weak pull-down resistor (NMOS device) enabled/disabled. Digital input: Repeater mode enabled/disabled. Digital input: Programmable input digital filter selectable on all pins. Analog input: Selected through the switch matrix. VDD VDD open-drain enable strong pull-up output enable ESD data output PIN strong pull-down pin configured as digital output driver ESD VSS VDD weak pull-up pull-up enable weak pull-down repeater mode enable pull-down enable data input pin configured as digital input select data inverter SWM PINENABLE for analog input analog input transmission gate pin configured as analog input aaa-028401 Fig 10. Standard I/O pad configuration LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 19 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.9 Switch Matrix (SWM) The switch matrix controls the function of each digital or mixed analog/digital pin in a highly flexible way by allowing to connect many functions like the USART, SPI, CTimer, Capacitive Touch, and I2C functions to any pin that is not power or ground. These functions are called movable functions and are listed in Table 5. Functions that need specialized pads can be enabled or disabled through the switch matrix. These functions are called fixed-pin functions and cannot move to other pins. The fixed-pin functions are listed in Section 7.2 “Pin description”. If a fixed-pin function is disabled, any other movable function can be assigned to this pin. 9.10 Fast General-Purpose parallel I/O (GPIO) Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be set or cleared in one write operation. LPC804 use accelerated GPIO functions: • GPIO registers are on the Arm Cortex-M0+ IO bus for fastest possible single-cycle I/O timing, allowing GPIO toggling with rates of up to 7 MHz. • An entire port value can be written in one instruction. • Mask, set, and clear operations are supported for the entire port. All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the switch matrix. Therefore each GPIO port pin is assigned to one specific pin and cannot be moved to another pin. Except for pins SWDIO/PIO0_2, SWCLK/PIO0_3, and RESET/PIO0_5, the switch matrix enables the GPIO port pin function by default. 9.10.1 Features • Bit level port registers allow a single instruction to set and clear any number of bits in one write operation. • Direction control of individual bits. • All I/O default to GPIO inputs with internal pull-up resistors enabled after reset. • Pull-up/pull-down configuration, repeater, and open-drain modes can be programmed through the IOCON block for each GPIO pin (see Figure 10). • Direction (input/output) can be set and cleared individually. • Pin direction bits can be toggled. 9.11 Pin interrupt The pin interrupt block configures up to eight pins from all digital pins for providing eight external interrupts connected to the NVIC. Any digital pin, independently of the function selected through the switch matrix, can be configured through the SYSCON block as input to the pin interrupt. The registers that control the pin interrupt are on the IO+ bus for fast single-cycle access. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 20 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.11.1 Features • Pin interrupts – Up to eight pins can be selected from all digital pins as edge- or level-sensitive interrupt requests. Each request creates a separate interrupt in the NVIC. – Edge-sensitive interrupt pins can interrupt on rising or falling edges or both. – Level-sensitive interrupt pins can be HIGH- or LOW-active. – Pin interrupts can wake up the LPC804 from sleep mode, deep-sleep mode, and power-down mode. 9.12 USART0/1 All USART functions are movable functions and are assigned to pins through the switch matrix. 9.12.1 Features • Maximum bit rates of 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in synchronous mode for USART functions connected to all digital pins. • 7, 8, or 9 data bits and 1 or 2 stop bits • Synchronous mode with master or slave operation. Includes data phase selection and continuous clock option. • Multiprocessor/multidrop (9-bit) mode with software address compare. (RS-485 possible with software address detection and transceiver direction control.) • Parity generation and checking: odd, even, or none. • One transmit and one receive data buffer. • RTS/CTS for hardware signaling for automatic flow control. Software flow control can be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an RTS output. • • • • • • Received data and status can optionally be read from a single register Break generation and detection. Receive data is 2 of 3 sample "voting". Status flag set when one sample differs. Built-in Baud Rate Generator. A fractional rate divider is shared among all UARTs. Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS detect, and receiver sample noise detected. • Separate data and flow control loopback modes for testing. • Baud rate clock can also be output in asynchronous mode. 9.13 SPI0 All SPI functions are movable functions and are assigned to pins through the switch matrix. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 21 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.13.1 Features • Maximum data rates of up to 15 Mbit/s in master mode and up to 20 Mbit/s in slave mode for SPI functions connected to all digital pins. • Data frames of 1 to 16 bits supported directly. Larger frames supported by software. • Master and slave operation. • Data can be transmitted to a slave without the need to read incoming data, which can be useful while setting up an SPI memory. • Control information can optionally be written along with data, which allows very versatile operation, including “any length” frames. • One Slave Select input/output with selectable polarity and flexible usage. Remark: Texas Instruments SSI and National Microwire modes are not supported. 9.14 I2C-bus interface (I2C0 and I2C1) The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line (SCL) and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master. 9.14.1 Features • • • • • I2C0 and I2C1 support standard and fast mode with data rates of up to 400 kbit/s. Independent Master, Slave, and Monitor functions. Supports both Multi-master and Multi-master with Slave functions. Multiple I2C slave addresses supported in hardware. One slave address can be selectively qualified with a bit mask or an address range in order to respond to multiple I2C bus addresses. • 10-bit addressing supported with software assist. • Supports SMBus. 9.15 Capacitive Touch Interface The Capacitive Touch interface is designed to handle up to five capacitive buttons in different sensor configurations, such as slider, and button matrix. It operates in sleep, deep sleep, and power-down modes, allowing very low power performance. The Capacitive Touch module measures the change in capacitance of an electrode plate when an earth-ground connected object (for example, finger) is brought within close proximity. 9.16 CTimer 9.16.1 General-purpose 32-bit timers/external event counter The LPC804 has one general-purpose 32-bit timer/counter. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 22 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The timer/counter also includes three capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 9.16.1.1 Features • A 32-bit timer/counter with a programmable 32-bit prescaler. • Counter or timer operation. • Up to three 32-bit captures can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. The number of capture inputs for each timer that are actually available on device pins can vary by device. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. – Shadow registers are added for glitch-free PWM output. • For each timer, up to 4 external outputs corresponding to match registers with the following capabilities (the number of match outputs for each timer that are actually available on device pins can vary by device): – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. • The timer and prescaler may be configured to be cleared on a designated capture event. This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge. • Up to 4 match registers can be configured for PWM operation, allowing up to 3 single edged controlled PWM outputs. (The number of match outputs for each timer that are actually available on device pins can vary by device.) 9.17 Multi-Rate Timer (MRT) The Multi-Rate Timer (MRT) provides a repetitive interrupt timer with two channels. Each channel can be programmed with an independent time interval, and each channel operates independently from the other channels. 9.17.1 Features • 31-bit interrupt timer • Two channels independently counting down from individually set values • Bus stall, repeat and one-shot interrupt modes LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 23 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.18 Windowed WatchDog Timer (WWDT) The watchdog timer resets the controller if software fails to service the watchdog timer periodically within a programmable time window. 9.18.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • • • • Incorrect feed sequence causes reset or interrupt if enabled. Flag to indicate watchdog reset. Programmable 24-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK)  256  4) to (Tcy(WDCLK)  224  4) in multiples of Tcy(WDCLK)  4. • The WatchDog Clock (WDCLK) is generated by the dedicated watchdog oscillator (WDOSC). 9.19 Self-Wake-up Timer (WKT) The self-wake-up timer is a 32-bit, loadable down counter. Writing any non-zero value to this timer automatically enables the counter and launches a count-down sequence. When the counter is used as a wake-up timer, this write can occur prior to entering a reduced power mode. 9.19.1 Features • 32-bit loadable down counter. Counter starts automatically when a count value is loaded. Time-out generates an interrupt/wake up request. • The WKT supports three clock sources: an external clock on the WKTCLKIN pin, the low-power oscillator, and the FRO. The low-power oscillator can be used as the clock source in sleep, deep-sleep, and power-down modes. • The WKT can be used for waking up the part from any reduced power mode or for general-purpose timing. 9.20 Programmable Logic Unit (PLU) The PLU is comprised of 26 5-input LUT elements. Each LUT element contains a 32-bit truth table (look-up table) register and a 32:1 multiplexer. During operation, the five LUT inputs control the select lines of the multiplexer. This structure allows any desired logical combination of the five LUT inputs. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 24 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.20.1 Features • The PLU is used to create small combinatorial and/or sequential logic networks including simple state machines. • The PLU is comprised of an array of 26 inter-connectable, 5-input Look-up Table (LUT) elements, and four flip-flops. • Eight primary outputs can be selected using a multiplexer from among all of the LUT outputs and the four flip-flops. • An external clock to drive the four flip-flops must be applied to the PLU_CLKIN pin if a sequential network is implemented. • Programmable logic can be used to drive on-chip inputs/triggers through external pin-to-pin connections. • A tool suite is provided to facilitate programming of the PLU to implement the logic network described in a Verilog RTL design. Remark: PLU cannot be used to wake-up from sleep, deep-sleep, power-down, and deep power-down modes. 9.21 Analog comparator (ACMP) The analog comparator with selectable hysteresis can compare voltage levels on external pins and internal voltages. After power-up and after switching the input channels of the comparator, the output of the voltage ladder must be allowed to settle to its stable value before it can be used as a comparator reference input. Settling times are given in Table 27. The analog comparator output is a movable function and is assigned to a pin through the switch matrix. The comparator inputs and the voltage reference are enabled through the switch matrix. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 25 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller VDD COMPARATOR ANALOG BLOCK COMPARATOR DIGITAL BLOCK ACMPVREF 4 32 sync comparator level ACMP_O, ADC trigger edge detect comparator edge NVIC DACOUT_0 internal voltage reference ACMP_I[5:1] 4 aaa-027485 Fig 11. Comparator block diagram 9.21.1 Features • Selectable 0 mV, 10 mV ( 5 mV), and 20 mV ( 10 mV), 40 mV ( 20 mV) input hysteresis. • Two selectable external voltages (VDD or ACMPVREF); fully configurable on either positive or negative input channel. • Internal voltage reference from band gap selectable on either positive or negative input channel. • 32-stage voltage ladder with the internal reference voltage selectable on either the positive or the negative input channel. • Voltage ladder source voltage is selectable from an external pin or the main 3.3 V supply voltage rail. • Voltage ladder can be separately powered down for applications only requiring the comparator function. • Interrupt output is connected to NVIC. • Comparator level output is connected to output pin ACMP_O. • One comparator output is internally collected to the ADC trigger input multiplexer. 9.22 Analog-to-Digital Converter (ADC) The ADC supports a resolution of 12 bit and fast conversion rates of up to 480 KSamples/s. Sequences of analog-to-digital conversions can be triggered by multiple sources. Possible trigger sources are the pin triggers, the analog comparator output, and the Arm TXEV. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 26 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller The ADC includes a hardware threshold compare function with zero-crossing detection. Remark: For best performance, select VREFP and VREFN at the same voltage levels as VDD and VSS. When selecting VREFP and VREFN different from VDD and VSS, ensure that the voltage midpoints are the same: (VREFP-VREFN)/2 + VREFN = VDD/2 9.22.1 Features • • • • • • • 12-bit successive approximation analog to digital converter. 12-bit conversion rate of up to 480 KSamples/s. Two configurable conversion sequences with independent triggers. Optional automatic high/low threshold comparison and zero-crossing detection. Power-down mode and low-power operating mode. Measurement range VREFN to VREFP (not to exceed VDD voltage level). Burst conversion mode for single or multiple inputs. 9.23 Digital-to-Analog Converter (DAC) The DAC supports a resolution of 10 bits. Conversions can be triggered by an external pin input or an internal timer. The DAC includes an optional automatic hardware shut-off feature, which forces the DAC output voltage to zero while a HIGH level on the external DAC_SHUTOFF pin is detected. 9.23.1 Features • 10-bit digital-to-analog converter. • Internal timer or pin external trigger for staged, jitter-free DAC conversion sequencing. • Automatic hardware shut-off triggered by an external pin. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 27 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.24 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used. To save system power and bus bandwidth, the CRC engine supports DMA transfers. 9.24.1 Features • Supports three common polynomials CRC-CCITT, CRC-16, and CRC-32. – CRC-CCITT: x16 + x12 + x5 + 1 – CRC-16: x16 + x15 + x2 + 1 – CRC-32: x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 • Bit order reverse and 1’s complement programmable setting for input data and CRC sum. • Programmable seed number setting. • Supports CPU PIO or DMA back-to-back transfer. • Accept any size of data width per write: 8, 16 or 32-bit. – 8-bit write: 1-cycle operation. – 16-bit write: 2-cycle operation (8-bit x 2-cycle). – 32-bit write: 4-cycle operation (8-bit x 4-cycle). LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 28 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.25 Clocking and power control SYSAHBCLKCTRL (one bit per destination) fro to AHB peripherals, AHB matrix, memories, etc. 00 clk_in main_clk 01 lposc_clk main_clk Divider 10 fro_div 11 to CPU (1) SYSAHBCLKDIV[7:0] Main clock select MAINCLKSEL[1:0] fro 000 main_clk fro_div fro 000 main_clk “none” 010 clk_in lposc_clk “none” lposc_clk 001 CLKOUT Divider “none” CLKOUT 001 to CAPT 011 100 111 011 100 111 CAPT clock select CAPTCLKSEL[2:0] CLKOUTDIV[7:0] fro CLKOUT select CLKOUTSEL[2:0] 00 clk_in 01 “none” 11 ADC Clock Divider to ADC ADC clock select ADCCLKDIV ADCCLKSEL[1:0] aaa-040025 Fig 12. LPC804 clock generation LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 29 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller One for each USART (USART0 and USART1) fro main_clk frg0clk 000 SYSAHBCLKCTRL0[USARTn] 001 010 fro_div to USARTn 100 “none” 111 UARTn clock select UARTnCLKSEL[2:0] fro 00 main_clk “none” 01 Fractional Rate Divider 0 (FRG0) fro 11 FRG0 clock select FRG0CLKSEL[1:0] main_clk FRG0DIV, FRG0MULT frg0clk 000 001 010 fro_div to I2Cn 100 “none” 111 I2Cn clock select I2CnCLKSEL[2:0] fro main_clk frg0clk fro_div “none” 000 001 010 100 to SPIn 111 SPln clock select SPInCLKSEL[2:0] aaa-029249 Fig 13. LPC804 clock generation (continued) LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 30 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller WKT SYSCON system clock WKT registers SYSAHBCLKCTRL (WKT clock enable) CTRL 12 MHz FRO div 750 kHz 1 MHz PDRUNCFG (enable FRO and FRO output FRO_PD, FROOUT_PD) 32-bit counter COUNT CLKSEL SET_EXTCLK LPOSC PDRUNCFG aaa-029250 WKTCLKIN Fig 14. LPC804 WKT clocking fro Divide by 2 FRO OSCILLATOR 30/24/18 MHz (default = 24 MHz) 15/12/9 MHz (default = 12 MHz) set_fro_frequency() API Divide by 2 fro_div aaa-029251 Fig 15. LPC804 FRO subsystem Table 6. Clocking diagram signal name descriptions Name Description clk_in The internal clock that comes from the main CLK_IN pin function. That function must be connected to the pin by selecting it in the SWM block. frg_clk The output of the Fractional Rate Generator. The FRG and its source selection are shown in Figure 13. fro_div Divided output of the currently selected on-chip FRO oscillator. See Figure 15. fro The output of the currently selected on-chip FRO oscillator. See Figure 15. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 31 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 6. Clocking diagram signal name descriptions Name Description main_clk The main clock used by the CPU and AHB bus, and potentially many others. The main clock and its source selection are shown in Figure 12. “none” A tied-off source that should be selected to save power when the output of the related multiplexer is not used. lposc_clk The output of the 1 MHz low power oscillator. It must also be enabled in the PDRUNCFG0 register. 9.25.1 Internal oscillators The LPC804 include two independent oscillators: 1. Free Running Oscillator. 2. Low power oscillator. Following reset, the LPC804 operates from the FRO until switched by software allowing the part to run without any external clock and the bootloader code to operate at a known frequency. See Figure 12 for an overview of the LPC804 clock generation. 9.25.1.1 Free Running Oscillator (FRO) The FRO provides the default clock at reset and provides a clean system clock shortly after the supply pins reach operating voltage. • This oscillator provides a selectable 15 MHz, 12 MHz, and 9 MHz outputs that can be used as a system clock. Also, these outputs can be divided down to 7.5 MHz, 6 MHz, and 4.5 MHz for system clock. • The FRO is trimmed to ±1 % accuracy over the entire voltage and temperature range of 0 C to 70 C. • By default, the FRO output frequency is default system (CPU) clock frequency of 12 MHz. 9.25.1.2 Low Power Oscillator (LPOsc) The LPOsc is an independent oscillator which can be used as a system clock. The frequency of the LPCOsc is 1 MHz. 9.25.2 Clock input An external clock source can be supplied on the selected CLKIN pin. When selecting a clock signal for the CLKIN pin, follow the specifications for digital I/O pins in Table 12 “Static characteristics, supply pins” and Table 18 “Dynamic characteristics: I/O pins[1]”. The maximum frequency for both clock signals is 15 MHz. 9.25.3 Clock output The LPC804 features a clock output function that routes any oscillator or the main clock can be selected to the CLKOUT function. The CLKOUT function can be connected to any digital pin through the switch matrix. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 32 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.25.4 Power control The LPC804 supports the Arm Cortex-M0+ sleep mode. The CPU clock rate may also be controlled as needed by changing clock sources, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, a register is provided for shutting down the clocks to individual on-chip peripherals, allowing to fine-tune power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Selected peripherals have their own clock divider which provides even better power control. 9.25.4.1 Sleep mode When sleep mode is entered, the clock to the core is stopped. Resumption from the sleep mode does not need any special sequence but re-enabling the clock to the Arm core. In sleep mode, execution of instructions is suspended until either a reset or interrupt occurs. Peripheral functions continue operation during sleep mode and may generate interrupts to cause the processor to resume execution. sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 9.25.4.2 Deep-sleep mode In deep-sleep mode, the LPC804 core is in sleep mode and all peripheral clocks and all clock sources are off except for the FRO or low-power oscillator if selected. The FRO output is disabled. In addition, all analog blocks are shut down and the flash is in standby mode. In deep-sleep mode, the application can keep the low power oscillator and the BOD circuit running for self-timed wakeup and BOD protection. The LPC804 can wake up from deep-sleep mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive Touch, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode), or the I2C blocks (in slave mode). Any interrupt used for waking up from deep-sleep mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. Deep-sleep mode saves power and allows for short wake-up times. 9.25.4.3 Power-down mode In power-down mode, the LPC804 is in sleep mode and all peripheral clocks and all clock sources are off except for low-power oscillator if selected. In addition, all analog blocks and the flash are shut down. In power-down mode, the application can keep the low-power oscillator and the BOD circuit running for self-timed wake up and BOD protection. The LPC804 can wake up from power-down mode via a reset, digital pins selected as inputs to the pin interrupt block, a watchdog timer interrupt, an interrupt from Capacitive Touch, or an interrupt from the USART (if the USART is configured in synchronous slave mode), the SPI (in slave mode), or the I2C blocks (in slave mode). Any interrupt used for waking up from power-down mode must be enabled in one of the SYSCON wake-up enable registers and the NVIC. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 33 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Power-down mode reduces power consumption compared to deep-sleep mode at the expense of longer wake-up times. 9.25.4.4 Deep power-down mode In deep power-down mode, power is shut off to the entire chip except for the WAKEUP pins. The LPC804 can wake up from deep power-down mode via eight WAKEUP pins. See Section 9.19. Five general-purpose registers are available to store information during deep power-down mode. The LPC804 can be prevented from entering deep power-down mode by setting a lock bit in the PMU block. Locking out deep power-down mode enables the application to keep the watchdog timer or the BOD running at all times. When entering deep power-down mode, an external pull-up resistor is required on the WAKEUP pins to hold it HIGH. Table 7. Peripheral configuration in reduced power modes Peripheral Sleep mode Deep-sleep mode Power-down mode Deep power-down mode FRO software configurable on off off FRO output software configurable off off off Flash software configurable standby off off BOD software configurable software configurable software configurable off LPOsc/WWDT software configurable software configurable software configurable off Digital peripherals software configurable off off Wake-up buffers software configurable (cannot be used as wake-up source) software configurable (cannot be used as wake-up source) software configurable software configurable (cannot be used as wake-up source) ADC software configurable off off off DAC software configurable off off off Capacitive Touch software configurable software configurable software configurable off WKT/low-power oscillator software configurable software configurable software configurable off Comparator software configurable off off off PLU off off off off LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 off © NXP Semiconductors N.V. 2021. All rights reserved. 34 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 8. Wake-up sources for reduced power modes power mode Wake-up source Conditions Sleep Any interrupt Enable interrupt in NVIC. Deep-sleep and power-down Pin interrupts Enable pin interrupts in NVIC and STARTERP0 registers. BOD interrupt BOD reset WWDT interrupt WWDT reset Self-Wake-up Timer (WKT) time-out Interrupt from USART/SPI/I2C peripheral Interrupt from Capacitive Touch peripheral Deep power-down WAKEUP pins • • • • • • • • • • • • • • Enable interrupt in NVIC and STARTERP1 registers. • • • • • • Select low-power clock for WKT clock in the WKT CTRL register. • • • • • Enable interrupt in NVIC and STARTERP1 registers. Enable interrupt in BODCTRL register. BOD powered in PDSLEEPCFG register. Enable reset in BODCTRL register. BOD powered in PDSLEEPCFG register. Enable interrupt in NVIC and STARTERP1 registers. WWDT running. Enable WWDT in WWDT MOD register and feed. Enable interrupt in WWDT MOD register. LPOsc powered in PDSLEEPCFG register. WWDT running. Enable reset in WWDT MOD register. LPOsc powered in PDSLEEPCFG register. Enable interrupt in NVIC and STARTERP1 registers. Enable low-power oscillator in the LPOSCCLKEN register in the SYSCON block. Start the WKT by writing a time-out value to the WKT COUNT register. Enable interrupt in NVIC and STARTERP1 registers. Enable USART/I2C/SPI interrupts. Provide an external clock signal to the peripheral. Configure the USART in synchronous slave mode and I2C and SPI in slave mode. Enable the Capacitive Touch interrupt. Switch FCLK clock source to the LPOsc. Set Capacitive Touch registers. Provide a touch event to the peripheral. Enable the WAKEUP function in the WUENAREG register in the PMU. 9.25.5 Wake-up process The LPC804 begin operation at power-up by using the FRO as the clock source allowing chip operation to resume quickly. If LPOsc or external clock sources are needed by the application, software must enable these features and wait for them to stabilize before they are used as a clock source. 9.26 System control 9.26.1 Reset Reset has four sources on the LPC804: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by any source, once the operating voltage attains a usable level, starts the FRO and initializes the flash controller. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 35 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller A LOW-going pulse as short as 50 ns resets the part. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the boot block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS aaa-004613 Fig 16. Reset pad configuration 9.26.2 Brownout detection The LPC804 includes one reset level and three interrupt levels for monitoring the voltage on the VDD pin. If this voltage falls below one of the selected levels, the BOD asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated status register. One threshold level can be selected to cause a forced reset of the chip. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 36 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.26.3 Code security (Code Read Protection - CRP) CRP provides different levels of security in the system so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted. Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands are not affected by the CRP. In addition, ISP entry via the ISP entry pin can be disabled without enabling CRP. For details, see the LPC804 user manual. There are three levels of Code Read Protection: 1. CRP1 disables access to the chip via the SWD and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased. 2. CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands. 3. Running an application with level CRP3 selected, fully disables any access to the chip via the SWD pins and the ISP. This mode effectively disables ISP override using the ISP entry pin as well. If necessary, the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART. CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. In addition to the three CRP levels, sampling of the ISP entry pin for valid user code can be disabled. For details, see the LPC804 user manual. 9.26.4 APB interface The APB peripherals are located on one APB bus. 9.26.5 AHBLite The AHBLite connects the CPU bus of the Arm Cortex-M0+ to the flash memory, the main static RAM, the ROM, and the APB peripherals. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 37 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 9.27 Emulation and debugging Debug functions are integrated into the Arm Cortex-M0+. Serial wire debug functions are supported in addition to a standard JTAG boundary scan. The Arm Cortex-M0+ is configured to support up to four breakpoints and two watch points. The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the Arm SWD debug (RESET = HIGH). The Arm SWD debug port is disabled while the LPC804 is in reset. The JTAG boundary scan pins are selected by hardware when the part is in boundary scan mode. See Table 4. To perform boundary scan testing, follow these steps: 1. Erase any user code residing in flash. 2. Power up the part with the RESET pin pulled HIGH externally. 3. Wait for at least 250 s. 4. Pull the RESET pin LOW externally. 5. Perform boundary scan operations. 6. Once the boundary scan operations are completed, assert the TRST pin to enable the SWD debug mode, and release the RESET pin (pull HIGH). Remark: The JTAG interface cannot be used for debug purposes. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 38 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 10. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions [2] VDD supply voltage (core and external rail) Vref reference voltage on pin VREFP input voltage 5 V tolerant I/O pins; VDD  1.71 V VI analog input voltage IDD supply current ISS Ilatch I/O latch-up current Unit 0.5 +4.6 V 0.5 VDD V 0.5 +5.4 V [5] 0.5 +3.6 V [6][7] 0.5 +4.6 V per supply pin (TSSOP20) - 18 mA per supply pin (TSSOP24) - 22 per supply pin (HVQFN33) - 30 per ground pin (TSSOP20) - 40 per ground pin (TSSOP24) - 45 per ground pin (HVQFN33) - 50 (0.5VDD) < VI < (1.5VDD); - 100 mA 65 +150 C - 150 C - 0.36 W on digital pins configured for an analog function ground current Max [3][4] 3 V tolerant I/O pin ACMPVREF VIA Min [8] mA Tj < 125 C [9] Tstg storage temperature Tj(max) maximum junction temperature Ptot(pack) total power dissipation (per package) LPC804 Product data sheet TSSOP20, based on package heat transfer, not device power consumption All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 [11] © NXP Semiconductors N.V. 2021. All rights reserved. 39 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 9. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Vesd Parameter electrostatic discharge voltage Conditions Min Max Unit TSSOP20, based on package heat transfer, not device power consumption [12] - 0.26 W TSSOP24, based on package heat transfer, not device power consumption [11] - 0.34 W TSSOP24, based on package heat transfer, not device power consumption [12] - 0.26 W HVQFN33, based on package heat transfer, not device power consumption [11] - 0.93 W HVQFN33, based on package heat transfer, not device power consumption [12] - 0.34 W WLCSP20, based on package heat transfer, not device power consumption [11] - 0.8 W WLCSP20, based on package heat transfer, not device power consumption [12] - 0.3 W human body model; all pins [10] - 2000 V [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Maximum/minimum voltage above the maximum operating voltage (see Table 12) and below ground that can be applied for a short time (< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device. [3] Applies to all 5 V tolerant I/O pins except the 3 V tolerant pin PIO0_7. [4] Including the voltage on outputs in 3-state mode. [5] VDD present or not present. [6] An ADC input voltage above 3.6 V can be applied for a short time without leading to immediate, unrecoverable failure. Accumulated exposure to elevated voltages at 4.6 V must be less than 106 s total over the lifetime of the device. Applying an elevated voltage to the ADC inputs for a long time affects the reliability of the device and reduces its lifetime. [7] If the comparator is configured with the common mode input VIC = VDD, the other comparator input can be up to 0.2 V above or below VDD without affecting the hysteresis range of the comparator function. [8] It is recommended to connect an overvoltage protection diode between the analog input pin and the voltage supply pin. [9] Dependent on package type. [10] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. [11] JEDEC (4.5 in  4 in); still air. [12] Single layer (4.5 in  3 in); still air. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 40 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 11. Thermal characteristics The average chip junction temperature, Tj (C), can be calculated using the following equation: T j = T amb +  P D  R th  j – a   (1) • Tamb = ambient temperature (C), • Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) • PD = sum of internal and I/O power dissipation The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 10. Symbol Thermal resistance Parameter Conditions Max/min Unit TSSOP20 package Rth(j-a) Rth(j-c) thermal resistance from junction-to-ambient JEDEC (4.5 in  4 in); still air 108  15 % C/W single-layer (4.5 in  3 in); still 151  15 % air C/W 24  15 % thermal resistance from junction-to-case C/W TSSOP24 package Rth(j-a) Rth(j-c) thermal resistance from junction-to-ambient JEDEC (4.5 in  4 in); still air 114  15 % C/W single-layer (4.5 in  3 in); still 153  15 % air C/W 31  15 % C/W thermal resistance from junction-to-ambient JEDEC (4.5 in  4 in); still air 42  15 % C/W single-layer (4.5 in  3 in); still 114  15 % air C/W thermal resistance from junction-to-case 21  15 % thermal resistance from junction-to-case HVQFN33 package Rth(j-a) Rth(j-c) C/W WLCSP20 package Rth(j-a) Rth(j-c) LPC804 Product data sheet thermal resistance from junction-to-ambient JEDEC (4.5 in  4 in); still air 56.5  15 % C/W single-layer (4.5 in  3 in); still 148  15 % air C/W 0.7  15 % C/W thermal resistance from junction-to-case All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 41 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12. Static characteristics 12.1 General operating conditions Table 11. General operating conditions Tamb = −40 °C to +105 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit fclk clock frequency internal CPU/system clock - - 15 MHz VDD supply voltage (core and external rail) 1.71 - 3.6 V For ADC operations 2.5 - 3.6 V For DAC operations 2.7 - 3.6 V 1.71 - 3.6 V For ADC operations 2.5 - 3.6 V For DAC operations 2.7 - 3.6 V on pin VREFP 2.5 - VDD V VDDIO I/O rail ADC positive reference voltage Vref Pin capacitance Cio input/output capacitance pins with analog and digital functions [2] - - 7.1 pF pins with digital functions only [2] - - 2.8 pF [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), nominal supply voltages. [2] Including bonding pad capacitance. Based on simulation, not tested in production. 12.2 Power consumption Power measurements in active, sleep, deep-sleep, and power-down modes were performed under the following conditions: • Configure all pins as GPIO with pull-up resistor disabled in the IOCON block. • Configure GPIO pins as outputs using the GPIO DIR register. • Write 1 to the GPIO CLR register to drive the outputs LOW. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 42 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller Table 12. Static characteristics, supply pins Tamb = −40 °C to +105 °C, unless otherwise specified. Symbol Parameter Conditions Min IDD supply current Active mode; code Typ[1][2] Max[9] Unit while(1){} executed from flash; system clock = 1 MHz VDD = 3.3 V [3][5][6][10] 0.5 - mA system clock = 9 MHz VDD = 3.3 V [3][4][5][6] 0.8 - mA system clock = 12 MHz VDD = 3.3 V [3][4][5][6] - 1.0 - mA system clock = 15 MHz VDD = 3.3 V [3][4][5][6] - 1.3 - mA Sleep mode system clock = 9 MHz VDD = 3.3 V [3][4][5][6] system clock = 12 MHz VDD = 3.3 V [3][4][5][6] - 0.5 - mA system clock = 15 MHz VDD = 3.3 V [3][4] - 0.6 - mA 100 175 A - 240 A 6 14 A - 75 A supply current Deep-sleep mode; VDD = 3.3 V; IDD 0.4 [5][6] [3][7] - Tamb = 25 C Tamb = 105 C - supply current Power-down mode; VDD = 3.3 V IDD [3][7] - Tamb = 25 C Tamb = 105 C - supply current Deep power-down mode; VDD = 3.3 V; IDD [8] Tamb = 25 C - 0.15 0.5 A Tamb = 105 C - - 7 A [1] Typical ratings are not guaranteed. The values listed are for room temperature (25 C), VDD = 3.3 V. [2] Characterized through bench measurements using typical samples. [3] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [4] FRO enabled. [5] BOD disabled. [6] All peripherals disabled in the SYSAHBCLKCTRL register. Peripheral clocks disabled in system configuration block. [7] All oscillators and analog blocks turned off. [8] WAKEUP function pin pulled HIGH externally. [9] Tested in production, VDD = 3.6 V. [10] LPOsc enabled, FRO disabled. LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 43 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller aaa-029007 180 IDD (μA) 160 3.6 V 3.0 V 2.7 V 2.0 V 1.8 V 1.7 V 140 120 100 80 -40 -10 20 50 80 Temperature (°C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register. Fig 17. Deep-sleep mode: Typical supply current IDD versus temperature for different supply voltages VDD aaa-029008 30 IDD (μA) 25 20 3.6 V 3.0 V 1.8 V 1.7 V 15 10 5 0 -40 -10 20 50 80 temperature (°C) 110 Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register. Fig 18. Power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 44 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller aaa-029006 1.5 IDD (μA) 1.3 1 3.6 V 3.0 V 1.8 V 1.7 V 2.7 V 0.8 0.5 0.3 0 -40 -10 20 50 80 Temperature (°C) 110 WKT not running. Fig 19. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD LPC804 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 45 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12.2.1 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG. and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code accessing the peripheral is executed. Measured on a typical sample at Tamb = 25 C. The supply currents are shown for system clock frequencies of 12 MHz and 15 MHz. Table 13. Power consumption for individual analog and digital blocks Peripheral Typical supply current in μA Notes System clock frequency = n/a 12 MHz 15 MHz FRO 74 - - FRO = 12MHz. FRO output disabled. BOD 39 - - Independent of main clock frequency. Flash 80 - - - LPOsc 1 - - FRO; independent of main clock frequency. GPIO + pin interrupt - 40 54 GPIO pins configured as outputs and set to LOW. Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register. SWM - 24 30 - IOCON - 28 36 - CTimer - 28 37 - MRT - 45 56 - WWDT - 31 41 - I2C0 - 44 58 - I2C1 - SPI0 - 33 42 - USART0 - 39 46 - USART1 - 40 50 - Comparator ACMP - 36 46 - ADC - 61 78 Digital controller only. Analog portion of the ADC disabled in the PDRUNCFG register. - 61 78 Combined analog and digital logic. ADC enabled in the PDRUNCFG register and LPWRMODE bit set to 1 in the ADC CTRL register (ADC in low-power mode). - 61 78 Combined analog and digital logic. ADC enabled in the PDRUNCFG register and LPWRMODE bit set to 0 in the ADC CTRL register (ADC powered). DAC - 29 35 Capacitive Touch - 22 26 PLU - 118 149 CRC - 37 50 LPC804 Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 2.0 — 21 September 2021 © NXP Semiconductors N.V. 2021. All rights reserved. 46 of 87 LPC804 NXP Semiconductors 32-bit Arm Cortex-M0+ microcontroller 12.3 Pin characteristics Table 14. Static characteristics, electrical pin characteristics Tamb = −40 °C to +105 °C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit Standard port pins configured as digital pins, RESET IIL LOW-level input current VI = 0 V; on-chip pull-up resistor disabled - 0.5 10[2] nA IIH HIGH-level input current VI = VDD; on-chip pull-down resistor disabled - 0.5 10[2] nA IOZ OFF-state output current VO = 0 V; VO = VDD; on-chip pull-up/down resistors disabled - 0.5 10[2] nA VI input voltage VDD  1.71 V; 5 V tolerant pins except PIO0_7 0 - 5.4 V VDD = 0 V 0 - 3.6 V VO output voltage output active 0 - VDD V VIH HIGH-level input voltage 0.7VDD - - V VIL LOW-level input voltage - - 0.3VDD V Vhys hysteresis voltage - 0.4 - V VOH HIGH-level output voltage VOL IOH LOW-level output voltage HIGH-level output current IOH = 4 mA; 2.5 V