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QorIQ Communications Platforms P Series QorIQ P1011 and P1020 communications processors Overview The P1011 and P1020 processors are ideally The P1011 and P1020 platforms are software Freescale QorIQ communications platforms are suited for multiservice gateways, Ethernet switch compatible, and both feature the e500 Power controllers, wireless LAN access points and high- Architecture core and peripherals, as well performance general-purpose control processor as being fully software compatible with the using high-performance Power Architecture applications with tight thermal constraints. earlier PowerQUICC processors. This enables cores, QorIQ platforms enable a new era of The P1011 and P1020 processors are networking innovation where the reliability, pin-compatible with the QorIQ P2 platform security and quality of service for every products, offering a four-chip range of cost- connection matters. effective solutions. Scaling from a single core the next-generation evolution of our leading PowerQUICC communications processors. Built ® QorIQ P1011 and P1020 Communications Processors The QorIQ P1 family, which includes the P1011 customers to create a product with multiple performance points from a single board design. The P1020 dual-core processor supports both symmetric and asymmetric processing, enabling customers to further optimize their design with at 533 MHz (P1011) to a dual core at the same applications running on each core 1.2 GHz per core (P2020), the combined or serialize their application using the cores for QorIQ platforms offer an impressive 4.5x different processing tasks. aggregate frequency range. and P1020 communications processors, offers the value of smart integration and efficient power for a wide variety of applications in the networking, telecom, defense and industrial markets. Based on 45 nm technology for low power, the P1011 and P1020 processors provide both single- and dual-core options, from and P1011 Block Diagram QorIQ QorIQP1020 P1011 and P1020 Block Diagram Not on P1011 Security Acceleration XOR Power Architecture® e500 Core 32 KB 32 KB L1 I Cache L1 D Cache 256 KB L2 Cache Power Architecture e500 Core 32 KB 32 KB L1 I Cache L1 D Cache 533–800 MHz, along with advanced security and a rich set of interfaces. DDR2/DDR3 SDRAM Controller DUART, 2x I2C, Timers, Interrupt Control, SD/MMC, SPI, 2x USB 2.0/ULPI Coherency Module Enhanced Local Bus Controller (eLBC) System Bus TDM 3x Gigabit Ethernet On-Chip Network 2x PCI Express® 4-ch. DMA Controller 4-lane SerDes Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Accelerators and Memory Control Networking Elements Basic Peripherals and Interconnect The P1011 and P1020 processors have an available junction temperature range of –40 ºC advanced set of features for ease of use. The to +125 ºC, the devices can be used in power- 256 KB L2 cache offers incremental configuration sensitive defense and industrial applications, to partition the cache between the two cores or and outdoor environments less protected from to configure it as SRAM or stashing memory. the environment. The devices’ primary The integrated security engine supports the target applications are networking and cryptographic algorithms commonly used telecom linecards. in IPsec, SSL, 3GPP and other networking • Three 10/100/1000 Mb/s enhanced threespeed Ethernet controllers (eTSECs) TCP/IP acceleration and classification capabilities IEEE 1588 support Lossless flow control RGMII, SGMII A multiservice router or business gateway and wireless security protocols. The memory • High-speed interfaces (not all requires a combination of high performance controller offers future-proofing against memory available simultaneously) and a rich set of peripherals to support the technology migration with support for both DDR2 Four SerDes to 3.125 GHz multiplexed datapath throughputs and required system and DDR3. It also supports error correction across controllers functionality. The P1011 and P1020 devices codes, a baseline requirement for any high- Two PCI Express controllers offer a scalable platform to develop a range of reliability system. products that can support the same feature set. Two SGMII interfaces • Two High-Speed USB controllers (USB 2.0) The P1011 and P1020 processors integrate Integrated 10/100/1000 Ethernet controllers a rich set of interfaces, including a 4-lane with classification and QoS capabilities are ideal Host and device support multiprotocol SerDes, Gigabit Ethernet, PCI for managing the datapath traffic between the Express® and USB. The three 10/100/1000 LAN and WAN interface. PCI Express ports Enhanced host controller interface (EHCI) Ethernet ports support advanced packet parsing, can provide connectivity to IEEE 802.11n radio flow control and quality of service features, as cards for wireless support, TDM for legacy well as IEEE® 1588 time-stamping—all ideal for phone interfaces to support voice and the USB managing the datapath traffic between the LAN or SD/MMC interfaces can be used to support • Serial peripheral interface and WAN interface. A TDM interface can support local storage. The second USB interface is • Integrated security engine (SEC 3.3) voice for legacy phone applications. Four SerDes also available to support USB-attached printers lanes can be portioned across two PCI Express or as a console port. And the integrated AES, RSA/ECC, MD5/SHA, ARC4, Snow ports and two SGMII ports. The PCI Express security engine can provide encrypted secure 3G and FIPS deterministic RNG ports can provide connectivity to IEEE 802.11n communications for remote users with radio cards for wireless support. USB or SD/ VPN support. MMC interfaces can be used to support local ULPI interface to PHY • Enhanced secure digital host controller (eSDHC) Crypto algorithm support includes 3DES, Single pass encryption/message authentication for common security protocols (e.g., IPsec, SSL, SRTP, WiMAX) Technical Specifications storage. A second USB interface is also available to support USB attached printers or as a console XOR acceleration • Dual (P1020) or single (P1011) high- port. Multiple memory connection ports are performance Power Architecture e500 cores available, including the 16-bit local bus, two USB 36-bit physical addressing 2.0 controllers, eSDHC and SPI. compliant with OpenPIC standard 32 KB L1 instruction cache and 32 KB L1 data cache for each core The P1011 and P1020 processors serve in • Enhanced local bus controller (eLBC) clock frequency are well suited for various combinations of • 16 general-purpose I/O signals • 256 KB L2 cache with ECC, also data plane and control plane workloads in configurable as SRAM and stashing memory networking and telecom applications. With an • Four-channel DMA controller • Two I2C controllers, DUART, timers 533–800 MHz core a wide variety of applications. The devices controller with ECC support • Programmable interrupt controller (PIC) Double-precision floating-point support Target Applications • 32-bit DDR2/DDR3 SDRAM memory • Package: 689-pin wirebond power-BGA (TEPBGA2) QorIQ P1020 and P1011 Features QorIQ Platform P1 P1 P2 P2 Device Cores P1011 P1020 P2010 P2020 1 2 1 2 Top Core Frequency 800 MHz 800 MHz 1200 MHz 1200 MHz L2 Size 256 256 512 512 KB KB KB KB DDR 2/3 Support GE Ports 32-bit 32-bit 64-bit 64-bit with with with with ECC ECC ECC ECC 3 3 3 3 QUICC Engine 4 4 4 4 SerDes PCI Express Serial RapidIO TDM 2 2 3 3 N/A N/A 2 2 Yes Yes N/A N/A Yes Yes In QUICC Engine In QUICC Engine For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine and CoreNet are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2009, 2011, 2013 Freescale Semiconductor, Inc. Document Number: QP10XXFS REV 6