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QorIQ P Series Processors QorIQ P1012 and P1021 Communications Processors The QorIQ P1 family, which includes the P1012 and P1021 communications processors, offers the value of smart integration and efficient power intelligence for a wide variety of applications in the networking, telecom, defense and industrial markets. Based on 45 nm technology for low power, the P1012 and P1021 processors provide single- and dual-core options, from 533 MHz– 800 MHz, along with advanced security and a rich set of interfaces. The P1012 and P1021 processors are ideally suited for multiservice gateways, Ethernet switch controllers, wireless LAN access points and highperformance general-purpose control processor applications with tight thermal constraints. The P1012 and P1021 processors are pincompatible with the QorIQ P1011, P1020 and P2 platform products, offering a six-chip range of cost-effective solutions. Scaling from a single core at 533 MHz (P1012) to a dual core at 1.2 GHz per core (P2020), the combined QorIQ platforms deliver an impressive 4.5x aggregate frequency range. The P1012 and P1021 platforms are fully software compatible, both featuring the e500 Power Architecture core and peripherals, as well as being fully software compatible with the earlier PowerQUICC processors. This enables customers to create a product with multiple performance points from a single board design. The QorIQ P1021 dual-core processor supports both symmetric and asymmetric processing, enabling customers to further optimize their design with the same applications running on each core or serialize your application using the cores for different processing tasks. QorIQ P1012 P1021 Block Diagram QorIQ P1012 andand P1021 Block Diagram QorIQ P1012 and P1021 Block Diagram Not on P1012 Security Acceleration Security Acceleration XOR XOR Power Architecture e500 Core ® Power Architecture Not on P1012 Power Architecture e500Architecture Core Power ® 256 KB L2256 Cache KB e500 Core 32 KB 32 KB L1 I 32 Cache Cache KB L1 D32 KB e500 Core 32 KB 32 KB L1 I 32 Cache Cache KB L1 D32 KB L2 Cache L1 I Cache L1 D Cache L1 I Cache L1 D Cache Coherency Module System Bus Enhanced Local Bus Controller Local (eLBC)Bus Enhanced System Bus 3x Gigabit 3x Ethernet Gigabit Ethernet QUICC Engine On-Chip Network Express® Controller 4-lane SerDes UTOPIA-L2 TDM Ethernet UTOPIA-L2 TDM Ethernet 4-lane SerDes Core Complex L2 and Frontside CoreNet Platform Cache) Accelerators and(CPU, Memory Control Networking Elements Accelerators and Memory Control Controller (eLBC) On-Chip Network 2x PCI 4-ch. DMA ® Express Controller 2x PCI 4-ch. DMA Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Networking Elements DUART, 2x I2C, Timers, Interrupt DUART, 2xControl, I2C, Timers, SD/MMC,Control, SPI, Interrupt USB 2.0/ULPI SD/MMC, SPI, USB 2.0/ULPI Coherency Module QUICC Engine DDR2/DDR3 SDRAM Controller DDR2/DDR3 SDRAM Controller Basic Peripherals and Interconnect Basic Peripherals and Interconnect The P1012 and P1021 processors have an advanced set of features for ease of use. The 256 KB L2 cache offers incremental configuration to partition the cache between the two cores or to configure it as SRAM or stashing memory. Target Applications The P1012 and P1021 processors serve a wide variety of applications and are well suited for various combinations of data plane and control plane workloads in networking and telecom applications. With an available junction temperature range of –40 ºC to +125 ºC, the devices can be used in powersensitive defense and industrial applications, and outdoor environments less protected from the environment. The devices primarily target applications such as networking and telecom linecards. A multiservice router or business gateway requires a combination of high performance and a rich set of peripherals to support the datapath throughputs and required system functionality. The P1012 and P1021 devices offer a scalable platform to develop a range of products that can support the same feature set. The QUICC Engine module, as well as integrated 10/100/1000 Ethernet controllers with classification and QoS capabilities, are ideal for managing the datapath traffic between the LAN and WAN interface. PCI Express ports can provide connectivity to IEEE 802.11n radio cards for wireless support, TDM for legacy phone interfaces to support voice and the USB or SD/MMC interfaces can be used to support local storage. The integrated security engine can provide encrypted secure communications for remote users with VPN support. Technical Specifications • Single (P1012) and dual (P1021) highperformance Power Architecture e500 cores 36-bit physical addressing Double-precision floating-point support 32 KB L1 instruction cache and 32 KB L1 data cache for each core 533 MHz–800 MHz core clock frequency • 256 KB L2 cache with ECC, also configurable as SRAM and stashing memory • Three 10/100/1000 Mb/s enhanced threespeed Ethernet controllers (eTSECs) TCP/IP acceleration and classification capabilities IEEE 1588 support Lossless flow control RGMII, SGMII • High-speed interfaces (not all available simultaneously) Four SerDes to 3.125 GHz multiplexed across controllers Two PCI Express controllers Two SGMII interfaces • QUICC Engine module UTOPIA-L2 Up to two 10/100 Ethernet interfaces Up to four T1/E1/J1/E3 or DS-3 serial interfaces Up to four HDLC interfaces with 128 channels of HDLC Up to four BISYNC interfaces Up to four UART interfaces SPI interfaces GPIO • High-speed USB controller (USB 2.0) Host and device support Enhanced host controller interface (EHCI) ULPI interface to PHY • Enhanced secure digital host controller • Serial peripheral interface • Integrated security engine (SEC 3.3) Crypto algorithm support includes 3DES, AES, RSA/ECC, MD5/ SHA, ARC4, Snow 3G and FIPS deterministic RNG Single pass encryption/message authentication for common security protocols (e.g., IPsec, SSL, SRTP, WiMAX) XOR acceleration • 32-bit DDR2/DDR3 SDRAM memory controller with ECC support • Programmable interrupt controller (PIC) compliant with OpenPIC standard • Four-channel DMA controller • Two I2C controllers, DUART, timers • Enhanced local bus controller (eLBC) • 16 general-purpose I/O signals • Package: 689-pin wirebond power-BGA (TEPBGA2) QorIQ P1021 Features QorIQ Platform Device Cores Top Core Frequency L2 Size DDR 2/3 Support GE Ports QUICC Engine SerDes PCI Express Serial RapidIO TDM P1 P1011 1 800 MHz 256 KB 32-bit with ECC 3 N/A 4 2 N/A Yes P1 P1020 2 800 MHz 256 KB 32-bit with ECC 3 N/A 4 2 N/A Yes P1 P1012 1 800 MHz 256 KB 32-bit with ECC 3 Yes 4 2 N/A In QUICC Engine P1 P1021 2 800 MHz 256 KB 32-bit with ECC 3 Yes 4 2 N/A In QUICC Engine P2 P2010 1 1200 MHz 512 KB 64-bit with ECC 3 N/A 4 3 2 N/A P2 P2020 2 1200 MHz 512 KB 64-bit with ECC 3 N/A 4 3 2 N/A For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo, PowerQUICC and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. QUICC Engine and CoreNet are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2010, 2013, 2015 Freescale Semiconductor, Inc. Document Number: QORIQP1021FS REV 3