P2020NSN2MHC

QorIQ Communications Platforms QorIQ P2010 and P2020 Processors Overview The QorIQ mid-performance tier, which The P2020 and P2010 processors have an Target Applications includes the P2020 (dual-core processor) and advanced set of features for ease of use. The P2010 (single-core processor) communications optional integrated security engine supports The P2010 and P2020 processors serve in a processors, delivers high single-threaded the cryptographic algorithms commonly used performance per watt for a wide variety of in IPsec, SSL, 3GPP and other networking applications in the networking, telecom, and wireless security protocols. The 64-bit military and industrial markets. These memory controller offers future proofing against P2 devices deliver dual- and single-core memory technology migration with support for frequencies up to 1.2 GHz on a 45 nm both DDR2 and DDR3. It also supports error technology low-power platform. correction codes, a baseline requirement for The QorIQ P2020 and P2010 dual- and single-core products are pin compatible with the QorIQ P1 family devices in the value- any high-reliability system. Other memory types such as flash are supported through the 16-bit local bus, USB, SD/MMC and SPI. wide range of applications, notably those with tight thermal constraints. With an available junction temperature range of –40 °C to +125 °C, the devices can be used in power-sensitive defense, aerospace and industrial applications, and less protected outdoor environments. They enable various combinations of data plane and control plane workloads in networking and telecom applications that require higher performance but want to avoid the complexity of partitioning performance tier, offering four interchangeable The P2010 and P2020 processors integrate a the application across many cores. The cost-effective solutions. Scaling from a single- rich set of interfaces, including SerDes, Gigabit devices’ primary target applications are core processor at 533 MHz (P1011) to a dual- Ethernet, PCI Express , RapidIO technology networking and telecom linecards. The P2 core processor at 1.2 GHz (P2020), the two and USB. The three 10/100/1000 Ethernet devices, with their low power budget and high tiers of devices together deliver an impressive ports support advanced packet parsing, flow single-threaded performance, are uniquely well- 4.5x aggregate frequency range within the control and quality of service features, as well suited for control plane applications. same pinout. as IEEE 1588 time stamping. ® ® ® The P2010 and P2020 devices are software compatible, sharing the e500 Power Architecture® core and peripherals, as well QorIQ P1 and P2 Family Comparison Chart as being fully software compatible with the Device Cores Top Core L2 Frequency Size DDR 2/3 Support GE SerDes PCI Serial TDM Ports Express® RapidIO® existing PowerQUICC processors. This enables P1011 1 800 MHz 256 KB 32-bit with ECC 3 4 2 N/A Yes customers to create a product with multiple P1020 2 800 MHz 256 KB 32-bit with ECC 3 4 2 N/A Yes performance points from a single board P2010 1 1200 MHz 512 KB 64-bit with ECC 3 4 3 2 N/A design. The P2020 and P1020 dual-core P2020 2 1200 MHz 512 KB 64-bit with ECC 3 4 3 2 N/A processors support symmetric and asymmetric multiprocessing, enabling customers to scale performance through either thread-level or QorIQ P2020/P2010 Communication Processors QorIQ P2020/P2010 Communication Processors application-level parallelism. Power Architecture® e500-v2 Core 32 KB D Cache 2x USB 2.0 512 KB Frontside Cache 32 KB I Cache 64/32-bit DDR2/3 Memory Controller P2010–Single Core Only eLBC Coherent System Bus TDM SD/MMC DUART Security 3.3 2x I2C SRIO 1 GE SPI, GPIO 1 GE SRIO PCIe PCle 4-Lane 2.5/3 GHz SerDes Core Complex (CPU and L2 Cache) Basic Peripherals and Interconnect Accelerators and Memory Control Networking Elements DMA 1 GE PCIe Control plane applications tend to be more Technical Specifications • Serial peripheral interface sequential in nature and thus lose scaling • Dual (P2020) or single (P2010) high- • Integrated security engine (SEC 3.1) efficiency with increasing number of threads or performance Power Architecture cores. Both P2 devices, with their low power, e500 cores efficient dual-issue out-of-order e500 core, Power Architecture technology and high 1.2 GHz frequency, offer a level of single-threaded performance that is suitable for control plane applications. The networking linecard requires an optimal combination of good performance to manage a large amount of control plane traffic balanced 3DES, AES, RSA/ECC, MD5/SHA, Double-precision floating-point support ARC4, Kasumi, Snow 3G and FIPS 32 KB L1 instruction cache and 32 KB L1 data cache for each core 800 MHz to 1.2 GHz clock frequency • 512 KB L2 cache with ECC. Also configurable as SRAM and stashing I/O, flexible core configurations and an memory. processors are well-suited for this application, which involves controlling ASICs, managing exceptions and routing table maintenance. Crypto algorithm support includes 36-bit physical addressing against low power and cost. With convenient onboard security block, the P2010 and P2020 (optional) • Three 10/100/1000 Mb/s enhanced threespeed Ethernet controllers TCP/IP acceleration and deterministic RNG Single pass encryption/message authentication for common security protocols (IPsec, SSL, SRTP, WiMAX) XOR acceleration • 64-bit DDR2/DDR3 SDRAM memory controller with ECC support • Programmable interrupt controller compliant with OpenPIC standard classification capabilities • Two four-channel DMA controllers well-suited for LTE and WiMAX channel card IEEE 1588 support • Two I2C controllers, DUART, timers applications. With dual-core performance in Lossless flow control • Enhanced local bus controller R/G/MII, R/TBI, SGMII • 16 general-purpose I/O signals FIFO interfaces • Package: 689-pin wirebond power-BGA The P2010 and P2020 processors are also single-core power budgets, the P2 devices facilitate the “flattening” of the wireless network hierarchy. The dual Serial RapidIO interfaces allow direct connection to the DSPs (such as the MSC8156 DSP) that implement layer 1 processing as well as redundant backplane connections. • High-speed interfaces supporting various multiplexing options Four SerDes to 3.125 GHz multiplexed across controllers Three PCI Express interfaces Two Serial RapidIO interfaces Two SGMII interfaces • High-Speed USB controller (USB 2.0) (TEPBGA2) Software and Tools Support • Enea®: Real-time operating system support • Green Hills®: Complete portfolio of software and hardware development tools, trace tools and real-time operating systems • Mentor Graphics®: Commercial-grade Linux® solution • P2020 development system, P2020 Host and device support reference design board and P2020 COM Enhanced host controller interface Express development board ULPI interface to PHY • Enhanced secure digital host controller (SD/MMC) For more information, visit freescale.com/QorIQ Freescale, the Freescale logo, CoreNet, PowerQUICC and QorIQ and the Freescale logo are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2009, 2013 Freescale Semiconductor, Inc. Document Number: QP20XXFS REV 5 cc