P5020NSN7VNB

QorIQ Communications Platforms P Series QorIQ P5020 and P5010 communications processors Overview e5500 Core The QorIQ P5 family delivers scalable 64-bit The P5020 is based on the 64-bit e5500 processing with single-, dual- and quad-core Power Architecture® core. The e5500 devices. With frequencies scaling up to 2.0 GHz, a tightly coupled cache hierarchy for low latency and integrated hardware acceleration, the P5020 (dual-core) and P5010 (single-core) devices are ideally suited for compute intensive, power-conscious control plane applications. DPAA Hardware Accelerators Frame manager (FMAN) 12 Gb/s classify, parse and distribute core uses a seven-stage pipeline for low Buffer manager (BMAN) 64 buffer pools latency response to unpredictable code Queue manager (QMAN) Up to 224 queues execution paths, boosting its single-threaded Security (SEC) 17 Gb/s: 3 DES, AES performance. Key features: Pattern matching engine (PME) 10 Gb/s aggregate • Supports up to 2 GHz core frequencies RapidIO® manager • Tightly coupled low latency cache Supports Type 9 and Type 11 messaging RAID5/6 engine Calculates parity for network attached storage and direct attached storage applications hierarchy: 32 KB I/D (L1), 512 KB L2 Target Markets and Applications The P5020 is designed for high-performance, power-constrained control plane applications and provides an ideal combination of core performance, integrated accelerators and advanced I/O required for the following compute-intensive applications: • Enterprise equipment: Router, switch, services • Data center: Server appliance, SAN storage controller, iSCSI controller, FCoE bridging per core • Up to 2 MB of shared platform cache (L3) • Up to 64 GB of addressable memory space The P5020 integrates QorIQ DPAA, an • Hybrid 32-bit mode to support legacy innovative multicore infrastructure for software and seamless transition to 64-bit scheduling work to cores (physical and virtual), architecture hardware accelerators and network interfaces. The FMAN, a primary element of the DPAA, Virtualization parses headers from incoming packets and The P5020 includes support for hardware- classifies and selects data buffers with optional assisted virtualization. The e5500 core offers policing and congestion management. The an extra core privilege level (hypervisor). FMAN passes its work to the QMAN, which Virtualization software for the P5 family • Aerospace and defense includes kernel-based virtual machine (KVM), • Industrial computing: Single-board Linux® containers, Freescale hypervisor and computers, test/measurement, robotics Data Path Acceleration Architecture (DPAA) • 3 DMIPS/MHz per core assigns it to cores or accelerators with a multilevel scheduling hierarchy. The P5020 also offers accelerators for cryptography, enhanced commercial virtualization software from Green regular expression pattern matching and Hills® Software and Enea®. RAID5/6 offload. QorIQ P5020/P5010 QorIQ P5020/P5010 Processors Processors Block Diagram *Only Available on P5020 *Only Available on P5020 Power Architecture® e5500 Core 512 KB Backside L2 Cache 32 KB D Cache 32 KB I Cache Security Fuse Processor PAMU eSDHC PAMU eLBC SD/MMC 1024 KB Frontside CoreNet Platform Cache 64-bit DDR2/3 Memory Controller Queue Mgr. Pattern Match Engine 2.0 Buffer Mgr. 2x I C RAID 5/6 Engine Parse, Classify, Distribute 10 GE Peripheral Access PAMU Management Unit PAMU Frame Manager Serial Security RapidIO® 4.0 Mgr. 2 SPI, GPIO 64-bit DDR2/3 Memory Controller CoreNet Coherency Fabric 2x Full Speed USB w/PHY 2x DUART 1024 KB Frontside CoreNet Platform Cache 1GE 1GE 1GE 1GE 1GE SATA SATA 2.0 2.0 Real-Time Debug RapidIO Message Unit PCIe PCIe 2x DMA PCIe 18-Lane 5 GHz SerDes Core Complex (CPU, L2 and Frontside CoreNet Platform Cache) Accelerators and Memory Control Networking Elements Basic Peripherals and Interconnect SRIO PCIe/ SRIO Watchpoint Cross Trigger Perf. Monitor Trace Aurora  P5 Family Comparison Chart CPU cores Threads Max core frequency L2 L3/Platform DDR I/F PCI Express® GbE, 10 GbE SRIO SerDes lanes Package P5020/P5010 P5040/P5021 2x 64-bit e5500, 1x (P5010) 2/1 (single thread per core) 1.6 to 2 GHz 512 KB per core 2 MB (P5020)/1 MB (P5010) 2x 64-bit DDR3 (up to 1333 MT/s) 1x 64-bit DDR3 (P5010) 4x PCIe v2.0 5x 1 GbE, 1x 10 GbE 2x SRIO v2.1 (supports Type 9 and 11 messaging) 18 lanes 1295-pin 37.5 x 37.5 mm FC-PBGA 4x 64-bit e5500, 2x (P5021) 4/2 (single thread per core) 1.8 to 2.2 GHz 512 KB per core 2 MB (both P5040 and P5021) 2x 64-bit DDR3 (up to 1600 MT/s) System Peripherals and Networking For networking, the FMAN supports one 10 Gb/s and 5x 1 Gb/s MAC controllers that connect to PHYs, switches and backplanes over RGMII, SGMII and XAUI. High-speed system expansion is supported through four P5020/P5010 Features List Two (P5020) or one (P5010) single threaded e5500 cores built on Power Architecture® technology • Up to 2 GHz with 64-bit ISA support (Power Architecture V2.06 compliant) • Three levels of instruction: User, supervisor, hypervisor • Hybrid 32-bit mode to support legacy software and transition to 64-bit architecture CoreNet platform cache (CPC) • 2 MB configured as dual 1 MB blocks (1 MB only for P5010) Hierarchical interconnect fabric • CoreNet fabric supporting coherent and non-coherent transactions with prioritization and bandwidth allocation amongst CoreNet endpoints • QMAN fabric supporting packet-level queue management and quality of service scheduling Two 64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving support • Up to 1333 MT/s • Memory pre-fetch engine DPAA incorporating acceleration for the following functions • • • • • SerDes • 18 lanes at up to 5 Gb/s • Supports SGMII, XAUI, PCIe rev1.1/2.0, SATA Ethernet interfaces • One 10 Gb/s Ethernet MACs • 5x 1 Gb/s Ethernet MACs High-speed peripheral interfaces • Four PCI Express 2.0 controllers • Two Serial RapidIO controllers/ports (sRIO port) V1.3-compliant with features of V2.1 • Two serial ATA (SATA 2.0) controllers Additional peripheral interfaces • • • • • • DMA • Dual four channel Support for hardware virtualization and partitioning enforcement • Extra privileged level for hypervisor support QorIQ trust architecture 1.1 • Secure boot, secure debug, tamper detection, volatile key storage PCI Express v2.0 controllers that support a variety of lane widths. Other peripherals include SATA, SD/MMC, I2C, UART, SPI, NOR/ NAND controller, GPIO and dual 1333 MT/s DDR3/3L controllers. Software and Tool Support • Enea: Real-time operating system support and virtualization software • Green Hills: Comprehensive portfolio of software and hardware development tools, trace tools, real-time operating systems and virtualization software • Mentor Graphics®: Commercial-grade Linux solution • QNX : Real-time OS and development tool ® support • QorIQ P5020 development system (P5020DS) 3x PCIe v2.0 (incl. 1 x 8) 10x 1 GbE, 2x 10 GbE N/A 20 lanes 1295-pin 37.5 x 37.5 mm FC-PBGA Packet parsing, classification and distribution (FMAN) QMAN for scheduling, packet sequencing and congestion management Hardware BMAN for buffer allocation and de-allocation Cryptography acceleration (SEC 4.2) at up to 40 Gb/s RegEx pattern matching acceleration (PME 2.1) at up to 10 Gb/s Two USB 2.0 Full-Speed controllers with integrated PHY Enhanced secure digital host controller (SD/MMC/eMMC) Enhanced serial peripheral interface Four I2C controllers Four UARTs Integrated flash controller supporting NAND and NOR flash For more information, please visit freescale.com/QorIQ Freescale, the Freescale logo and QorIQ are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm Off. CoreNet is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. © 2012, 2014 Freescale Semiconductor,Inc. Document Number: QP5020FS REV 6