NXP Semiconductors
Data sheet: Advance Information
Document Number: VR5100
Rev. 5.0, 12/2018
Multi-output DC/DC regulator for
low-power LS1 communication
processors
VR5100
The VR5100 is a high performance, highly integrated, multi-output, DC/DC
regulator solution, with integrated power MOSFETs, ideally suited for the LS1
family of communications processors. Integrating three buck converters, six
linear regulators, RTC supply and a coin-cell charger, the VR5100 can provide
power for a complete system, including communications processors, memory,
and system peripherals.
Features:
• Three adjustable high efficiency buck regulators: 3.8 A, 1.25 A, 1.5 A
• Selectable modes: PWM, PFM, APS
• 5.0 V, 600 mA boost regulator with PFM or Auto mode
• Six adjustable general purpose linear regulators
• Input voltage range: 2.8 V to 4.5 V
• OTP (One Time Programmable) memory for device configuration
• Programmable start-up sequence and timing
• Selectable output voltage, frequency, soft start
• I2C control
POWER MANAGEMENT
EP SUFFIX
98ASA00719D
48 QFN 7.0 X 7.0
Applications:
• Network attached storage (NAS)
• Value IOT gateway
• Mobile NAS
• Industrial control
• Home/Factory automation
• Always ON RTC supply and Coin cell charger
• DDR reference voltage
• -40 °C to +125 °C operating junction temperature
Figure 1. VR5100 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP Semiconductors N.V. 2018
Table of Contents
1
5
6
6
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6 Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6 Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.6 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
7.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
8 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
9 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
9.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
10 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
10.1Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
VR5100
2
NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
The VR5100 is available with pre-programmed OTP memory configurations. The devices are identified using the program codes from
Table 1. Details of the OTP programming for each device can be found in Table 37.
Table 1. Orderable part variations
Part Number
MC34VR5100A0EP
MC34VR5100A1EP
MC34VR5100A2EP
Temperature (TA)
-40 °C to 105 °C
(For use in Industrial
applications)
Package
Programming Options
Notes
0 - Not programmed
48 QFN 7.0 mm x 7.0 mm
1 (LS1012 with DDR3L)
(1)
2 (LX2160 with DDR4)
Notes
1.
For tape and reel, add an R2 suffix to the part number.
VR5100
NXP Semiconductors
3
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
Figure 2. VR5100 simplified internal block diagram
VR5100
4
NXP Semiconductors
37 FBBST
38 PVIN2
39 VDDOTP
40 SGND
41 VCC
42 VIN
48 EN
Transparent top view
43 VDIG
Pinout diagram
44 VBG
3.1
45 SDA
Pin connections
47 VCCI2C
3
46 SCL
PIN CONNECTIONS
PINOUT DIAGRAM
1
36
LICELL
2
35
LXBST
3
34
VSNVS
STBY 4
33
VSD
5
32
V33
31
SGND3
30
NC
INTB
SD_VSEL
PORB
ICTEST
FB1
6
EP
23
24
REFIN
REFOUT
VHALF
25
22
12
LDO4
SGND1
21
SGND2
VLDOIN34
26
20
11
LDO3
NC
19
FB3
FB2
27
18
10
PVIN2
PVIN1
17
PVIN3
LX2
28
16
9
VLDOIN2
LX1
15
LX3
LDO2
29
14
8
LDO1
LX1
13
7
VLDOIN1
PVIN1
Figure 3. Pinout diagram
VR5100
NXP Semiconductors
5
PIN CONNECTIONS
PIN DEFINITIONS
3.2
Pin definitions
Table 2. Pin definitions
Pin number
Pin name
Pin
function
Type
Definition
-
EP
GND
GND
Expose pad. Functions as ground return for buck and boost regulators. Tie this pad to the
inner and external ground planes through vias to allow effective thermal dissipation
1
INTB
O
Digital
Open drain interrupt signal to processor
2
SD_VSEL
I/O
Digital
Input from LS1 processor to select SD regulator voltage • SD_VSEL=0, SD = 3.3 V •
SD_VSEL= 1, VSD = 1.8 V
3
PORB
O
Digital
Open drain reset output to processor
4
STBY
I
Digital
Standby input signal from processor
5
ICTEST
I
Digital and
Analog
6
FB1
I
Analog
SW1 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitance or near the load, if possible for best regulation
7
PVIN1
I
Analog
Input to SW1 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
8, 9
LX1
O
Analog
Switcher 1 switch node connection. Connect to SW1 inductor
10
PVIN1
I
Analog
Input to SW1 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
11, 30
NC
—
—
12
SGND1
GND
GND
13
VLDOIN1
I
Analog
LDO1 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the pin as
possible
14
LDO1
O
Analog
LDO1 regulator output. Bypass with a 2.2 μF ceramic output capacitor
15
LDO2
O
Analog
LDO2 regulator output. Bypass with a 4.7 μF ceramic output capacitor
16
VLDOIN2
I
Analog
LDO2 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the pin as
possible
17
LX2 (2)
O
Analog
Switcher 2 switch node connection.Connect to SW2 inductor
18
PVIN2 (2)
I
Analog
Input to SW2 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
19
FB2 (2)
I
Analog
SW2 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
20
LDO3
O
Analog
LDO3 regulator output. Bypass with a 2.2 μF ceramic output capacitor
21
VLDOIN34
I
Analog
LDO3 and LDO4 input supply. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible
22
LDO4
O
Analog
LDO4 regulator output. Bypass with a 2.2 μF ceramic output capacitor
23
VHALF
I
Analog
Half supply reference for REFOUT. Bypass with 0.1 μF to ground.
24
REFIN
I
Analog
REFOUT regulator input. Connect a 0.1 μF capacitor between REFIN and VHALF pin.
Ensure there is at least 1.0 μF net capacitance from REFIN to ground
25
REFOUT
O
Analog
REFOUT regulator output. Bypass with 1.0 μF to ground
26
SGND2
GND
GND
Reference ground for SW2 and SW3 regulators. Connect to GND. Keep away from high
current ground return paths
27
FB3 (2)
I
Analog
SW3 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
28
PVIN3 (2)
I
Analog
Input to SW3 regulator. Bypass with at least a 4.7 μF ceramic capacitor and a 0.1 μF
decoupling capacitor as close to the pin as possible
29
LX3 (2)
O
Analog
Switcher 3 switch node connection. Connect the SW3 inductor
Reserved pin. Connect to GND in application
Leave this pin floating
Ground reference for SW1. Connect to GND. Keep away from high current ground return
paths
VR5100
6
NXP Semiconductors
PIN CONNECTIONS
PIN DEFINITIONS
Table 2. Pin definitions (continued)
31
SGND3
GND
GND
Connect to GND.
32
V33
O
Analog
V33 regulator output. Bypass with a 4.7 μF ceramic output capacitor
33
VSD
O
Analog
Output of VSD regulator. Bypass with a 2.2 μF ceramic output capacitor.
34
VSNVS
O
Analog
VSNVS regulator/switch output. Bypass with 0.47 μF capacitor to ground.
35
LXBST (2)
I/O
Analog
SWBST switch node connection. Connect to SWBST inductor and anode of Schottky
diode
36
LICELL
I/O
Analog
Coin cell supply input/output. Bypass with 0.1 μF capacitor. Connect to optional coin cell
37
FBBST (2)
I
Analog
SWBST output voltage feedback pin. Route this trace separately from the high current
path and terminate at the output capacitor
38
PVIN2
I
Analog
Input to SD, V33 regulators and SWBST control circuitry. Connect to VIN rail and bypass
with 10 μF capacitor
39
VDDOTP
I
Digital &
Analog
40
SGND
GND
GND
41
VCC
O
Analog
Internal analog core supply. Bypass with 1 μF capacitor to ground
42
VIN
I
Analog
Main IC supply. Bypass with 1.0 μF capacitor to ground. Connect to system input supply.
43
VDIG
O
Analog
Internal digital core supply. Bypass with 1.0 μF capacitor to ground
44
VBG
O
Analog
Main band gap reference. Bypass with 220 nF capacitor to ground
45
SDA
I/O
Digital
I2C data line (open drain). Pull up to VCCI2C with a 4.7 kΩ resistor
46
SCL
I
Digital
I2C clock. Pull up to VCCI2C with a 4.7 kΩ resistor
47
VCCI2C
I
Analog
Supply for I2C bus. Bypass with 0.1 μF ceramic capacitor. Connect to 1.7 to 3.6 V supply.
Ensure VCCI2C is always lesser than or equal to VIN
48
EN
I
Digital
Power ON/OFF input from processor
Supply to program OTP fuses. Connect VDDOTP to GND during normal application
Ground reference for IC core circuitry. Connect to ground. Keep away from high current
ground return paths
Notes
2.
Unused switching regulators should be connected as follows: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be
connected to VIN with a 0.1 F bypass capacitor.
VR5100
NXP Semiconductors
7
GENERAL PRODUCT CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
4
General product characteristics
4.1
Absolute maximum ratings
Table 3. Absolute maximum voltage ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol
Description
Value
Unit
–
-0.3 to 7.5
V
VIN, PVIN2,
VLDOIN1, PVIN1,
–
PVIN2, PVIN3,
LX1, LX2, LX3
-0.3 to 4.8
V
OTP programming input supply voltage
-0.3 to 10.0
V
Boost switcher feedback
-0.3 to 5.5
V
-0.3 to 3.6
V
Notes
Electrical ratings
ICTEST, LXBST
VDDOTP
FBBST
INTB, SD_VSEL,
PORB, STBY, FB1,
FB2, FB3, LDO1,
VLDOIN2,
VLDOIN34, LDO3,
LDO4, VHALF, –
REFIN, REFOUT,
V33, VSD, VSNVS,
LICELL, VCC,
SDA, SCL,
VCCI2C, EN
LDO2
LDO2 linear regulator output
-0.3 to 2.5
V
VDIG
Digital core supply voltage output
-0.3 to 1.65
V
VBG
Bandgap reference voltage output
-0.3 to 1.5
V
VESD
ESD ratings
• Human body model
• Charge device model
2000
500
V
(3)
(4)
Notes
3.
10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.
4.
ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge device model
(CDM), Robotic (CZAP = 4.0 pF).
VR5100
8
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
THERMAL CHARACTERISTICS
4.2
Thermal characteristics
Table 4. Thermal ratings
Symbol
Description (Rating)
Min.
Max.
Unit
Notes
Thermal ratings
TA
Ambient operating temperature range
• Industrial version
-40
105
C
TJ
Operating junction temperature range
-40
125
C
Storage temperature range
-65
150
C
–
(7)
C
(6) (7)
TST
TPPRT
Peak package reflow temperature
(5)
QFN48 thermal resistance and package dissipation ratings
RJA
Junction to ambient, natural convection
• Four layer board (2s2p)
• Eight layer board (2s6p)
–
–
24
15
°C/W
(8) (9) (10)
RJB
Junction to board
–
11
°C/W
(11)
RJCBOTTOM
Junction to case bottom
–
1.4
°C/W
(12)
JT
Junction to package top
• Natural convection
–
1.3
°C/W
(13)
Notes
5.
Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Thermal
Protection Thresholds for thermal protection features.
6.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
7.
NXP's package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and
moisture sensitivity levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
8.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
9.
The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
10.
Per JEDEC JESD51-6 with the board horizontal.
11.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
12.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
13.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC
JESD51-2. When Greek letters (JT) are not available, the thermal characterization parameter is written as Psi-JT.
VR5100
NXP Semiconductors
9
GENERAL PRODUCT CHARACTERISTICS
CURRENT CONSUMPTION
4.3
Current consumption
The current consumption of the individual blocks is described in detail in the following table.
Table 5. Current consumption summary
TA= -40 °C to 105 °C, VIN = 3.6 V, VCCI2C = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V, VSNVS = 3.0 V, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VCCI2C = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless
otherwise noted.
Mode
Coin Cell
Off
Sleep LPSR
Standby
ON
VR5100 Conditions
Typ.
Max.
Unit
Notes
No load on VSNVS
4.0
7.0
A
(14) (15)
VSNVS from VIN or LICELL
Wake-up from EN active
32 kHz RC on
All other blocks off
VIN UVDET
No load on VSNVS, PMIC able to wakeup
16
25
A
(14) (15)
VSNVS from VIN
Wake-up from EN active
Trimmed reference active
SW3 PFM. All other regulators off.
Trimmed 16 MHz RC off
32 kHz RC on
REFOUT disabled
No load on any of the regulators
130 (14)
200 (17)
220 (14)
A
(16)
LDO1 & LDO3 activated in addition to
SW3
No load on any of the regulators
170 (14)
260 (17)
248 (14)
A
(16)
VSNVS from either VIN or LICELL
SW1 in PFM
SW2 in PFM
SW3 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
LDO1-4 enabled
V33 enabled
VSD enabled
REFOUT enabled
No load on any of the regulators
297
450
A
(16)
VSNVS from VIN
SW1 in APS
SW2 in APS
SW3 in APS
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
LDO1-4 enabled
V33 enabled
VSD enabled
REFOUT enabled
No load on any of the regulators
1.2
VSNVS from LICELL, All other blocks
off, VIN = 0.0 V
System Conditions
mA
Notes
14.
At 25 °C only
15.
When VIN is below the UVDET threshold, in the range of 1.8 V VIN < 2.65 V, the quiescent current increases by 50 A, typically.
16.
17.
For PFM operation, headroom should be 300 mV or greater.
At 105 °C only
VR5100
10
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
4.4
Electrical characteristics
Table 6. Static electrical characteristics – SW1
All parameters are specified at TA = -40 °C to 105 °C, VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, typical external component
values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN1 = 3.6 V, VSW1 = 1.2 V,
ISW1 = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(18)
Switch mode supply SW1
VPVIN1
Operating input voltage
2.8
–
4.5
V
VSW1
Nominal output voltage
–
Table 46
–
V
-25
25
mV
-25
35
mV
45
mV
-6.0
6.0
%
-6.0
6.0
%
VSW1ACC
ISW1
ISW1Q
Output voltage accuracy
• PWM, APS, 2.8 V < VPVIN1 < 4.5 V, 0 < ISW1 < 3.8 A
0.7 V VSW1 1.2 V
• PFM, APS, 2.8 V < VPVIN1 < 4.5 V, 0 < ISW1 < 3.8 A
1.225 V < VSW1 < 1.425 V
• PFM, steady state, 2.8 V < VPVIN1 < 4.5 V, 0 < ISW1 < 150 mA
1.8 V VSW1 1.425 V
• PWM, APS, 2.8 V < VPVIN1 < 4.5 V, 0 < ISW1 < 2.75A
1.8 V < VSW1 < 3.3 V
• PFM, steady state, 2.8 V < VPVIN1 < 4.5 V, 0 < ISW1 < 150 mA
1.8 V VSW1 3.3 V
Rated output load current,
• 2.8 V VPVIN1 4.5 V, 0.7 V < VSW1 < 1.425 V, 1.8V, 3.3V
Quiescent current
• PFM Mode
• APS Mode
-45
–
3800
–
–
mA
–
–
22
300
–
–
μA
4
2.6
5.5
4.0
8.0
5.4
A
ISW1LIM
Current limiter peak current detection , current through inductor
• SW1ILIM = 0
• SW1ILIM = 1
VSW1
Output ripple
–
5.0
–
mV
Discharge resistance
–
600
–
Start-up overshoot, ISW1 = 0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN1
= 4.5 V, VSW1 = 1.425 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW1 = 0 mA, DVS clk =
25 mV/4 s, VIN = VPVIN1 = 4.5 V, VSW1 = 1.425 V
–
–
500
μs
RSW1DIS
Switch mode supply SW1
VSW1OSH
tONSW1
Notes
18.
Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any VR5100 regulator, or external system supply.
VR5100
NXP Semiconductors
11
GENERAL PRODUCT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 7. Static electrical characteristics – SW2
All parameters are specified at TA = -40 °C to 105 °C, VIN = VPVIN2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VPVIN2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(19)
Switch mode supply SW2
VPVIN2
Operating input voltage
2.8
–
4.5
V
VSW2
Nominal output voltage
–
Table 48
–
V
-3.0%
-6.0%
–
–
3.0%
6.0%
-6.0%
-6.0%
–
–
6.0%
6.0%
1250
–
–
–
–
–
23
145
305
–
–
–
1.625
1.235
2.5
1.9
3.375
2.565
A
VSW2ACC
ISW2
ISW2Q
Output voltage accuracy
• PWM, APS, 2.8 V VPVIN2 4.5 V, 0 ISW2 1.25 A
• 1.50 V VSW2 1.85 V
• 2.5 V VSW2 3.3 V
• PFM, 2.8 V VPVIN2 4.5 V, 0 ISW2 50 mA
• 1.50 V VSW2 1.85 V
• 2.5 V VSW2 3.3 V
Rated output load current,
2.8 V < VPVIN2 < 4.5 V, 1.50 V < VSW2 < 1.85 V, 2.5 V < VSW2 < 3.3 V
Quiescent current
• PFM mode
• APS mode (Low output voltage settings)
• APS mode (High output voltage settings, SW2_HI=1)
%
mA
(20)
μA
ISW2LIM
Current limiter peak current detection, current through inductor
• SW2ILIM = 0
• SW2ILIM = 1
VSW2
Output ripple
–
5.0
–
mV
RONSW2P
SW2 P-MOSFET RDS(on) at VIN = VPVIN2 = 3.3 V
–
215
245
m
RONSW2N
SW2 N-MOSFET RDS(on) at VIN = VPVIN2 = 3.3 V
–
258
326
m
ISW2PQ
SW2 P-MOSFET leakage current, VIN = VPVIN2 = 4.5 V
–
–
10.5
μA
ISW2NQ
SW2 N-MOSFET leakage current, VIN = VPVIN2 = 4.5 V
–
–
3.0
μA
RSW2DIS
Discharge resistance during OFF mode
–
600
–
VSW2OSH
Start-up overshoot, ISW2 = 0.0 mA, DVS clk = 25 mV/4 s,
VIN = VPVIN2 = 4.5 V
–
–
66
mV
tONSW2
Turn-on time, enable to 90% of end value, ISW2 = 0.0 mA,
DVS clk = 25 mV/4 s, VIN = VPVIN2 = 4.5 V
–
–
500
μs
Notes
19.
Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any VR5100 regulator, or external system supply.
20.
The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VPVIN2 - VSW2) = ISW2*
(DCR of Inductor + RONSW2P + PCB trace resistance).
VR5100
12
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 8. Static electrical characteristics – SW3
All parameters are specified at TA = -40 °C to 105 °C, VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VPVIN3 = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(21)
Switch mode supply SW3
VPVIN3
Operating input voltage
2.8
–
4.5
V
VSW3
Nominal output voltage
–
Table 50
–
V
-3.0%
–
3.0%
-6.0%
–
6.0%
1500
–
–
mA
–
–
50
150
–
–
μA
1.95
1.45
3.0
2.25
4.05
3.05
A
VSW3ACC
ISW3
ISW3Q
Output voltage accuracy
• PWM, APS, 2.8 V < VPVIN3 < 4.5 V, 0 < ISW3 < 1.5 A, 0.9 V < VSW3
< 1.65 V
• PFM, steady state (2.8 V < VPVIN3 < 4.5 V, 0 < ISW3 < 50 mA), 0.9 V
< VSW3 < 1.65 V
Rated output load current, 2.8 V < VPVIN3 < 4.5 V, 0.9 V < VSW3 <
1.65 V, PWM, APS mode
Quiescent current
• PFM Mode
• APS Mode
ISW3LIM
Current limiter peak current detection, current through inductor
• SW3ILIM = 0
• SW3ILIM = 1
VSW3
%
Output ripple
–
5.0
–
mV
RONSW3P
SW3 P-MOSFET RDS(on)at VIN = VSW3IN = 3.3 V
–
205
235
m
RONSW3N
SW3 N-MOSFET RDS(on) at VIN = VSW3IN = 3.3 V
–
250
315
m
ISW3PQ
SW3 P-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
12
μA
ISW3NQ
SW3 N-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
4.0
μA
RSW3DIS
Discharge resistance during Off mode
–
600
–
VSW3OSH
Start-up overshoot, ISW3 = 0.0 mA, DVS clk = 25 mV/4 s, VIN = VPVIN3
= 4.5 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW3 = 0 mA, DVS clk =
25 mV/4 s, VIN = VPVIN3 = 4.5 V
–
–
500
μs
tONSW3
(22)
Notes
21.
Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any VR5100 regulator, or external system supply.
22.
The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VSW3IN - VSW3) =
ISW3* (DCR of Inductor +RONSW3P + PCB trace resistance).
VR5100
NXP Semiconductors
13
GENERAL PRODUCT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 9. Static electrical characteristics - SWBST
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, typical external
component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at VIN = VSWBSTIN = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Unit
Notes
2.8
–
4.5
V
(23)
Switch mode supply SWBST
VSWBSTIN
Input voltage range
VSWBST
Nominal output voltage
–
Table 52
–
V
ISWBST
Continuous load current
• 2.8 V VIN 3.0 V
• 3.0 V VIN 4.5 V
500
600
–
–
–
–
mA
Output voltage accuracy, 2.8 V VIN 4.5 V, 0 < ISWBST < ISWBSTMAX
-4.0
–
3.0
%
VSWBSTACC
ISWBSTQ
Quiescent current (auto mode)
–
222
289
A
VSWBST
Output ripple, 2.8 V VIN 4.5 V, 0 < ISWBST < ISWBSTMAX, excluding
reverse recovery of Schottky diode
–
–
120
mVp-p
ISWBSTLIM
Peak Current Limit
1400
2200
3200
mA
RDSONBST
MOSFET on resistance
–
206
306
m
ISWBSTHSQ
NMOS Off leakage, VSWBST = 4.5 V, SWBSTMODE [1:0] = 00
–
1.0
5.0
μA
VSWBSTOSH
Start-up overshoot, ISWBST = 0.0 mA
–
–
500
mV
Turn-on time, enable to 90% of VSWBST, ISWBST = 0.0 mA
–
–
2.0
ms
tONSWBST
(24)
Notes
23.
Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any VR5100 regulator, or external system supply.
24.
Only in Auto and APS modes.
Table 10. Static electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Operating input voltage
• Valid coin cell range
• Valid VIN
1.8
2.25
–
3.3
4.5
V
ISNVS
Operating load current, VINMIN < VIN < VINMAX
1.0
–
1000
A
VSNVS
Output voltage
• 5.0 A < ISNVS < 1000 A (OFF), 3.20 V < VIN < 4.5 V
• 5.0 A < ISNVS < 1000A (ON), 3.20 V < VIN < 4.5 V
• 5.0 A < ISNVS < 1000 A (Coin Cell mode), 2.84 V < VCOIN < 3.3 V
-5.0%
-5.0%
VCOIN-0.10
3.0
3.0
7.0%
5.0%
VCOIN
–
–
110
mV
1100
–
6750
A
Operating input voltage, valid coin cell range
1.8
–
3.3
V
ISNVS
Operating load current
1.0
–
1000
A
RDSONSNVS
Internal switch RDS(on)
–
–
100
Notes
VSNVS
VIN
VSNVSDROP
ISNVSLIM
Dropout voltage, 2.85 V < VIN < 2.9 V, 1.0 A < ISNVS < 1000 A
Current limit, VIN > VTH1
V
VSNVS DC, SWITCH
VLICELL
VR5100
14
NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 11. Dynamic electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, typical external component values, unless
otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(25),(26)
VSNVS
VSNVSTON
Turn-on time (load capacitor, 0.47 F), from VIN = VTH1 to 90% of
VSNVS, VCOIN = 0.0 V, ISNVS = 5.0 A
–
–
24
ms
VSNVSOSH
Start-up overshoot, ISNVS = 5.0 A
–
40
70
mV
VSNVSLOTR
Transient load response, 3.2 < VIN 4.5 V, ISNVS = 100 to 1000 A
2.8
–
–
V
VTL1
VIN falling threshold (VIN powered to coin cell powered)
2.45
2.70
3.05
V
VTH1
VIN Rising Threshold (coin cell powered to VIN powered)
2.5
2.75
3.10
V
VIN threshold hysteresis for VTH1-VTL1
5.0
-
-
mV
Output voltage during crossover, VCOIN > 2.9 V, Switch to LDO: VIN >
VTH1, ISNVS = 100 A, LDO to Switch: VIN < VTL1, ISNVS = 100 A
2.45
-
-
V
VHYST1
VSNVSCROSS
Notes
25.
The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to 3.0 V.
26.
From coin cell insertion to VSNVS = 1.0 V, the delay time is typically 400 ms.
Table 12. Static electrical characteristics - LDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDOIN1 = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN1 = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
VLDO1NOM
+0.250
–
–
4.5
4.5
V
(27)
–
Table 55
–
V
Rated output load current
100
–
–
mA
Output voltage tolerance, VLDO1INMIN < VLDOIN1 < 4.5 V, 0.0 mA <
ILDO1 < 100 mA, LDO1 = 1.8 V to 3.3 V
-3.0
–
3.0
%
–
13
–
A
122
167
280
mA
LDO1 linear regulator
VLDOIN1
VLDO1NOM
ILDO1
VLDO1TOL
ILDO1Q
ILDO1LIM
Operating input voltage
• 1.8 V VLDO1NOM 2.5 V
• 2.6 V VLDO1NOM 3.3 V
Nominal output voltage
Quiescent current, no load, change in IVIN, when LDO1 enabled
Current limit, ILDO1 when VLDO1 is forced to VLDO1NOM/2
Notes
27.
Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any VR5100 regulator, or external system supply.
VR5100
NXP Semiconductors
15
GENERAL PRODUCT CHARACTERISTICS
ELECTRICAL CHARACTERISTICS
Table 13. Dynamic electrical characteristics - LDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDOIN1 = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDOIN1 = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
dB
Notes
LDO1 linear regulator
PSRRLDO1
PSRR, ILDO1 = 75 mA, 20 Hz to 20 kHz
• LDO1 = 1.8 V to 3.3 V, VLDOIN1 = VLDO1INMIN + 100 mV
• LDO1 = 1.8 V to 3.3 V, VLDOIN1 = VLDO1NOM + 1.0 V
35
52
40
60
–
–
NOISELDO1
Output noise density, VLDOIN1 = VLDO1INMIN, ILDO1 = 75 mA
• 100 Hz to 2.7 V (typical)
1 VIN 2.7 V (typical)
0
ENI
Power on interrupt bit —ENI is set to 1 when the turn on event occurs. This flag can only be cleared by writing a 1. Writing a 0 has no
effect.
0 Power on has not occurred.
1 Power on has occurred.
VR5100
NXP Semiconductors
61
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.2
Interrupt status mask register 0 (INTMASK0)
INTMASK0 is the mask register for the status interrupt register INTSTAT0. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 93. Interrupt status mask register 0 (INTMASK0)
Access: user read/write (54)
Address: 0x06 functional page
7
6
R
W
Default
0
5
4
3
2
1
0
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
ENM
1
1
1
1
1
1
0
= Unimplemented or reserved
Notes
54.
Read: Anytime
Write: Anytime
Table 94. INTMASK0 field descriptions
Field
Description
5
THERM130M
130 °C thermal interrupt mask bit
0 THERM130I unmasked
1 THERM130I masked
4
THERM125M
125 °C thermal interrupt mask bit
0 THERM125I unmasked
1 THERM125I masked
3
THERM120M
120 °C thermal interrupt mask bit
0 THERM120I unmasked
1 THERM120I masked
2
THERM110M
110 °C thermal interrupt mask bit
0 THERM110I unmasked
1 THERM110I masked
1
LOWVINM
0
ENM
Low-voltage interrupt mask bit
0 LOWVINI unmasked
1 LOWVINI masked
Power on interrupt mask bit
0 ENI unmasked
1 ENI masked
VR5100
62
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.3
Interrupt sense register 0 (INTSENSE0)
This register has seven read-only sense bits. These sense bits reflects the actual state of the corresponding function.
Table 95. Interrupt sense register 0 (INTSENSE0)
Access: user read-only (55)
Address: 0x07 functional page
7
R
6
VDDOTPS
5
4
3
2
1
0
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
ENS
X (58)
X (58)
X (58)
X (58)
X (57)
X (56)
W
Default
X (59)
0
= Unimplemented or reserved
Notes
55.
56.
57.
58.
59.
Read: Anytime
Default value depends on the initial EN pin state.
Default value depends on the initial VIN voltage.
Default value depends on the initial temperature of the die.
Default value depends on the initial VDDOTP pin state.
Table 96. INTSENSE0 field descriptions
Field
7
VDDOTPS
Description
VDDOTP voltage sense bit
0 VDDOTP grounded.
1 VDDOTP to VDIG or greater.
5
THERM130S
130 °C thermal interrupt sense bit
0 Die temperature below THERM130 threshold.
1 Die temperature above THERM130 threshold.
4
THERM125S
125 °C thermal interrupt sense bit
0 Die temperature below THERM125 threshold.
1 Die temperature has crossed THERM125 threshold.
3
THERM120S
120 °C thermal interrupt sense bit
0 Die temperature below THERM120 threshold.
1 Die temperature has crossed THERM120 threshold.
2
THERM110S
110 °C thermal interrupt sense bit
0 Die temperature below THERM110 threshold.
1 Die temperature has crossed THERM110 threshold.
1
LOWVINS
0
ENS
Low-voltage interrupt sense bit
0 VIN > 2.7 V (typical)
1 VIN 2.7 V (typical)
Power on interrupt sense bit
0 EN low.
1 EN high.
VR5100
NXP Semiconductors
63
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.4
Interrupt status register 1 (INTSTAT1)
INSTAT1 is one of the four status interrupt registers. This register contains four status flags. Write a logic 1 to clear a flag.
Table 97. Status interrupt register 1 (INTSTAT1)
Access: user read/write (60)
Address: 0x08 functional page
7
6
5
R
W
Default
0
0
4
3
SW3FAULTI
SW2FAULTI
0
0
0
2
0
1
0
SW1FAULTI
SW1FAULTI
0
0
= Unimplemented or reserved
Notes
60.
Read: Anytime
Write: Anytime
Table 98. INTSTAT1 field descriptions
Field
Description
4
SW3FAULTI
SW3 overcurrent interrupt bit — SW3FAULTI is set to 1 when the SW3 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW3 in normal operation
1 SW3 above current limit
3
SW2FAULTI
SW2 overcurrent interrupt bit — SW2FAULTI is set to 1 when the SW2 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW2 in normal operation
1 SW2 above current limit
1
SW1FAULTI
SW1 overcurrent interrupt bit — SW1FAULTI is set to 1 when the SW1 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW1 in normal operation
1 SW1 above current limit
0
SW1FAULTI
SW1 overcurrent interrupt bit — SW1FAULTI is set to 1 when the SW1 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW1 in normal operation
1 SW1 above current limit
6.6.5.3.5
Interrupt status mask register 1 (INTMASK1)
INTMASK1 is the mask register for the status interrupt register INTSTAT1. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 99. Interrupt status mask register 1 (INTMASK1)
Access: user read/write (61)
Address: 0x09 functional page
7
6
5
R
W
Default
0
0
0
4
3
SW3FAULTM
SW2FAULTM
1
1
2
0
1
0
SW1FAULTM
SW1FAULTM
1
1
= Unimplemented or reserved
Notes
61.
Read: Anytime
Write: Anytime
VR5100
64
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 100. INTMASK1 field descriptions
Field
Description
4
SW3FAULTM
SW3 overcurrent interrupt mask bit
0 SW3FAULTI Unmasked
1 SW3FAULTI Masked
3
SW2FAULTM
SW2 overcurrent interrupt mask bit
0 SW2FAULTI Unmasked
1 SW2FAULTI Masked
1
SW1FAULTM
SW1 overcurrent interrupt mask bit
0 SW1FAULTI Unmasked
1 SW1FAULTI Masked
0
SW1FAULTM
SW1 overcurrent interrupt mask bit
0 SW1FAULTI Unmasked
1 SW1FAULTI Masked
6.6.5.3.6
Interrupt sense register 1 (INTSENSE1)
This register has four read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Table 101. Interrupt sense register 1 (INTSENSE1)
Access: user read-only (62)
Address: 0x0A functional page
7
6
5
R
4
3
SW3FAULTS
SW2FAULTS
X (63)
X (63)
2
1
0
SW1FAULTS
SW1FAULTS
X (63)
X (63)
W
Default
0
0
0
0
= Unimplemented or reserved
Notes
62.
Read: Anytime
63.
Default value depends on the regulator initial state
Table 102. INTSENSE1 field descriptions
Field
Description
4
SW3FAULTS
SW3 overcurrent sense bit
0 SW3 in normal operation
1 SW3 above current limit
3
SW2FAULTS
SW2 overcurrent sense bit
0 SW2 in normal operation
1 SW2 above current limit
1
SW1FAULTS
SW1 overcurrent sense bit
0 SW1 in normal operation
1 SW1 above current limit
0
SW1FAULTS
SW1 overcurrent sense bit
0 SW1 in normal operation
1 SW1 above current limit
VR5100
NXP Semiconductors
65
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.7
Interrupt status register 3 (INTSTAT3)
INSTAT3 is one of the four status interrupt registers. This register contains four status flags. Write a logic 1 to clear a flag.
Table 103. Status interrupt register 3 (INTSTAT3)
Access: user read/write (64)
Address: 0x0E functional page
R
W
Default
7
6
OTP_ECCI
OTP_AUTO_BL
OW_DONEI
0
0
5
4
3
2
1
0
SWBSTFAULTI
0
0
0
0
0
0
= Unimplemented or reserved
Notes
64.
Read: Anytime
Write: Anytime
Table 104. INTSTAT3 field descriptions
Field
Description
7
OTP_ECCI
OTP error interrupt bit — OTP_ECCI is set to 1 when an error is detected in OTP registers. This flag can only be cleared by writing
a 1. Writing a 0 has no effect.
0 No error detected
1 OTP error detected
OTP auto fuse blow interrupt bit — OTP_AUTO_BLOW_DONEI is set to 1 after the Auto Fuse Blow Sequence is completed. This
6
flag can only be cleared by writing a 1. Writing a 0 has no effect.
OTP_AUTO_BL 0 OTP Auto Fuse Blow Sequence not completed
OW_DONEI
1 OTP Auto Fuse Blow Sequence completed
SWBST overcurrent limit interrupt bit — SWBSTFAULTI is set to 1 when the SWBST regulator is in current limit protection. This flag
can only be cleared by writing a 1. Writing a 0 has no effect.
0
SWBSTFAULTI 0 SWBST in normal operation
1 SWBST above current limit
6.6.5.3.8
Interrupt status mask register 3 (INTMASK3)
INTMASK3 is the mask register for the status interrupt register INTSTAT3. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 105. Interrupt status mask register 3 (INTMASK3)
Access: user read/write (65)
Address: 0x0F functional page
R
W
Default
7
6
OTP_ECCM
OTP_AUTO_BL
OW_DONEM
1
1
5
4
3
2
1
0
SWBSTFAULTM
0
0
0
1
0
1
= Unimplemented or reserved
Notes
65.
Read: Anytime
Write: Anytime
VR5100
66
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 106. INTMASK3 field descriptions
Field
Description
OTP error interrupt mask bit
0 OTP_ECCI unmasked
1 OTP_ECCI masked
7
OTP_ECCM
OTP auto blow mask bit
6
OTP_AUTO_BLO 0 OTP_AUTO_BLOW_DONEI unmasked
W_DONEM
1 OTP_AUTO_BLOW_DONEI masked
SWBST overcurrent limit interrupt mask bit
0 SWBSTFAULTI unmasked
1 SWBSTFAULTI masked
0
SWBSTFAULTM
6.6.5.3.9
Interrupt sense register 3 (INTSENSE3)
This register has four read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Table 107. Interrupt sense register 3 (INTSENSE3)
Access: user read-only (66)
Address: 0x10 functional page
R
7
6
OTP_ECCS
OTP_AUTO_B
LOW_DONES
0
0
5
4
3
2
1
0
SWBSTFAULTS
W
Default
0
0
0
0
0
X (67)
= Unimplemented or reserved
Notes
66.
Read: Anytime
67.
Default value depends on the regulator initial state
Table 108. INTSENSE3 field descriptions
Field
7
OTP_ECCS
Description
OTP error sense bit
0 No error detected
1 OTP error detected
OTP auto blow sense bit — This bit is high while the auto blow sequence is running. Do not read/write the OTP TBB registers while
6
this bit is 1.
OTP_AUTO_BLO 0 SW2 in normal operation
W_DONES
1 SW2 at current limit
0
SWBSTFAULTS
SWBST overcurrent limit sense bit
0 SWBST in normal operation
1 SWBST above current limit
VR5100
NXP Semiconductors
67
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.10
Interrupt status register 4 (INTSTAT4)
INSTAT4 is one of the four status interrupt registers. This register contains six status flags. Write a logic 1 to clear a flag.
Table 109. Status interrupt register 4 (INTSTAT4)
Access: user read/write (68)
Address: 0x11 functional page
7
6
R
W
Default
0
0
5
4
3
2
1
0
LDO4FAULTI
LDO3FAULTI
V33FAULTI
VSDFAULTI
LDO2FAULTI
LDO1FAULTI
0
0
0
0
0
0
= Unimplemented or reserved
Notes
68.
Read: Anytime
Write: Anytime
Table 110. INTSTAT4 field descriptions
Field
Description
5
LDO4FAULTI
LDO4 overcurrent interrupt bit — LDO4FAULTI is set to 1 when the LDO4 regulator is in current limit protection. This flag can only
be cleared by writing a 1. Writing a 0 has no effect.
0 LDO4 in normal operation
1 LDO4 above current limit
4
LDO3FAULTI
LDO3 overcurrent interrupt bit — LDO3FAULTI is set to 1 when the LDO3 regulator is in current limit protection. This flag can only
be cleared by writing a 1. Writing a 0 has no effect.
0 LDO3 in normal operation
1 LDO3 above current limit
3
V33FAULTI
V33 overcurrent interrupt bit — V33FAULTI is set to 1 when the V33 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 V33 in normal operation
1 V33 above current limit
2
VSDFAULTI
VSD overcurrent interrupt bit — VSDFAULTI is set to 1 when the VSD regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 VSD in normal operation
1 VSD above current limit
1
LDO2FAULTI
LDO2 overcurrent interrupt bit — LDO2FAULTI is set to 1 when the LDO2 regulator is in current limit protection. This flag can only
be cleared by writing a 1. Writing a 0 has no effect.
0 LDO2 in normal operation range.
1 LDO2 above current limit
0
LDO1FAULTI
LDO1 overcurrent interrupt bit — LDO1FAULTI is set to 1 when the LDO1 regulator is in current limit protection. This flag can only
be cleared by writing a 1. Writing a 0 has no effect.
0 LDO1 in normal operation range.
1 LDO1 above current limit
VR5100
68
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.11
Interrupt status mask register 4 (INTMASK4)
INTMASK4 is the mask register for the status interrupt register INTSTAT4. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 111. Interrupt status mask register 4 (INTMASK4)
Access: user read/write (69)
Address: 0x12 functional page
7
6
R
W
Default
0
5
4
3
2
1
0
LDO4FAULTM
LDO3FAULTM
V33FAULTM
VSDFAULTM
LDO2FAULTM
LDO1FAULTM
1
1
1
1
1
1
0
= Unimplemented or reserved
Notes
69.
Read: Anytime
Write: Anytime
Table 112. INTMASK4 field descriptions
Field
Description
5
LDO4FAULTM
LDO4 overcurrent interrupt mask bit
0 LDO4FAULTI unmasked
1 LDO4FAULTI masked
4
LDO3FAULTM
LDO3 overcurrent interrupt mask bit
0 LDO3FAULTI unmasked
1 LDO3FAULTI masked
3
V33FAULTM
V33 overcurrent interrupt mask bit
0 V33FAULTI unmasked
1 V33FAULTI masked
2
VSDFAULTM
VSD overcurrent interrupt mask bit
0 VSDFAULTI unmasked
1 VSDFAULTI masked
1
LDO2FAULTM
LDO2 overcurrent interrupt mask bit
0 LDO2FAULTI unmasked
1 LDO2FAULTI masked
0
LDO1FAULTM
LDO1 overcurrent interrupt mask bit
0 LDO1FAULTI unmasked
1 LDO1FAULTI masked
VR5100
NXP Semiconductors
69
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.12
Interrupt sense register 4 (INTSENSE4)
This register has four read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Access: user read-only (70)
Address: 0x13 functional page
7
6
R
5
4
3
2
1
0
LDO4FAULTS
LDO3FAULTS
V33FAULTS
VSDFAULTS
LDO2FAULTS
LDO1FAULTS
X (71)
X (71)
X (71)
X (71)
X (71)
X (71)
W
Default
0
0
= Unimplemented or reserved
Notes
70.
Read: Anytime
71.
Default value depends on the regulator initial state
Table 113. INTSENSE4 field descriptions
Field
Description
5
LDO4FAULTS
LDO4 overcurrent sense bit
0 LDO4 in normal operation
1 LDO4 above current limit
4
LDO3FAULTS
LDO3 overcurrent sense bit
0 LDO3 in normal operation
1 LDO3 above current limit
3
V33FAULTS
V33 overcurrent sense bit
0 V33 in normal operation
1 V33 above current limit
2
VSDFAULTS
VSD overcurrent sense bit
0 VSD in normal operation
1 VSD above current limit
1
LDO2FAULTS
LDO2 overcurrent sense bit
0 LDO2 in normal operation
1 LDO2 above current limit
0
LDO1FAULTS
LDO1 overcurrent sense bit
0 LDO1 in normal operation
1 LDO1 above current limit
VR5100
70
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.13
Coin cell control register (COINCTL)
This register is used to control the coin cell charger.
Table 114. Coin cell control register (COINCTL)
Access: user read/write (72)
Address: 0x1A functional page
7
6
5
4
3
R
2
1
COINCHEN
W
Default
0
0
0
0
0
0
VCOIN
0
0
0
= Unimplemented or reserved
Notes
72.
Read: Anytime
Write: Anytime
Table 115. COINCTL field descriptions
Field
3
COINCHEN
2:0
VCOIN
6.6.5.3.14
Description
Coin cell charger enable bit
0 Coin cell charger disabled.
1 Coin cell charger enabled.
Coin cell charger output voltage selection — This field is used to set the coin cell charging voltage from 2.50 V to 3.30 V. See
Table 63 for all options selectable through these bits.
Power control register (PWRCTL)
Table 116. Power control register (PWRCTL)
Access: user read/write (73)
Address: 0x1B functional page
R
W
7
6
REGSCPEN
STBYINV
0
0
Default
5
4
3
STBYDLY
0
2
ENBDBNC
1
0
0
1
0
ENRSTEN
RESTARTEN
0
0
= Unimplemented or reserved
Notes
73.
Read: Anytime
Write: Anytime
VR5100
NXP Semiconductors
71
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 117. PWRCTL field descriptions
Field
Description
7
REGSCPEN
Short-circuit protection enable bit — When REGSCPEN is set to 1, whenever a current limit event occurs on a LDO regulator, this
regulator is shutdown.
0 Short-circuit protection disabled
1 Short-circuit protection enabled
6
STBYINV
STBY inversion bit —STBYINV is used to control the polarity of the STBY pin.
0 Standby pin is active high
1 Standby pin is active low
4:3
STBYDLY
STBY delay bits — STBYDLY is used to set the delay between a standby request from the STBY pin and the entering in standby
mode.
00 No delay
01 One 32 kHz period (default)
10 Two 32 kHz periods
11 Three 32 kHz periods
3:2
ENDBNC
EN programmable debouncer bits — ENDBNC is used to set the debounce time for the EN input pin. For configuration, see
Table 31.
1
ENRSTEN
EN reset enable bit — When set to 1, the VR5100 can enter OFF mode when the EN pin is held low for 4 seconds or longer. See
EN Pin section for details.
0 Disallow OFF mode after EN held low
1 Allow OFF mode after ENheld low
0
RESTARTEN
Restart enable bit — When set to 1, the VR5100 restarts automatically after a power off event generated by the EN (held low for 4
seconds or longer) when PWR_CFG bit = 1.
0 Automatic restart disabled.
1 Automatic restart enabled.
6.6.5.3.15
Embedded memory register A (MEMA)
Table 118. Embedded memory register A (MEMA)
Access: user read/write (74)
Address: 0x1C functional page
7
6
5
4
R
2
1
0
0
0
0
0
MEMA
W
Default
3
0
0
0
0
= Unimplemented or reserved
Notes
74.
Read: Anytime
Write: Anytime
Table 119. MEMA field descriptions
Field
Description
7:0
MEMA
Memory bank A — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
VR5100
72
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.16
Embedded memory register B (MEMB)
Table 120. Embedded memory register B (MEMB)
Address: 0x1D functional page
7
6
5
Access: user read/write
4
R
2
1
0
0
0
0
0
MEMB
W
Default
3
0
0
0
0
= Unimplemented or reserved
Notes
75.
Read: Anytime
Write: Anytime
Table 121. MEMB field descriptions
Field
Description
7:0
MEMB
Memory bank B — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
6.6.5.3.17
Embedded memory register C (MEMC)
Table 122. Embedded memory register C (MEMC)
Access: user read/write (76)
Address: 0x1E functional page
7
6
5
4
R
2
1
0
0
0
0
0
MEMC
W
Default
3
0
0
0
0
= Unimplemented or reserved
Notes
76.
Read: Anytime
Write: Anytime
Table 123. MEMC field descriptions
Field
Description
7:0
MEMC
Memory bank C — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
VR5100
NXP Semiconductors
73
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.18
Embedded memory register D (MEMD)
Table 124. Embedded memory register D (MEMD)
Access: user read/write (77)
Address: 0x1F functional page
7
6
5
4
R
2
1
0
0
0
0
0
MEMD
W
Default
3
0
0
0
0
= Unimplemented or reserved
Notes
77.
Read: Anytime
Write: Anytime
Table 125. MEMD field descriptions
Field
Description
7:0
MEMD
Memory bank D — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
6.6.5.3.19
SW1 voltage control register (SW1VOLT)
This register is used to set the output voltage of the SW1 regulator in normal operation.
Table 126. SW1 voltage control register (SW1VOLT)
Access: user read/write (78)
Address: 0x20 functional page
7
6
5
4
3
R
1
0
X (79)
X (79)
SW1
W
Default
2
0
0
0
X (79)
X (79)
X (79)
= Unimplemented or reserved
Notes
78.
Read: Anytime
Write: Anytime
79.
Default value depends on OTP content.
Table 127. SW1VOLT field descriptions
Field
4:0
SW1
Description
SW1 output voltage — Refer to Table 46
VR5100
74
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.20
SW1 standby voltage control register (SW1STBY)
This register is used to set the output voltage of the SW1 regulator in standby operation.
Table 128. SW1 standby voltage control register (SW1STBY)
Access: user read/write (80)
Address: 0x21 functional page
7
6
5
4
3
R
1
0
X (81)
X (81)
SW1STBY
W
Default
2
0
0
0
X (81)
X (81)
X (81)
= Unimplemented or reserved
Notes
80.
Read: Anytime
Write: Anytime
81.
Default value depends on OTP content.
Table 129. SW1STBY field descriptions
Field
4:0
SW1STBY
6.6.5.3.21
Description
SW1 standby output voltage — Refer to Table 46
SW1 Sleep mode voltage control register (SW1OFF)
This register is used to set the output voltage of the SW1 regulator in Sleep mode operation.
Table 130. SW1 Sleep mode voltage control register (SW1OFF)
Access: user read/write (82)
Address: 0x22 functional page
7
6
5
4
3
R
1
0
X (83)
X (83)
SW1OFF
W
Default
2
0
0
0
X (83)
X (83)
X (83)
= Unimplemented or Reserved
Notes
82.
Read: Anytime
Write: Anytime
83.
Default value depends on OTP content.
Table 131. SW1OFF field descriptions
Field
4:0
SW1STBY
Description
SW1 Sleep mode output voltage — Refer to Table 46
VR5100
NXP Semiconductors
75
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.22
SW1 Switching mode selector register (SW1MODE)
This register is used to set the switching mode of the SW1 regulator.
Table 132. SW1 Switching mode selector register (SW1MODE)
Access: user read/write (84)
Address: 0x23 functional page
7
6
R
4
3
2
SW1OMODE
W
Default
5
0
0
0
1
0
X (85)
X (85)
SW1MODE
X (85)
0
X (85)
= Unimplemented or reserved
Notes
84.
Read: Anytime
Write: Anytime
85.
Default value depends on OTP content.
Table 133. SW1MODE field descriptions
Field
5
SW1OMODE
3:0
SW1MODE
6.6.5.3.23
Description
SW1 Off mode bit— This bit configures the mode entered by SW1 after a turn-off event
0 OFF mode entered after a turn-off event.
1 Sleep mode entered after a turn-off event.
SW1 Switching mode selector — Refer to Table 41
SW1 configuration register (SW1CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW1 regulator.
Table 134. SW1 configuration register (SW1CONF)
Access: user read/write (86)
Address: 0x24 functional page
7
R
5
SW1DVSSPEE
D
W
Default
6
0
X (87)
4
3
SW1PHASE
0
2
1
SW1ILIM
SW1FREQ
0
X (87)
0
X (87)
0
X (87)
= Unimplemented or reserved
Notes
86.
Read: Anytime
Write: Anytime
87.
Default value depends on OTP content.
VR5100
76
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 135. SW1CONF field descriptions
Field
Description
6
SW1DVSSPEED
5:4
SW1PHASE
SW1 phase clock bit— SW1PHASE is used to set the phase clock for SW1. Refer to Table 43.
3:2
SW1FREQ
SW1 switching frequency— SW1PHASE is used to set the desired switching frequency for SWA. Refer to Table 45.
SW1 current limiter bit— This bit configures the current limit for SW1.
0 4 A (typ).
1 2.0 A (typ).
0
SW1ILIM
6.6.5.3.24
SW1 DVS speed bit— This bit configures the DVS stepping rates speed for SW1. Refer to the Table 42.
0 25 mV step each 2.0 s.
1 25 mV step each 4.0 s.
SW1 configuration register (SW1CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW1 regulator.
Table 136. SW1 configuration register (SW1CONF)
Access: user read/write X (88)
Address: 0x32 functional page
7
R
6
5
SW1DVSSPEED
W
Default
0
X (89)
4
3
SW1PHASE
0
2
1
SW1FREQ
0
X (89)
0
SW1ILIM
X (89)
0
X (89)
= Unimplemented or reserved
Notes
88.
Read: Anytime
Write: Anytime
89.
Default value depends on OTP content.
Table 137. SW1CONF field descriptions
Field
6
SW1DVSSPEED
5:4
SW1PHASE
3:2
SW1FREQ
0
SW1ILIM
Description
SW1 DVS speed bit— This bit configures the DVS stepping rates speed for SW1. Refer to the Table 42.
0 25 mV step each 2.0 s.
1 25 mV step each 4.0 s.
SW1 phase clock bit— SW1PHASE is used to set the phase clock for SW1. Refer to Table 43.
SW1 switching frequency— SW1PHASE is used to set the desired switching frequency for SW1. Refer to Table 45.
SW1 current limiter bit— This bit configures the current limit for SW1.
0 4.0 A (typ).
1 2.0 A (typ).
VR5100
NXP Semiconductors
77
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.25
SW2 voltage control register (SW2VOLT)
This register is used to set the output voltage of the SW2 regulator in normal operation.
Table 138. SW2 voltage control register (SW2VOLT)
Access: user read/write (90)
Address: 0x35 functional page
7
6
R
4
3
SW2_HI
W
Default
5
0
0
X (91)
2
1
0
X (91)
X (91)
SW2
X (91)
X (91)
X (91)
= Unimplemented or reserved
Notes
90.
Read: Anytime
Write: Anytime
91.
Default value depends on OTP content.
Table 139. SW2VOLT field descriptions
Field
4:0
SW2
5
SW2_HI
6.6.5.3.26
Description
SW2 output voltage — Refer to Table 48.
SW2 output voltage range —This bit configures the range of SW2 Output voltage. Refer to Table 48.
0 Low output voltage settings
1 High output voltage settings
SW2 standby voltage control register (SW2STBY)
This register is used to set the output voltage of the SW2 regulator in standby operation.
Table 140. SW2 standby voltage control register (SW2STBY)
Access: user read/write (92)
Address: 0x36 functional page
7
6
R
4
3
SW2_HI
W
Default
5
0
0
X (93)
2
1
0
X (93)
X (93)
SW2STBY
X (93)
X (93)
X (93)
= Unimplemented or reserved
Notes
92.
Read: Anytime
Write: Anytime
93.
Default value depends on OTP content.
Table 141. SW2STBY field descriptions
Field
4:0
SW2STBY
5
SW2_HI
Description
SW2 standby output voltage — Refer to Table 48.
SW2 output voltage range —This bit configures the range of SW2 output voltage. Refer to Table 48.
0 Low output voltage settings
1 High output voltage settings
VR5100
78
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.27
SW2 Sleep mode voltage control register (SW2OFF)
This register is used to set the output voltage of the SW2 regulator in Sleep mode operation.
Table 142. SW2 Sleep mode voltage control register (SW2OFF)
Access: user read/write (94)
Address: 0x37 functional page
7
6
R
4
3
SW2_HI
W
Default
5
0
0
X (95)
2
1
0
X (95)
X (95)
SW2OFF
X (95)
X (95)
X (95)
= Unimplemented or reserved
Notes
94.
Read: Anytime
Write: Anytime
95.
Default value depends on OTP content.
Table 143. SW2OFF field descriptions
Field
4:0
SW2STBY
5
SW2_HI
6.6.5.3.28
Description
SW2 Sleep mode output voltage — Refer to Table 48.
SW2 output voltage range —This bit configures the range of SW2 output voltage. Refer to Table 48.
0 Low output voltage settings
1 High output voltage settings
SW2 Switching mode selector register (SW2MODE)
This register is used to set the switching mode of the SW2 regulator.
Table 144. SW2 Switching mode selector register (SW2MODE)
Access: user read/write (96)
Address: 0x38 functional page
7
6
R
4
3
2
SW2OMODE
W
Default
5
0
0
0
1
0
X (97)
X (97)
SW2MODE
0
X (97)
X (97)
= Unimplemented or reserved
Notes
96.
Read: Anytime
Write: Anytime
97.
Default value depends on OTP content.
Table 145. SW2MODE field descriptions
Field
5
SW2OMODE
3:0
SW2MODE
Description
SW2 Off mode bit— This bit configures the mode entered by SW2 after a turn-off event
0 OFF mode entered after a turn-off event.
1 Sleep mode entered after a turn-off event.
SW2 Switching mode selector — Refer to Table 41.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.29
SW2 configuration register (SW2CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW2 regulator.
Table 146. SW2 configuration register (SW2CONF)
Access: user read/write (98)
Address: 0x39 functional page
7
R
6
5
SW2DVSSPEE
D
W
Default
0
X (99)
4
3
SW2PHASE
0
2
1
0
SW2FREQ
X (99)
0
SW2ILIM
X (99)
X (99)
0
= Unimplemented or reserved
Notes
98.
Read: Anytime
Write: Anytime
99.
Default value depends on OTP content.
Table 147. SW2CONF field descriptions
Field
Description
6
SW2DVSSPEED
5:4
SW2PHASE
3:2
SW2FREQ
0
SW2ILIM
6.6.5.3.30
SW2 DVS Speed bit- This bit configures the DVS stepping rates speed for SW2. Refer to the Table 42.
0 25 mV step each 2.0 s.
1 25 mV step each 4.0 s.
SW2 phase clock bit— SW2PHASE is used to set the phase clock for SW2. Refer to Table 43.
SW2 switching frequency— SW2PHASE is used to set the desired switching frequency for SW2. Refer to Table 45.
SW2 current limiter bit— This bit configures the current limit for SW2.
0 2.75 A (typ).
1 2.0 A (typ).
SW3 voltage control register (SW3VOLT)
This register is used to set the output voltage of the SW3 regulator in normal operation.
Table 148. SW3 voltage control register (SW3VOLT)
Access: user read/write (100)
Address: 0x3C functional page
7
6
5
4
3
R
1
0
X (101)
X (101)
SW3
W
Default
2
0
0
0
X (101)
X (101)
X (101)
= Unimplemented or reserved
Notes
100. Read: Anytime
Write: Anytime
101. Default value depends on OTP content.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 149. SW3VOLT field descriptions
Field
4:0
SW3
6.6.5.3.31
Description
SW3 output voltage — Refer to Table 50.
SW3 standby voltage control register (SW3STBY)
This register is used to set the output voltage of the SW3 regulator in standby operation.
Table 150. SW3 standby voltage control register (SW3STBY)
Access: user read/write (102)
Address: 0x3D functional page
7
6
5
4
3
R
1
0
X (103)
X (103)
SW3STBY
W
Default
2
0
0
0
X (103)
X (103)
X (103)
= Unimplemented or reserved
Notes
102. Read: Anytime
Write: Anytime
103. Default value depends on OTP content.
Table 151. SW3STBY field descriptions
Field
4:0
SW3STBY
6.6.5.3.32
Description
SW3 standby output voltage — Refer to Table 50.
SW3 Sleep mode voltage control register (SW3OFF)
This register is used to set the output voltage of the SW3 regulator in sleep mode operation.
Table 152. SW3 Sleep mode voltage control register (SW3OFF)
Access: user read/write (104)
Address: 0x3E functional page
7
6
5
4
3
R
1
0
X (105)
X (105)
SW3OFF
W
Default
2
0
0
0
X (105)
X (105)
X (105)
= Unimplemented or reserved
Notes
104. Read: Anytime
Write: Anytime
105. Default value depends on OTP content.
Table 153. SW3OFF field descriptions
Field
4:0
SW3STBY
Description
SW3 Sleep mode output voltage — Refer to Refer to Table 50.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
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6.6.5.3.33
SW3 Switching mode selector register (SW3MODE)
This register is used to set the switching mode of the SW3 regulator.
Table 154. SW3 Switching mode selector register (SW3MODE)
Access: user read/write (106)
Address: 0x3F functional page
7
6
R
4
3
2
SW3OMODE
W
Default
5
0
0
0
1
0
X (107)
X (107)
SW3MODE
X (107)
0
X (107)
= Unimplemented or reserved
Notes
106. Read: Anytime
Write: Anytime
107. Default value depends on OTP content.
Table 155. SW3MODE field descriptions
Field
5
SW3OMODE
3:0
SW3MODE
6.6.5.3.34
Description
SW3 Off mode bit— This bit configures the mode entered by SW3 after a turn-off event
0 OFF mode entered after a turn-off event.
1 Sleep mode entered after a turn-off event.
SW3 Switching mode selector — Refer to Table 41.
SW3 configuration register (SW3CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW3 regulator.
Table 156. SW3 configuration register (SW3CONF)
Access: user read/write (108)
Address: 0x40 functional page
7
R
5
SW3DVSSPEE
D
W
Default
6
0
X (109)
4
SW3PHASE
0
3
2
1
SW3FREQ
0
X (109)
X (109)
0
SW3ILIM
0
X (109)
= Unimplemented or reserved
Notes
108. Read: Anytime
Write: Anytime
109. Default value depends on OTP content.
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CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 157. SW3CONF field descriptions
Field
Description
SW3 DVS speed bit— This bit configures the DVS stepping rates speed for SW3. Refer to the Table 42.
0 25 mV step each 2.0 s.
1 25 mV step each 4.0 s.
6
SW3DVSSPEED
5:4
SW3PHASE
SW3 phase clock bit— SW3PHASE is used to set the phase clock for SW3. Refer to Table 43.
3:2
SW3FREQ
SW3 switching frequency— SW3PHASE is used to set the desired switching frequency for SW3. Refer to Table 45.
SW3 current limiter bit— This bit configures the current limit for SW3.
0 2.75 A (typ).
1 2.0 A (typ).
0
SW3ILIM
6.6.5.3.35
SWBST setup and control register (SWBSTCTL)
This register is used to configure both the output voltage and switching modes of the SWBST regulator.
Table 158. SWBST configuration register (SWBSTCTL)
Access: user read/write (110)
Address: 0x66 functional page
7
R
6
5
4
SWBST1STBYMODE
W
Default
0
X (111)
X (111)
3
2
SWBST1MODE
0
X (111)
X (111)
1
0
SWBST1VOLT
X (111)
X (111)
= Unimplemented or reserved
Notes
110. Read: Anytime
Write: Anytime
111. Default value depends on OTP content.
Table 159. SWBSTCTL Field Descriptions
Field
Description
SWBST Switching mode in standby— SWBST1MODE is used to set the switching mode in Standby mode.
00 OFF
6:5
01 PFM
SWBST1STBYMODE
10 Auto (112)
11 APS
3:2
SWBST1MODE
SWBST Switching mode in normal operation— SWBST1MODE is used to set the switching mode on Normal operation.
00 OFF
01 PFM
10 Auto (112)
11 APS
1:0
SWBST1VOLT
SWBST output voltage— SWBST1VOLT is used to set the output voltage for SWBST.
00 5.000 V (typ).
01 5.050 V (typ).
10 5.100 V (typ).
11 5.150 V (typ).
Notes
112. In Auto mode, the controller automatically switches between PFM and APS modes depending on the load current. Regulator switches in Auto
mode if enabled in the startup sequence.
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CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.36
REFOUT control register (REFOUTCTL)
This register is used to control the REFOUT supply operation.
Table 160. REFOUT control register (REFOUTCTL)
Access: user read/write (113)
Address: 0x6A functional page
7
6
5
4
3
2
1
0
R
REFOUTEN
W
Default
0
0
0
0
0
0
0
0
= Unimplemented or reserved
Notes
113. Read: Anytime
Write: Anytime
Table 161. REFOUT field descriptions
Field
0
REFOUTEN
Description
REFOUT supply enable bit— REFOUTEN is used to enable or disable the REFOUT supply.
0 REFOUT supply disabled
1 REFOUT supply enabled
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CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.37
VSNVS control register (VSNVSCTL)
This register is used to control the VSNVS supply operation.
Table 162. VSNVS control register (VSNVSCTL)
Access: user read/write (114)
Address: 0x6B functional page
7
6
5
4
3
2
1
0
R
VSNVSVOLT
W
Default
0
0
0
0
X (115)
0
X (115)
X (115)
= Unimplemented or Reserved
Notes
114. Read: Anytime
Write: Anytime
115. Default value depends on OTP content.
Table 163. VSNVSCTL field descriptions
Field
Description
VSNVS output voltage configuration— VSNVSVOLT is used to configure the VSNVS output voltage. Values below are
typical voltages.
000 = RSVD
001 = RSVD
010 = RSVD
011 = RSVD
100 = RSVD
101 = RSVD
110 = 3.0 V (default)
111 = RSVD
2:0
VSNVSVOLT
6.6.5.3.38
LDO1 control register (LDO1CTL)
This register is used to configure output voltage, normal and standby mode operation of the LDO1 regulator.
Table 164. LDO1 control register (LDO1CTL)
Access: user read/write (116)
Address: 0x6C functional page
R
W
Default
7
6
5
4
LDO1OMODE
LDO1LPWR
LDO1STBY
LDO1EN
0
0
0
X (117)
3
2
1
0
X (117)
X (117)
LDO1
X (117)
X (117)
= Unimplemented or reserved
Notes
116. Read: Anytime
Write: Anytime
117. Default value depends on OTP content.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 165. LDO1CTL field descriptions
Field
Description
7
LDO1OMODE
LDO1 OFF mode bit—LDO1OMODE is used to configure LDO1 operating mode when a EN turn-off event occurs.
0 LDO1 in OFF mode if a EN turn off event occurs
1 LDO1 in Sleep mode if a EN turn off event occurs
6
LDO1LPWR
LDO1 Low-power mode enable bit— When LDO1LPWR is set to 1, LDO1 can enter Low-power mode per the conditions in the
Table 59.
0 Low-power mode disabled
1 Low-power mode enabled
5
LDO1STBY
LDO1 standby enable bit— When LDO1STBY is set to 1, LDO1 is turned off during Standby mode. Refer to Table 59.
0 LDO1 is ON during Standby mode.
1 LDO1 is OFF during Standby mode.
4
LDO1EN
3:0
LDO1
LDO1 enable bit — LDO1EN is used to enable or disable the LDO1 regulator.
0 LDO1 disabled
1 LDO1 enabled
LDO1 output voltage configuration— Refer to Table 55.
6.6.5.3.39
LDO2 control register (LDO2CTL)
This register is used to configure output voltage, Normal and Standby mode operation of the LDO2 regulator.
Table 166. LDO2 control register (LDO2CTL)
Access: user read/write (118)
Address: 0x6D functional page
R
W
Default
7
6
5
4
LDO2OMODE
LDO2LPWR
LDO2STBY
LDO2EN
0
0
0
X (119)
3
2
1
0
X (119)
X (119)
LDO2
X (119)
X (119)
= Unimplemented or reserved
Notes
118. Read: Anytime
Write: Anytime
119. Default value depends on OTP content.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 167. LDO2CTL field descriptions
Field
Description
7
LDO2OMODE
LDO2 OFF mode bit—LDO2OMODE is used to configure LDO2 operating mode when a EN turn-off event occurs.
0 LDO2 in OFF mode if a EN turn off event occurs
1 LDO2 in Sleep mode if a EN turn off event occurs
6
LDO2LPWR
LDO2 low power mode enable bit— When LDO2LPWR is set to 1, LDO2 can enter Low-power mode per the conditions in the LDO
Control table.
0 Low-power mode disabled
1 Low-power mode enabled
5
LDO2STBY
LDO2 standby enable bit— When LDO2STBY is set to 1, LDO2 is turned off during Standby mode. Refer to Table 59.
0 LDO2 is ON during Standby mode.
1 LDO2 is OFF during Standby mode.
4
LDO2EN
3:0
LDO2
LDO2 enable bit — LDO2EN is used to enable or disable the LDO2 regulator.
0 LDO2 disabled
1 LDO2 enabled
LDO2 output voltage configuration— Refer to Table 55.
6.6.5.3.40
VSD control register (VSDCTL)
This register is used to configure output voltage, Normal and Standby mode operation of the VSD regulator.
Table 168. VSD control register (VSDCTL)
Access: user read/write (120)
Address: 0x6E functional page
R
W
Default
7
6
5
4
VSDOMODE
VSDLPWR
VSDSTBY
VSDEN
0
0
0
X (121)
3
2
1
0
VSD
0
0
X (121)
X (121)
= Unimplemented or reserved
Notes
120. Read: Anytime
Write: Anytime
121. Default value depends on OTP content.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 169. VSDCTL field descriptions
Field
Description
7
VSDOMODE
VSD OFF mode bit— VSDOMODE is used to configure VSD operating mode when a EN turn-off event occurs.
0 VSD in OFF mode if a EN turn off event occurs
1 VSD in Sleep mode if a EN turn off event occurs
6
VSDLPWR
VSD low-power mode enable bit— When VSDLPWR is set to 1, VSD can enter Low-power mode per the conditions in Table 58.
0 Low-power mode disabled
1 Low-power mode enabled
5
VSDSTBY
VSD standby enable bit— When VSDSTBY is set to 1, VSD is turned off during Standby mode. Refer to Table 58.
0 VSD is ON during Standby mode.
1 VSD is OFF during Standby mode.
VSD enable bit — VSDEN is used to enable or disable the VSD regulator.
0 VSD disabled
1 VSD enabled
4
VSDEN
1:0
VSD
VSD output voltage configuration— Refer to Table 58.
6.6.5.3.41
V33 control register (V33CTL)
This register is used to configure output voltage, Normal and Standby mode operation of the V33 regulator.
Table 170. V33 control register (V33CTL)
Access: user read/write (122)
Address: 0x6F functional page
R
W
7
6
5
4
V33OMODE
V33LPWR
V33STBY
V33EN
0
0
0
X (123)
Default
3
2
1
0
V33
0
0
X (123)
X (123)
= Unimplemented or reserved
Notes
122. Read: Anytime
Write: Anytime
123. Default value depends on OTP content.
Table 171. V33CTL field descriptions
Field
7
V33OMODE
Description
V33 OFF mode bit— V33OMODE is used to configure V33 operating mode when a turn-off event (using pin EN) occurs.
0 V33 in OFF mode if a PWRON turn-off event (using pin EN) occurs
1 V33 in Sleep mode if a PWRON turn-off event (using pin EN) occurs
6
V33LPWR
V33 Low-power mode enable bit— When V33LPWR is set to 1, V33 can enter Low-power mode per the conditions in the Table 57.
0 Low-power mode disabled
1 Low-power mode enabled
5
V33STBY
V33 standby enable bit— When V33STBY is set to 1, V33 is turned off during Standby mode. Refer to Table 57.
0 V33 is ON during Standby mode.
1 V33 is OFF during Standby mode.
4
V33EN
1:0
V33
V33 enable bit — V33EN is used to enable or disable the V33 regulator.
0 V33 disabled
1 V33 enabled
V33 output voltage configuration— Refer to Table 57.
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6.6.5.3.42
LDO3 control register (LDO3CTL)
This register is used to configure output voltage, Normal and Standby mode operation of the LDO3 regulator.
Table 172. LDO3 control register (LDO3CTL)
Access: user read/write (124)
Address: 0x70 functional page
R
W
7
6
5
4
LDO3OMODE
LDO3LPWR
LDO3STBY
LDO3EN
0
0
0
X (125)
Default
3
2
1
0
X (125)
X (125)
LDO3
X (125)
X (125)
= Unimplemented or reserved
Notes
124. Read: Anytime
Write: Anytime
125. Default value depends on OTP content.
Table 173. LDO3CTL field descriptions
Field
7
LDO3OMODE
Description
LDO3 OFF mode bit—LDO3OMODE is used to configure LDO3 operating mode when a EN turn-off event occurs.
0 LDO3 in OFF mode if a EN turn off event occurs
1 LDO3 in Sleep mode if a EN turn off event occurs
6
LDO3LPWR
LDO3 Low-power mode enable bit— When LDO3LPWR is set to 1, LDO3 can enter Low-power mode per the conditions in
Table 59.
0 Low-power mode disabled
1 Low-power mode enabled
5
LDO3STBY
LDO3 standby enable bit— When LDO3STBY is set to 1, LDO3 is turned off during Standby mode. Refer to Table 59.
0 LDO3 is ON during Standby mode.
1 LDO3 is OFF during Standby mode.
4
LDO3EN
3:0
LDO3
LDO3 enable bit — LDO3EN is used to enable or disable the LDO3 regulator.
0 LDO3 disabled
1 LDO3 enabled
LDO3 output voltage configuration— Refer to Table 56.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
6.6.5.3.43
LDO4 control register (LDO4CTL)
This register is used to configure output voltage, Normal and Standby mode operation of the LDO4 regulator.
Table 174. LDO4 control register (LDO4CTL)
Access: user read/write (126)
Address: 0x71 functional page
R
W
7
6
5
4
LDO4OMODE
LDO4LPWR
LDO4STBY
LDO4EN
0
0
0
X (127)
Default
3
2
1
0
X (127)
X (127)
LDO4
X (127)
X (127)
= Unimplemented or reserved
Notes
126. Read: Anytime
Write: Anytime
127. Default value depends on OTP content.
Table 175. LDO4CTL field descriptions
Field
7
LDO4OMODE
Description
LDO4 OFF mode bit—LDO4OMODE is used to configure LDO4 operating mode when a EN turn-off event occurs.
0 LDO4 in OFF mode if a EN turn off event occurs
1 LDO4 in Sleep mode if a EN turn off event occurs
6
LDO4LPWR
LDO4 Low-power mode enable bit— When LDO4LPWR is set to 1, LDO4 can enter Low-power mode per the conditions in
Table 59.
0 Low-power mode disabled
1 Low-power mode enabled
5
LDO4STBY
LDO4 standby enable bit— When LDO4STBY is set to 1, LDO4 is turned off during Standby mode. Refer to Table 59.
0 LDO4 is ON during Standby mode.
1 LDO4 is OFF during Standby mode.
4
LDO4EN
3:0
LDO4
6.6.5.3.44
LDO4 Enable bit — LDO4EN is used to enable or disable the LDO4 regulator.
0 LDO4 disabled
1 LDO4 enabled
LDO4 output voltage configuration— Refer to Table 56.
Page selection register
This register is used to access the extended register pages.
Table 176. Page Selection Register
Access: user read/write (128)
Address: 0x7F functional page
7
6
5
4
3
2
R
0
0
0
PAGE
W
Default
1
0
0
0
0
0
0
= Unimplemented or reserved
Notes
128. Read: Anytime
Write: Anytime
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 177. Page register field descriptions
Field
Description
3:0
PAGE
6.6.6
Register page selection — The PAGE field is used to select one of the three available register pages.
0000 Functional page selected
0001 Extended page 1 selected
0010 Extended page 2 selected
Register map
The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can
be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,
the functional registers are the same, but the extended registers are different. To access registers in Extended page 1, one must first write
0x01 to the page register at address 0x7F, and to access registers Extended page 2, one must first write 0x02 to the page register at
address 0x7F. To access the Functional page from one of the extended pages, no write to the page register is necessary.
Registers missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect. The contents
of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit
Bit #: The bit location in the register (7-0)
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Bits reset by SC and VDIG_PORB
Bits reset by EN or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB
Bits reset by VDIG_PORB
Bits reset by POR or OFFB
Default: The value after reset, as noted in the Default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read/Write bits initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are
subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits which may have other dependencies. For
example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the interrupts.
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FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
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6.6.6.1
Register map
Table 178. Functional page
BITS[7:0]
Add
Register
name
R/W
Default
00
DeviceID
R
8'b0011_0000
03
04
05
06
07
08
09
0A
0E
0F
10
11
12
13
1A
1B
SILICONREVID
FABID
INTSTAT0
INTMASK0
R
RW1C
R/W
R
INTSTAT1
RW1C
INTSENSE1
INTSTAT3
INTMASK3
R/W
R
RW1C
R/W
INTSENSE3
R
INTSTAT4
RW1C
INTMASK4
R/W
INTSENSE4
R
COINCTL
R/W
PWRCTL
6
5
4
–
–
–
–
0
0
1
1
3
2
R/W
1
0
DEVICE ID [3:0]
0
0
FULL_LAYER_REV[3:0]
R
INTSENSE0
INTMASK1
7
0
0
METAL_LAYER_REV[3:0]
8'b0001_0000
0
0
0
1
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
–
–
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
ENI
0
0
0
0
0
0
0
0
–
–
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
ENM
0
0
1
1
1
1
1
1
VDDOTPS
ICTESTS
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
ENS
0
0
x
x
x
x
x
x
–
–
–
SW3FAULTI
SW2FAULTI
–
SW1FAULTI
SW1FAULTI
FAB[1:0]
0
FIN[1:0]
8'b0000_0000
8'b0000_0000
8'b0011_1111
8'b00xx_xxxx
8'b0000_0000
0
0
0
0
0
x
0
0
–
–
–
SW3FAULTM
SW2FAULTM
–
SW1FAULTM
SW1FAULTM
0
1
1
1
1
1
1
1
–
–
–
SW3FAULTS
SW2FAULTS
–
SW1FAULTS
SW1FAULTS
0
x
x
x
x
x
x
x
OTP_ECCI
OTP AUTO
BLOW DONE
–
–
–
–
–
SWBSTFAULT
I
0
0
0
0
0
0
0
0
OTP_ECCM
OTP_AUTO_B
LOW_DONEM
–
–
–
–
–
SWBSTFAULT
M
1
1
0
0
0
1
0
1
OTP_ECCS
OTP_AUTO_B
LOW_DONES
–
–
–
–
–
SWBSTFAULT
S
0
0
0
0
0
0
0
0
–
–
LDO4FAULTI
LDO3FAULTI
V33FAULTI
VSDFAULTI
LDO2FAULTI
LDO1FAULTI
0
0
0
0
0
0
0
0
–
–
LDO4
FAULTM
LDO3
FAULTM
V33
FAULTM
VSDFAULTM
0
0
1
1
1
1
1
1
–
–
LDO4
FAULTS
LDO3
FAULTS
V33
FAULTS
VSD
FAULTS
LDO2
FAULTS
LDO1
FAULTS
0
0
x
x
x
x
x
x
–
–
–
–
COINCHEN
0
0
0
0
0
REGSCPEN
STBYINV
0
0
8'b0111_1111
8'b0xxx_xxxx
8'b0000_0000
8'b1100_0101
8'b0000_000x
8'b0000_0000
8'b0011_1111
8'b00xx_xxxx
LDO2FAULTM LDO1FAULTM
VCOIN[2:0]
8'b0000_0000
STBYDLY[1:0]
0
ENBDBNC[1:0]
0
0
ENRSTEN
RESTARTEN
0
0
8'b0001_0000
0
1
0
0
VR5100
92
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 178. Functional page (continued)
BITS[7:0]
Add
Register
name
R/W
Default
1C
MEMA
R/W
8'b0000_0000
7
1E
1F
20
21
22
23
24
32
35
36
37
38
39
3C
3D
3E
MEMB
MEMC
MEMD
SW1VOLT
SW1STBY
SW1OFF
R/W
R/W
R/W
R/W
SW2OFF
R/W
R/W
R/W
R/W
SW2MODE
R/W
SW2CONF
R/W
SW3VOLT
SW3STBY
SW3OFF
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
–
8'b0000_0000
0
0
0
0
0
0
0
0
8'b0000_0000
MEMD[7:0]
R/W
SW1CONF
SW2STBY
3
MEMC[7:0]
R/W
R/W
SW2VOLT
4
MEMB[7:0]
R/W
SW1MODE
SW1CONF
5
MEMA[7:0]
0
1D
6
R/W
R/W
R/W
8'b0000_0000
0
0
0
0
–
–
–
0
0
0
–
–
–
0
0
0
–
–
–
0
0
0
–
SW1[4:0]
8'b000x_xxxx
–
–
–
SW1STBY[4:0]
8'b000x_xxxx
–
–
–
SW1OFF[4:0]
8'b000x_xxxx
–
–
SW1OMODE
–
0
0
0
x
–
SW1DVSSPE
ED
x
-1
–
SW1DVSSPE
ED
–
–
–
–
SW1MODE[3:0]
8'b0000_xxxx
8'bxx00_0100
8'bx100_0100
SW1PHASE[1:0]
0
0
SW1PHASE[1:0]
SW1FREQ[1:0]
–
–
SW1FREQ[1:0]-
x
–
0
0
–
–
–
–
–
SW2_HI
–
0
x
x
x
–
–
–
–
–
SW2_HI
0
x
x
x
–
–
–
–
–
SW2_HI
0
x
x
x
–
–
–
SW2OMODE
–
0
0
1
0
–
SW2DVS
SPEED
x
–
0
1
–
–
–
–
–
–
–
SW1ILIM
0
0
–
SW1ILIM
0
0
SW2[2:0]
8'b0xxx_0110
–
–
–-
SW2STBY[2:0]
8'b0xxx_xxxx
–
–
–-
SW2STBY[2:0]
8'b0xxx_xxxx
–
–
–-
SW2MODE[3:0]
8'b0010_1000
8'bxx01_0100
1
SW2PHASE[1:0]
0
SW2FREQ[1:0]
–
–
0
0
–
SW2ILIM
0
0
–
–
–
–
–
–
SW3[3:0]
8'b0xxx_1100
0
x
x
x
–
–
–
–
0
x
x
x
–
–
–
–
0
x
x
x
–
–
SW3STBY[3:0]
8'b0xxx_1100
–
–
SW3OFF[3:0]
8'b0xxx_1100
–
–
VR5100
NXP Semiconductors
93
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 178. Functional page (continued)
BITS[7:0]
Add
Register
name
R/W
Default
3F
SW3MODE
R/W
8'b0011_1000
40
SW3CONF
R/W
7
6
5
4
–
–
SW3OMODE
–
0
0
1
1
–
SW3DVS
SPEED
x
–
8'bxx10_0100
–
66
69
6A
6B
6C
6D
6E
6F
70
71
7F
SWBSTCTL
LDOGCTL
REFOUTCTL
VSNVSCTL
LDO1CTL
LDO2CTL
VSDCTL
V33CTL
LDO3CTL
LDO4CTL
Page Register
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
3
SWBST1STBYMODE[1:0]
1
0
SW3MODE[3:0]
1
SW3PHASE[1:0]
1
2
0
SW3FREQ[1:0]
0
–
–
SWBST1MODE[1:0]
–
–
8'b0xx0_10xx
0
0
–
SW3ILIM
0
0
SWBST1VOLT[1:0]
0
–
–
0
–
–
–
–
–
–
–
–
–
–
–
STBY_LP_B
0
x
x
x
x
x
x
x
–
–
–
REFOUTEN
–
–
–
–
0
0
0
–
0
0
0
0
–
–
–
–
–
0
0
0
0
0
LDO1OMODE
LDO1LPWR
LDO1STBY
LDO1EN
0
0
0
–
LDO2OMODE
LDO2LPWR
LDO2STBY
LDO2EN
0
0
0
–
–
–
VSDOMODE
VSDLPWR
VSDSTBY
VSDEN
–
–
0
0
0
–
x
x
V33OMODE
V33LPWR
V33STBY
V33EN
–
–
0
0
0
–
x
x
LDO3OMODE
LDO3LPWR
LDO3STBY
LDO3EN
0
0
0
–
–
–
LDO4OMODE
LDO4LPWR
LDO4STBY
LDO4EN
0
0
0
–
–
–
–
0
0
0
8'b0xxx_xxx0
8'b000x_0000
VSNVSVOLT[2:0]
8'b0000_0110
1
1
0
–
–-
–
–-
LDO1[3:0]
8'b010x_1110
–
–
LDO2[3:0]
8'b000x_1000
VSD[1:0]
8'b000x_xx10
–
–
V33[1:0]
8'b000x_xx10
–
–
–
–
–
–
0
LDO3[3:0]
8'b010x_0000
LDO4[3:0]
8'b000x_xxxx
–
–
PAGE[4:0]
8'b0000_0000
0
0
0
0
3
2
1
0
Table 179. Extended page 1
Address
80
84
8A
Register
Name
OTP FUSE
READ EN
OTP LOAD
MASK
OTP ECC SE1
TYPE
R/W
R/W
R
Default
BITS[7:0]
7
6
5
4
–
–
–
–
–
–
–
OTP FUSE
READ EN
0
0
0
x
x
x
x
x
START
RL PWBRTN
FORCE
PWRCTL
RL PWRCTL
RL OTP
RL OTP ECC
RL OTP
FUSE
RL TRIM FUSE
0
0
0
0
0
0
0
0
–
–
–
ECC5_SE
ECC4_SE
ECC3_SE
ECC2_SE
ECC1_SE
x
x
x
0
0
0
0
0
8'b000x_xxx0
8'b0000_0000
8'bxxx0_0000
VR5100
94
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 179. Extended page 1 (continued)
Address
Register
Name
TYPE
Default
8B
RSVD
R
8'bxxx0_0000
8C
OTP ECC DE1
R
8'bxxx0_0000
8D
RSVD
R
8'bxxx0_0000
A0
OTP SW1
VOLT
R/W
8'b00xx_xxxx
BITS[7:0]
7
6
5
4
3
2
1
0
–
–
–
ECC5_DE
ECC4_DE
ECC3_DE
ECC2_DE
ECC1_DE
x
x
x
0
0
0
0
0
x
x
OTP_SW1_VOLT[4:0]
x
x
x
x
x
x
OTP_SW1_SEQ[2:0]
A1
OTP SW1 SEQ
A2
OTP SW1
CONFIG
R/W
RSVD
R/W
AA
AC
–
–
–
–
OTP_SW1_CONFIG[1:0]
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8'b00xx_xxxx
OTP_SW2_HI
OTP SW2
VOLT
R/W
OTP SW2 SEQ
R/W
OTP_SW2_VOLT[2:0]
8'b0xxx_xxxx
x
x
x
x
x
x
–
AD
AE
B0
OTP SW2
CONFIG
R/W
R/W
OTP SW3 SEQ
R/W
x
x
x
x
x
x
–
–
–
–
–
–
0
0
0
x
x
BC
BD
C0
C4
C8
C9
OTP SWBST
VOLT
R/W
OTP SWBST
SEQ
R/W
OTP VSNVS
VOLT
R/W
RSVD
R/W
OTP_SW2_FREQ[1:0]
0
x
x
OTP_SW3_VOLT[3:0]
x
x
x
x
x
x
x
OTP_SW3_SEQ[2:0]
8'b0xxx_xxxx
x
x
x
x
x
–
R/W
x
8'b0xxx_xxxx
x
OTP SW3
CONFIG
x
8'b0000_00xx
x
B2
x
OTP_SW2_SEQ[2:0]
–
B1
x
8'b0xxx_xxxx
–
OTP SW3
VOLT
OTP_SW1_FREQ[1:0]
8'b000x_xxXx
x
x
OTP_SW3_FREQ[1:0]
8'b0xxx_xxxx
x
x
x
x
x
x
–
–
–
–
–
–
0
0
0
0
0
0
–
–
–
–
–
x
x
OTP_SWBST_VOLT[1:0]
8'b0000_00xx
0
0
OTP_SWBST_SEQ[2:0]
8'b0000_xxxx
0
0
0
0
0
–
–
–
–
–
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
–
–
–
0
0
0
x
x
x
x
x
OTP_VSNVS_VOLT[2:0]
8'b0000_0xxx
8'b000x_x0xx
OTP_LDO1_VOLT[3:0]
OTP LDO1
VOLT
R/W
OTP LDO1
SEQ
R/W
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_LDO1_SEQ[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
VR5100
NXP Semiconductors
95
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 179. Extended page 1 (continued)
Address
Register
Name
TYPE
Default
CC
OTP LDO2
VOLT
R/W
8'b0000_xxxx
OTP LDO2
SEQ
R/W
OTP VSD
VOLT
R/W
OTP VSD SEQ
R/W
CD
D0
BITS[7:0]
7
6
5
4
3
0
0
0
0
x
2
1
0
OTP_LDO2_VOLT[3:0]
x
x
x
OTP_LDO2_SEQ[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
–
x
OTP_VSD_VOLT[2:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_VSD_SEQ[2:0]
D1
8'b0000_xxxx
0
D4
0
0
0
0
x
x
x
OTP_V33_VOLT[2:0]
OTP V33
VOLT
R/W
OTP V33 SEQ
R/W
8'b0000_xxxx
0
0
0
0
x
x
0
0
0
0
x
x
x
x
OTP_V33_SEQ[3:0]
D5
D8
D9
DC
DD
E0
E4
E5
E6
E7
E8
F0
F1
R/W
OTP LDO3
SEQ
R/W
OTP LDO4
VOLT
R/W
OTP LDO4
SEQ
R/W
OTP PU
CONFIG1
R/W
0
0
0
x
x
x
x
OTP_LDO3_SEQ[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_LDO4_VOLT[3:0]
8'b0000_xxxx
0
0
0
0
x
x
x
x
OTP_LDO4_SEQ[3:0]
8'b0000_xxxx
0
0
0
0
x
RSVD
R/W
R/W
R
OTP PWRGD
EN
R/W/M
RSVD
R/W
R/W
x
x
OTP_SWDVS
_CLK
OTP_EN_CFG
R/W
RSVD
x
8'b0000_xxxx
0
OTP FUSE
POR1
RSVD
x
OTP_LDO3_VOLT[3:0]
OTP LDO3
VOLT
RSVD
8'b0000_xxxx
8'b000x_xxxx
x
OTP_SEQ_CL
K_SPEED
x
x
x
x
x
x
x
x
TBB_POR
–
–
–
–
–
–
–
0
0
0
0
0
0
x
0
–
–
–
–
–
–
–
0
0
0
0
0
0
0
–
–
–
–
–
–
–
0
0
0
0
0
0
0
8'b0000_00x0
8'b0000_00x0
8'b0000_00x0
–
–
–
–
–
–
–
0
0
0
0
0
0
0
–
–
–
–
–
–
–
OTP_PG_EN
0
0
0
0
0
0
x
0
–
–
–
0
0
0
x
x
x
x
x
–
–
–
0
0
0
x
x
x
x
x
8'b0000_00x0
8'b0000_000x
8'b000x_xxxx
8'b000x_xxxx
VR5100
96
NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 179. Extended page 1 (continued)
Address
F7
FF
Register
Name
OTP BLOWN
OTP I2C
ADDR
TYPE
R/W
R/W
Default
BITS[7:0]
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
OTP_BLOWN
0
0
0
0
0
0
0
x
8'b0000_000x
8'b0000_1xxx
USE_DEFAUL
T_ADD
I2C_SLV
ADDR[3]
–
0
0
0
0
OTP_I2C_SLV ADDR[2:0]
1
x
2
x
x
1
0
Table 180. Extended page 2
Address
81
83
84
85
Register
Name
SW1 PWRSTG
SW1 PWRSTG
SW2 PWRSTG
SW3 PWRSTG
TYPE
R/W
R
R
R
Default
8'b1111_1111
8'b1111_1111
8'b1111_1111
8'b1111_1111
88
PWRCTRL
OTP CTRL
8D
I2C WRITE
ADDRESS
TRAP
R/W
8'b0000_0000
8E
I2C TRAP
PAGE
R/W
8'b0000_0000
R
8'b0000_0001
8F
I2C TRAP
CNTR
R/W
8'b0000_0000
90
IO DRV
R/W
8'b00xx_xxxx
D0
OTP AUTO
ECC0
R/W
8'b0000_0000
D8
Reserved
–
8'b0000_0000
D9
Reserved
–
8'b0000_0000
E1
E2
E3
E4
OTP ECC
CTRL1
R/W
OTP ECC
CTRL2
R/W
OTP ECC
CTRL3
R/W
OTP ECC
CTRL4
R/W
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
BITS[7:0]
7
6
5
4
3
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
SW1_PWRSTG[2:0]
1
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
SW1_PWRSTG[2:0]
RSVD
1
1
1
SW2_PWRSTG[2:0]
RSVD
1
1
1
SW3_PWRSTG[2:0]
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
1
1
1
1
1
1
1
1
–
–
–
–
–
–
OTP_PWRGD
_EN
PG_SHDWN_
EN
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
I2C_WRITE_ADDRESS_TRAP[7:0]
0
0
0
LET_IT_ ROLL
RSVD
RSVD
0
0
0
0
0
0
0
I2C_TRAP_PAGE[4:0]
I2C_WRITE_ADDRESS_COUNTER[7:0]
0
0
0
0
0
0
x
x
x
x
x
x
AUTO_ECC
_BANK5
AUTO_ECC
_BANK4
AUTO_ECC_B
ANK3
AUTO_ECC
_BANK2
AUTO_ECC_B
ANK1
0
0
0
0
0
0
0
0
SDA_DRV[1:0]
0
RSVD
–
–
–
0
0
0
INTB_DRV[1:0]
PORBMCU_DRV[1:0]
AUTO_BLOW_TIME[7:0]
0
0
0
START
RELOAD
EN_RW
0
0
0
RSVD
ECC1_CALC_
CIN
0
0
RSVD
ECC2_CALC_
CIN
0
0
RSVD
ECC3_CALC_
CIN
0
0
RSVD
ECC4_CALC_
CIN
0
0
0
0
AUTO_FUSE_ AUTO_FUSE_ AUTO_FUSE_ AUTO_FUSE_ AUTO_FUSE_
BLOW5
BLOW4
BLOW3
BLOW2
BLOW1
0
0
0
0
0
0
0
0
0
0
0
0
0
ECC1_CIN_TBB[5:0]
0
0
0
0
ECC2_CIN_TBB[5:0]
0
0
0
0
ECC3_CIN_TBB[5:0]
0
0
0
0
ECC4_CIN_TBB[5:0]
0
0
0
0
VR5100
NXP Semiconductors
97
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
CONTROL INTERFACE I2C BLOCK DESCRIPTION
Table 180. Extended page 2 (continued)
Address
E5
F1
F2
F3
F4
F5
Register
Name
OTP ECC
CTRL5
OTP FUSE
CTRL1
OTP FUSE
CTRL2
OTP FUSE
CTRL3
OTP FUSE
CTRL4
OTP FUSE
CTRL5
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
Default
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
8'b0000_0000
BITS[7:0]
7
6
RSVD
ECC5_CALC_
CIN
0
0
5
4
3
2
1
0
0
0
ECC5_CIN_TBB[5:0]
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
–
–
–
–
0
0
0
0
0
0
ANTIFUSE1_E ANTIFUSE1_L ANTIFUSE1_R
N
OAD
W
0
0
0
ANTIFUSE2_E ANTIFUSE2_L ANTIFUSE2_R
N
OAD
W
0
0
0
ANTIFUSE3_E ANTIFUSE3_L ANTIFUSE3_R
N
OAD
W
0
0
0
ANTIFUSE4_E ANTIFUSE4_L ANTIFUSE4_R
N
OAD
W
0
0
0
ANTIFUSE5_E ANTIFUSE5_L ANTIFUSE5_R
N
OAD
W
0
0
0
BYPASS1
0
BYPASS2
0
BYPASS3
0
BYPASS4
0
BYPASS5
0
VR5100
98
NXP Semiconductors
TYPICAL APPLICATIONS
APPLICATION DIAGRAM
7
Typical applications
7.1
Application diagram
Figure 37. Typical application schematic
VR5100
NXP Semiconductors
99
BILL OF MATERIALS
APPLICATION DIAGRAM
8
Bill of materials
The following table provides a complete list of the recommended components on a full featured system using the VR5100 device for
-40 °C to 85 °C applications. Components are provided with an example part number; equivalent components may be used.
Table 181. Bill of material for -40 °C to 85 °C applications
Value
Qty
Description
Part#
Manufacturer
Component/Pin
PMIC
N/A
1
Power management IC
VR5100
NXP
IC
IND PWR 1.5 uH at 1.0 MHz 7.1 A
XAL4020-152ME
20% 2016
Coilcraft
SW1 inductor
IND PWR 1.5 uH at 1.0 MHz 2.6 A
LPS4012-152MR
20% 2016
Coilcraft
SW2 and SW3 inductors
Buck regulators
1.5 μH
4
4.7 μF
4
CAP CER 4.7 μF 10 V 20% X5R
0402
GRM155R61A475MEAA
Murata
SW1, SW2, SW3 input capacitors
0.1 μF
4
CAP CER 0.1 μF 10 V 20% X5R
0201
GRM033R61A104ME84
Murata
SW1, SW2, SW3 input capacitors
(optional)
22 μF
8
CAP CER 22 μF 10 V 20% X5R
0603
GRM188R61A226ME15
Murata
SW1, SW2, SW3 output
capacitors
IND PWR 2.2 μH at 1.0 MHz 2.4 A
DFE201610E-2R2M
20% 2016
TOKO INC.
SWBST inductor
IND PWR 2.2 μH at 1.0 MHz 1.85 A
BRL3225T2R2M
20% 1210
Taiyo Yuden
Alternate for low power
applications
Boost regulator
2.2 μH
1
10 μF
1
CAP CER 10 μF 10 V 20% X5R
0402
GRM155R61A106ME11
Murata
SWBST input capacitor
N/A
1
DIODE SCH PWR RECT 1.0 A
20 V SMT
MBR120LSFT3G
ON Semi
SWBST diode
22 μF
2
CAP CER 22 μF 10 V 20% X5R
0603
GRM188R61A226ME15D
Murata
SWBST output capacitors
Linear regulators
1.0 μF
3
CAP CER 1.0 μF 10 V 20% X5R
0201
GRM033R61A105ME44
Murata
LDO1, LDO2, LDO3 and LDO4
input capacitors
2.2 μF
3
CAP CER 2.2 μF 10 V 20% X5R
0201
GRM033R61A225ME47
Murata
LDO1, LDO3, VSD output
capacitors
10 μF
1
CAP CER 10 μF 10 V 20% X5R
0402
GRM155R61A106ME11
Murata
V33 and VSD input capacitor
4.7 μF
3
CAP CER 4.7 μF 10 V 20% X5R
0402
GRM155R61A475MEAA
Murata
LDO2, LDO4, V33 output
capacitors
1.0 μF
4
CAP CER 1.0 μF 10 V 20% X5R
0201
GRM033R61A105ME44
Murata
VCC, VBG, REFOUT,
VINREFOUT capacitors
0.22 μF
2
CAP CER 0.22 μF 10 V 20% X5R
0201
GRM033R61A224ME90
Murata
VDIG and coin cell output
capacitors
0.47 μF
1
CAP CER 0.47 μF 10 V 20% X5R
0201
GRM033R61A474ME90
Murata
VSNVS output capacitor
2.2 μF
1
CAP CER 2.2 μF 10 V 20% X5R
0201
GRM033R61A225ME47
Murata
VIN input capacitor when not
using Front-end LDO
Miscellaneous
VR5100
100
NXP Semiconductors
BILL OF MATERIALS
APPLICATION DIAGRAM
Table 181. Bill of material for -40 °C to 85 °C applications (continued)
Value
Qty
Description
Part#
Manufacturer
Component/Pin
0.1 μF
5
CAP CER 0.1 μF 10 V 10% X5R
0201
GRM033R61A104KE84
Murata
VCCI2C, VIN input capacitors
100 k
2
RES MF 100 k 1/16 W 1% 0402
RC0402FR-07100KL
YAGEO
AMERICA
Pull-up resistors
4.7 k
2
RES MF 4.70 k 1/20 W 1% 0201
RC0201FR-074K7L
YAGEO
AMERICA
I²C Pull-up resistors
The following table provides a complete list of the recommended components on a full featured system using the VR5100 Device for
-40 °C to 105 °C applications. Components are provided with an example part number, equivalent components may be used.
Table 182. Bill of material for -40 °C to 105 °C applications
Value
Qty
Description
Part#
Manufacturer
Component/Pin
PMIC
N/A
1
Power management IC
VR5100
NXP
IC
IND PWR 1.5 μH at 1.0 MHz 2.9 A
DFE201610E-1R5M
20% 2016
TOKO INC.
SW1, SW2, SW3 inductors
IND PWR 1.5 μH at 1.0 MHz 2.2 A
BRL3225T1R5M
20% 1210
Taiyo Yuden
Alternate for low-power
applications
Buck regulators
1.5 μH
4
4.7 μF
4
CAP CER 4.7 μF 10 V 10% X7S
0603
GRM188C71A475KE11
Murata
SW1, SW2, SW3 input capacitors
0.1 μF
4
CAP CER 0.1 μF 10 V 10% X7S
0201
GRM033C71A104KE14
Murata
SW1, SW2, SW3 input capacitors
(optional)
22 μF
8
CAP CER 22 μF 10 V 20% X7T
0805
GRM21BD71A226ME44
Murata
SW1, SW2, SW3 output
capacitors
IND PWR 2.2 μH at 1.0 MHz 2.4 A
DFE201610E-2R2M
20% 2016
TOKO INC.
SWBST inductor
IND PWR 2.2 μH at 1.0 MHz 1.85 A
BRL3225T2R2M
20% 1210
Taiyo Yuden
Alternate for low-power
applications
Boost regulator
2.2 μH
1
10 μF
1
CAP CER 10 μF 10 V 20% X7T
0603
GRM188D71A106MA73
Murata
SWBST input capacitor
N/A
1
DIODE SCH PWR RECT 1.0 A
20 V SMT
MBR120LSFT3G
ON Semi
SWBST diode
22 μF
2
CAP CER 22 μF 10 V 20% X5R
0603
GRM188R61A226ME15D
Murata
SWBST output capacitors
Linear regulators
1.0 μF
3
CAP CER 1.0 μF 10 V 10% X7S
0402
GRM155C71A105KE11
Murata
LDO1, LDO2, LDO3 and LDO4
input capacitors
2.2 μF
3
CAP CER 2.2 μF 10 V 10% X7S
0402
GRM155C71A225KE11
Murata
LDO1, LDO3, VSD output
capacitors
10 μF
1
CAP CER 10 μF 10 V 20% X7T
0603
GRM188D71A106MA73
Murata
V33 and VSD input capacitor
4.7 μF
3
CAP CER 4.7 μF 10 V 10% X7S
0603
GRM188C71A475KE11
Murata
LDO2, LDO4, V33 output
capacitors
1.0 μF
4
CAP CER 1.0 μF 10 V 10% X7R
0402
GRM155C71A105KE11
Murata
VCC, VDIG, REFOUT,
VINREFOUT capacitors
0.22 μF
2
CAP CER 0.22 μF 10 V 10% X7R
0402
GRM155R71A224KE01
Murata
VBG and coin cell output
capacitors
Miscellaneous
VR5100
NXP Semiconductors
101
BILL OF MATERIALS
APPLICATION DIAGRAM
Table 182. Bill of material for -40 °C to 105 °C applications (continued)
Value
Qty
Description
Part#
Manufacturer
Component/Pin
0.47 μF
1
CAP CER 0.47 μF 10 V 20% X5R
0201
GRM155R71A474KE01
Murata
VSNVS output capacitor
2.2 μF
1
CAP CER 2.2 μF 10 V 10% X7S
0402
GRM155C71A225KE11
Murata
VIN input capacitor
0.1 μF
5
CAP CER 0.1 μF 10 V 10% X7S
0201
GRM033C71A104KE14
Murata
VCCI2C, VHALF, VIN input
capacitors
100 k
2
RES MF 100 k 1/16 W 1% 0402
RC0402FR-07100KL
YAGEO
AMERICA
Pull-up resistors
4.7 k
2
RES MF 4.70 K 1/20 W 1% 0201
RC0201FR-074K7L
YAGEO
AMERICA
I²C pull-up resistors
VR5100
102
NXP Semiconductors
THERMAL INFORMATION
RATING DATA
9
Thermal information
9.1
Rating data
The thermal rating data of the packages has been simulated with the results listed in Thermal ratings. Junction to Ambient Thermal
Resistance Nomenclature: the JEDEC specification reserves the symbol RJA or JA (Theta-JA) strictly for junction-to-ambient thermal
resistance on a 1s test board in natural convection environment. RJMA or JMA (Theta-JMA) is used for both junction-to-ambient on a
2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated
the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.
9.2
Estimation of junction temperature
An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RJA x PD)
with:
TA = Ambient temperature for the package in °C
RJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction to ambient thermal resistance is an industry standard value providing a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board RJA and the value obtained on a four
layer board RJMA. Actual application PCBs show a performance close to the simulated four layer board value, although this may be
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
TJ = TB + (RJB x PD) with
TB = Board temperature at the package perimeter in °C
RJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
VR5100
NXP Semiconductors
103
PACKAGING
PACKAGING DIMENSIONS
10
Packaging
10.1
Packaging dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and perform
a keyword search for the drawing's document number. See the Thermal characteristics section for specific thermal characteristics for each
package.
Table 183. Package drawing information
Package
Suffix
48-pin QFN 7X7 mm - 0.5 mm pitch
EP
Package outline drawing number
98ASA00719D
VR5100
104
NXP Semiconductors
PACKAGING
PACKAGING DIMENSIONS
VR5100
NXP Semiconductors
105
PACKAGING
PACKAGING DIMENSIONS
VR5100
106
NXP Semiconductors
REVISION HISTORY
PACKAGING DIMENSIONS
11
Revision history
Revision
Date
1.0
12/2015
• Initial release
2.0
2/2016
• Relabeled REFDDR as REFOUT
• Updated form and style
3.0
2/2016
• VLDOIN34 max. voltage updated to 3.6 V
4.0
2/2017
5.0
12/2018
Description of changes
•
•
•
•
•
•
•
•
•
•
Replaced Figure 1
Removed PC34VR5100A2EP from Table 1
Corrected Figure 4
Removed A2 column from Table 37
Updated Figure 25
Corrected title for Figure 26
Changed PC parts to MC in Table 1
Updated Table 73 (changed default values to 1 for bits [5:0])
Added MC34VR5100A2EP to Table 1
Added A2 and its values in Table 37
VR5100
NXP Semiconductors
107
Ho w to Re ac h Us :
Information in this document is provided solely to enable system and software implementers to use NXP products.
Ho me Pag e :
NXP.com
There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits
We b S uppo rt:
http://www.nxp.com/support
products herein.
based on the information in this document. NXP reserves the right to make changes without further notice to any
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular
purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical"
parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications,
and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each
customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor
the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the
following address:
http://www.nxp.com/terms-of-use.html.
NXP, the NXP logo, Freescale, the Freescale logo, and SMARTMOS are trademarks of NXP Semiconductors N.V.
All other product or service names are the property of their respective owners. All rights reserved.
© NXP Semiconductors N.V. 2017
Docume nt Numbe r: VR5100
Re v. 5.0
12/2018
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