PCA2002

PCA2002 32 kHz watch circuit with programmable output period and pulse width Rev. 05 — 11 November 2008 Product data sheet 1. General description The PCA2002 is a CMOS integrated circuit for battery operated wrist watches with a 32 kHz quartz crystal as the timing element and a bipolar stepping motor. The quartz crystal oscillator and the frequency divider are optimized for minimum current consumption. A timing accuracy of 1 ppm is achieved with a programmable, digital frequency adjustment. The output period and the output pulse width can be programmed. It can be selected between a full output pulse or a chopped output pulse with a duty cycle of 75 %. In addition, a stretching pulse can be added to the primary driving pulse. A pad RESET is provided (used for stopping the motor) for accurate time setting and for accelerated testing of the watch. 2. Features I Amplitude-regulated 32 kHz quartz crystal oscillator, with excellent frequency stability and high immunity to leakage currents I Electrically programmable time calibration with 1 ppm resolution stored in One Time Programmable (OTP) memory I The quartz crystal is the only external component required I Very low current consumption: typically 90 nA I Output pulses for bipolar stepping motors I Five different programmable output periods (1 s to 30 s) I Output pulse width programmable between 1 ms and 8 ms I Full or chopped motor pulse and pulse stretching, selectable I Stop function for accurate time setting and current saving during shelf life I Test mode for accelerated testing of the mechanical parts of the watch I Test bits for type recognition 3. Applications I Driver circuits for bipolar stepping motors I High immunity motor drive circuits I High production volumes NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 4. Ordering information Table 1. Ordering information Package Name PCA2002U/AB/1 PCA200xU Description wire bond die; 8 bonding pads; 1.16 × 0.86 × 0.22 mm wire bond die; 8 bonding pads; 1.16 × 0.86 × 0.22 mm Delivery form bare die; chip in tray bare die; chip on film frame carrier Version PCA200xU PCA200xU PCA200xCX Type number PCA2002U/10AB/1 PCA200xU PCA2002CX8/5/1 PCA200xCX wafer level chip-size package; unsawn wafer with lead free solder 8 bumps; 1.16 × 0.86 × 0.31 mm bumps 5. Block diagram OSCIN OSCILLATOR OSCOUT 32 Hz 8 kHz ÷4 DIVIDER RESET RESET TIMING ADJUSTMENT, INHIBITION reset VDD VSS VOLTAGE DETECTOR, OTP-CONTROLLER OTP-MEMORY 1 Hz MOTOR CONTROL PCA2002 i.c. mbl568 MOT1 n.c. n.c. M MOT2 Fig 1. Block diagram PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 2 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 6. Pinning information 6.1 Pinning PCA200xU VSS i.c. 1 2 x 0 OSCIN OSCOUT 3 4 0 y 6 5 001aai177 PCA200xCX 8 7 RESET MOT2 VSS i.c. 1 2 x 0 MOT1 VDD OSCIN OSCOUT 3 4 0 y 6 5 001aai176 8 7 RESET MOT2 MOT1 VDD Top view. For mechanical details, see Figure 10. Top view. For mechanical details, see Figure 11 Fig 2. Pad and bump configuration of PCA2002 6.2 Pin description Table 2. Symbol VSS i.c. OSCIN OSCOUT VDD MOT1 MOT2 RESET Pin description for PCA2002 Pin 1 2 3 4 5 6 7 8 Description ground internally connected oscillator input oscillator output supply voltage motor 1 output motor 2 output reset input PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 3 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 7. Functional description 7.1 Motor pulse The motor driver delivers pulses with an alternating polarity. The output waveform across the motor terminals is illustrated in Figure 3. Between the motor pulses, both terminals are connected to VDD which means that the motor is short-circuit. The following parameters can be selected and are stored in a One Time Programmable (OTP) memory: • • • • Output periods of 1 s, 5 s, 10 s, 20 s and 30 s Pulse width (tp) between 0.98 ms and 7.8 ms in steps of 0.98 ms Full or chopped (75 %) output pulse Pulse stretching: an enlargement pulse is added to the primary motor pulse. This enlargement pulse has a duty cycle of 25 % and a width which is twice the programmed motor pulse width. period full pulse chopped pulse full pulse with stretching chopped pulse with stretching tp 2t p tp 2t p mgu718 Fig 3. Motor output waveforms 7.2 Time calibration The quartz crystal oscillator has an integrated capacitance of 5.2 pF, which is lower than the specified capacitance (CL) of 8.2 pF for the quartz crystal (see Table 9). Therefore, the oscillator frequency is typically 60 ppm higher than 32.768 kHz. This positive frequency offset is compensated by removing the appropriate number of 8192 Hz pulses in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is given in Table 3. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 4 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width Time calibration Correction per step (n = 1) ppm 2.03 1.017 0.176 0.088 Correction per step (n = 127) seconds per day 22.3 11.15 258 129 seconds per day ppm Table 3. Calibration period 1 minute 2 minutes After measuring the effective oscillator frequency, the number of correction pulses must be calculated and stored together with the calibration period in the OTP memory (see Section 7.6). The oscillator frequency can be measured at pad RESET, where a square wave signal 1 with the frequency of ----------- × f osc is provided. 1024 This frequency shows a jitter every minute or every two minutes, depending on the programmed calibration period, which originates from the time calibration. Details on how to measure the oscillator frequency and the programmed inhibition time are given in Section 7.10. 7.3 Reset 1 At pin RESET an output signal with a frequency of ----------- × f osc = 32Hz is provided. 1024 Connecting pin RESET to VDD stops the motor drive and opens the motor switches. After releasing pin RESET, the first motor pulse is generated exactly one period later with the opposite polarity to the last pulse before stopping. The debounce time for the reset function is between 31 ms and 62 ms. Connecting pin RESET to VSS activates the test mode. In this mode the motor output frequency is 32 Hz, which can be used to test the mechanical function of the watch. 7.4 Programming possibilities The programming data is organized in an array of 8-bit words (see Table 4). A contains the time calibration, B the setting for the monitor pulses, C is not used and D contains the type recognition (see Table 7). Table 4. Word A B C D type factory test bit Words and bits Bit 1 2 3 4 5 6 7 8 calibration period duty cycle pulse stretching number of 8192 Hz pulses to be removed pulse width output period PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 5 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width Description of word A bits Value Description adjust the number of the 8192 Hz pulses to be removed; bit 1 is the MSB and bit 7 is the LSB 1 minute 2 minutes Table 5. Bit Inhibit time 1 to 7 Calibration period 8 0 1 Table 6. Bit 1 to 3 Description of word B bits Value 000 001 010 011 100 101 110 111 Output period (s) 4 to 6 000 001 010 011 100 Duty cycle of motor pulse 7 Pulse stretching 8 0 1 no pulse stretching a pulse width of 2 × tp and a duty factor of 25 % are added 0 1 75 % 100 % 1 5 10 20 30 Description 0.98 1.95 2.9 3.9 4.9 5.9 6.8 7.8 Pulse width tp (ms) 7.5 Type recognition Byte D is read to determine which type of the PCA200x family is used in a particular application. Table 7. Bit Type recognition 1 to 4 0000 1000 0100 1100 PCA2002_5 Description of word D bits Value Description PCA2002 PCA2000 PCA2001 PCA2003 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 6 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 7.6 Programming procedure To ensure that the oscillator starts up correctly you must execute a reset sequence (see Figure 4). VDD tp(stop) VP(prog)(stop) td(start) > 500 ms VDD(nom) VSS 001aac503 td(start): start delay time. VDD(nom): nominal supply voltage. Fig 4. Supply voltage at start-up during production and testing For a watch it is essential that the timing calibration can be made after the watch is fully assembled. In this situation, the supply pins are often the only terminals which are still accessible. Writing to the OTP cells and performing the related functional checks is achieved in the PCA2002 by modulating the supply voltage. The necessary control circuit consists basically of a voltage level detector, an instruction counter which determines the function to be performed, and an 8-bit shift register which allows writing the OTP cells of an 8-bit word in one step and which acts as data pointer for checking the OTP content. • • • • • • State 1; measurement of the crystal oscillator frequency (divided by 1024) State 2; measurement of the inhibition time State 3; write/check word A State 4; write/check word B State 5; check word C (don’t care since no meaning) State 6; check word D (type recognition) Each instruction state is switched on with a pulse to VP(prog)(start). After this large pulse, an initial waiting time of t0 is required. The programming instructions are then entered by modulating the supply voltage with small pulses (amplitude VP(mod) and pulse width tmod). The first small pulse defines the start time, the following pulses perform three different functions, depending on the time delay (td) from the preceding pulse (see Figure 5, Figure 6, Figure 7, Figure 8 and Figure 9): • td = t1 (0.7 ms); increments the instruction counter • td = t2 (1.7 ms); clocks the shift register with data = logic 0 • td = t3 (2.7 ms); clocks the shift register with data = logic 1 The programming procedure requires a stable oscillator, which means that a waiting time, determined by the start-up time of the oscillator, is necessary after power-up of the circuit. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 7 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width After the VP(prog)(start) pulse, the instruction counter is in state 1 and the data shift register is cleared. The instruction state ends with a second pulse to VP(prog)(stop) or with the pulse to Vstore. In any case, the instruction states are terminated automatically 2 seconds after the last supply modulation pulse. 7.7 Programming the memory cells Applying the two-stage programming pulse (see Figure 5) transfers the stored data in the shift register to the OTP cells. Perform the following to program a memory word: 1. Starting with a VP(prog)(start) pulse, wait for the time period t0 then set the instruction counter to the word to be written (td = t1). 2. Enter the data to be stored into the shift register (td = t2 or t3), LSB first (bit 8) and MSB last (bit 1). 3. Applying the two-stage programming pulse Vprestore followed by Vstore stores the word. The delay between the last data bit and the pre-store pulse Vprestore is td = t4. Store the word by raising the supply voltage to Vstore; the delay between the last data bit and the store pulse is td. The example shown in Figure 5 performs the following functions: • • • • Start Setting the instruction counter to state 4 (word B) Entering data word 110101 into the shift register (sequence: LSB first and MSB last) Writing the OTP cells for word B tw(prestore) VDD Vstore tp(start) VP(prog)(start) Vprestore t0 VP(mod) VDD(nom) VSS t1 t1 t1 t3 t2 t3 t2 t3 t3 t4 tw(store) mgw356 The example shows the programming of B = 110101 (the sequence is MSB first and LSB last). VDD(nom): nominal supply voltage. Fig 5. Supply voltage modulation for programming PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 8 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 7.8 Checking the memory content The stored data of the OTP array can be checked bit wise by measuring the supply current (see Figure 6). The array word is selected by the instruction state and the bit is addressed by the shift register. To read a word, the word is first selected (td = t1) and a logic 1 is written into the first cell of the shift register (td = t3). This logic 1 is then shifted through the entire shift register (td = t2), so that it points with each clock pulse to the next bit. If the addressed OTP cell contains a logic 1, a 30 kΩ resistor is connected between VDD and VSS; this increases the supply current accordingly. Figure 6 shows the supply voltage modulation for reading word B, with the corresponding supply current variation for word B = 110101 (sequence: first MSB and last LSB). VDD tp(start) VP(prog)(start) t0 VP(mod) VDD(nom) VSS t1 t1 t1 t3 t2 t2 t2 VP(prog)(stop) t2 t2 tp(stop) IDD (1) mgw357 VDD(nom): nominal supply voltage. (1) V DD ∆ I DD = --------------30 k Ω Supply voltage modulation for reading word B Fig 6. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 9 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 7.9 Frequency tuning at assembled watch Figure 7 shows the test set-up for frequency tuning the assembled watch. 32 kHz M FREQUENCY COUNTER PCA200x motor PROGRAMMABLE DC POWER SUPPLY PC INTERFACE battery PC mgw568 Fig 7. Frequency tuning the assembled watch 7.10 Measurement of the oscillator frequency and the inhibition time The output of the two measuring states can either be monitored directly at pin RESET or as a modulation of the supply current (a modulating resistor of 30 kΩ is connected between VDD and VSS when the signal at pin RESET is at HIGH-level). The supply voltage modulation must be followed as shown in Figure 4 in order to guarantee the correct start-up of the circuit during production and testing. Measuring states: • State 1; quartz crystal oscillator frequency divided by 1024; state 1 starts with a pulse to VP and ends with a second pulse to VP • State 2; inhibition time has a value of n × 0.122 ms. A signal with the periodicity of 31.25 ms + n × 0.122 ms appears at pin RESET and as current modulation at pin VDD (see Figure 8 and Figure 9) 31.25 ms + inhibition time VDD VO(dif) VSS mgw355 Fig 8. Output waveform at pin RESET for instruction state 2 PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 10 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width VDD t p(start) VP(prog)(stop) t0 t1 t p(stop) VP(prog)(start) VP(mod) VDD(nom) VSS mgu719 VDD(nom): nominal supply voltage. Fig 9. Supply voltage modulation for start and stop of instruction state 2 PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 11 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 8. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI tsc Tamb Tstg Vesd Ilu [1] [2] [3] [4] [5] Parameter supply voltage input voltage short circuit duration time ambient temperature storage temperature electrostatic discharge voltage latch-up current Conditions VSS = 0 V output [1][2] Min −1.8 −0.5 −10 −30 Max +7.0 +7.5 indefinite +60 +100 ±2000 ±200 100 Unit V V s °C °C V V mA HBM MM [3] [4] [5] - When writing to the OTP cells, the supply voltage (VDD) can be raised to a maximum of 12 V for a time period of 1 s. Connecting the battery with reversed polarity does not destroy the circuit, but in this condition a large current flows which rapidly discharges the battery. Pass level; Human Body Model (HBM) according to JESD22-A114. Pass level; Machine Model (MM), according to JESD22-A115. Pass level; Latch-up testing, according to JESD78. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 12 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 9. Characteristics Table 9. Characteristics VDD = 1.55 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 25 °C; quartz crystal: Rs = 40 kΩ, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless otherwise specified. Symbol Supplies VDD ∆VDD IDD supply voltage supply voltage variation supply current normal operating mode; Tamb = −10 °C to +60 °C ∆V/∆t = 1 V/µs between motor pulses between motor pulses at VDD = 3.5 V Tamb = −10 °C to +60 °C stop mode; pin RESET connected to VDD Motor output Vsat Zo(sc) Oscillator Vstart gm tstartup ∆f/f CL(itg) Rpar Pad RESET fo VO(dif) tr tf Ii(AV) output frequency differential output voltage rise time fall time average input current RL = 1 MΩ; CL = 10 pF RL = 1 MΩ; CL = 10 pF RL = 1 MΩ; CL = 10 pF pin RESET connected to VDD or VSS [1] [1] [1] Parameter Conditions Min 1.1 - Typ 1.55 90 120 100 Max 3.6 0.25 120 180 200 135 Unit V V nA nA nA nA saturation voltage output impedance (short circuit) start voltage transconductance start-up time frequency stability integrated load capacitance parasitic resistance Rmotor = 2 kΩ; Tamb = −10 °C to +60 °C between motor pulses; Imotor < 1 mA - 150 200 200 300 mV Ω 1.1 Vi(osc) ≤ 50 mV(p-p) ∆VDD = 100 mV 5 4.3 allowed resistance between adjacent pins 20 10 0.3 0.05 5.2 - 0.9 0.2 6.3 - V µS s ppm pF MΩ 1.4 - 32 1 1 10 20 Hz V µs µs nA [1] RL and CL are a load resistor and load capacitor, externally connected to pad RESET. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 13 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 10. OTP programming characteristics Table 10. Symbol VDD VP(prog)(start) VP(prog)(stop) VP(mod) Vprestore Vstore Istore tp(start) tp(stop) tmod tw(prestore) tw(store) t0 t1 t2 t3 t4 SR Rmod Specifications for OTP programming Parameter[1] supply voltage programming supply voltage (start) programming supply voltage (stop) supply voltage modulation prestore voltage supply voltage store current start pulse width pulse width of stop pulse modulation pulse width prestore pulse width store pulse width time 0 time 1 time 2 time 3 time 4 slew rate modulation resistance for writing to the OTP cells waiting time after start pulse pulse distance for incrementing the state counter pulse distance for clocking the data register with data = logic 0 pulse distance for clocking the data register with data = logic 1 waiting time for writing to OTP cells for modulation of the supply voltage supply current modulation read-out resistor for entering instructions for prestore pulse for writing to the OTP cells for writing to the OTP cells Conditions during programming procedure Min 1.5 6.6 6.2 320 6.2 9.9 8 0.05 25 0.05 95 20 0.6 1.6 2.6 0.1 0.5 18 Typ 350 10.0 10 30 100 0.7 1.7 2.7 0.2 30 Max 3.0 6.8 6.4 380 6.4 10.1 10 12 0.5 40 0.5 110 30 0.8 1.8 2.8 0.3 5.0 45 Unit V V V mV V V mA ms ms µs ms ms ms ms ms ms ms V/µs kΩ [1] Program each word once only. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 14 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 11. Bare die outline Wire bond die; 8 bonding pads; 1.16 x 0.86 x 0.22 mm D A P1 P2 e1 e2 E PCA200xU P4 P3 detail X X eD DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A 0.22 0.20 0.18 D 1.16 E 0.86 e1 0.17 e2 0.32 eD 0.96 P1 P2 P3 P4 0 0.5 scale EUROPEAN PROJECTION ISSUE DATE 08-05-09 08-05-21 1 mm 0.099 0.089 0.099 0.089 0.096 0.086 0.096 0.086 0.093 0.083 0.093 0.083 OUTLINE VERSION PCA200xU REFERENCES IEC JEDEC JEITA Fig 10. Bare die outline PCA200xU PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 15 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width WLCSP8: wafer level chip-size package; 8 bumps; 1.16 x 0.86 x 0.31 mm D b PCA200xCX e1 e2 E A A2 A1 detail X eD DIMENSIONS (mm are the original dimensions) UNIT mm max nom min A A1 A2 0.22 0.20 0.18 b 0.12 0.10 0.08 D 1.16 E 0.86 e1 0.17 e2 0.32 eD 0.96 0 0.5 scale REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 08-05-09 08-05-21 1 mm X 0.310 0.090 0.275 0.075 0.240 0.060 OUTLINE VERSION PCA200xCX Fig 11. Bare die outline PCA200xCX (WLCSP8) Table 11. Symbol VSS [2] Bonding pad and solder bump locations Pad 1 2 3 4 5 6 7 8 Coordinates[1] x −480 −480 −480 −480 +480 +480 +480 +480 y +330 +160 −160 −330 −330 −160 +160 +330 i.c.[3] OSCIN OSCOUT VDD MOT1 MOT2 RESET [1] [2] [3] All coordinates are referenced, in µm, to the center of the die (see Figure 10 and Figure 11). The substrate (rear side of the chip) is connected to VSS. Therefore, the die pad must be either floating or connected to VSS. Pad i.c. is used for factory test; in normal operation it must be left open-circuit, and it has an internal pull-down resistor connected to VSS. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 16 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 12. Packing information 12.1 Tray information A G H 1,1 1,2 1,3 2,1 3,1 2,2 x,1 x C y D B F 1,y x,y A E M A J SECTION A-A mgu653 Fig 12. Tray details Table 12. A B C D E F G H J M x y Tray dimensions Description pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction tray width; x direction tray width; y direction distance from cut corner to pocket (1 and 1) center distance from cut corner to pocket (1 and 1) center tray thickness pocket depth number of pockets in x direction number of pockets in y direction Value 2.15 mm 2.43 mm 1.01 mm 1.39 mm 50.67 mm 50.67 mm 4.86 mm 4.66 mm 3.94 mm 0.61 mm 20 18 Dimension PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 17 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width The orientation of the IC in a pocket is indicated by the position of the IC type name on the surface of the die, with respect to the cut corner on the upper left of the tray. PCA2002 mbl573 Fig 13. Tray alignment PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 18 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 12.2 Unsawn wafer information ~18 µm(1) ~18 µm(1) 84 µm Saw lane 84 µm Saw lane ~18 µm(1) 84 µm detail Y detail X (1) 1 8 1 8 4 5 4 5 1 Y 8 X 1 8 4 5 4 5 1 8 1 8 4 5 4 5 1 8 1 8 4 5 4 5 1 8 1 8 4 5 4 5 1 8 1 8 4 5 4 5 Straight edge of the wafer 001aai236 The die are grouped in arrays of 2 × 6 devices. Each array is edged with a metal path. All this metal paths have to be cut while dicing. Fig 14. Wafer layout of PCA200CX8 PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 19 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 13. Soldering of WLCSP packages 13.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface mount reflow soldering description”. Wave soldering is not suitable for this package. All NXP WLCSP packages are lead-free. 13.2 Board mounting Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself 13.3 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a PbSn process, thus reducing the process window • Solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 13 Table 13. Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 20 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 15. Temperature profiles for large and small components For further information on temperature profiles, refer to application note AN10365 “Surface mount reflow soldering description”. 13.3.1 Stand off The stand off between the substrate and the chip is determined by: • The amount of printed solder on the substrate • The size of the solder land on the substrate • The bump height on the chip The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip. 13.3.2 Quality of solder joint A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids. 13.3.3 Rework In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again. PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 21 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note AN10365 “Surface mount reflow soldering description”. 13.3.4 Cleaning Cleaning can be done after reflow soldering. 14. Abbreviations Table 14. Acronym HBM LSB MM MSB OTP Abbreviations Description Human Body Model Least Significant Bit Machine Model Most Significant Bit One Time Programmable PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 22 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 15. Revision history Table 15. Revision history Release date 20081111 Data sheet status Product data sheet Change notice Supersedes PCA2002_4 Document ID PCA2002_5 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Implemented new drawings and wafer information Added new bare die outline drawing Product data sheet Product specification Objective specification Objective specification PCA2002_3 PCA2002_2 PCA2002_1 - PCA2002_4 PCA2002_3 PCA2002_2 PCA2002_1 20050907 20040120 20030204 20021025 PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 23 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA2002_5 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 05 — 11 November 2008 24 of 25 NXP Semiconductors PCA2002 32 kHz watch circuit programmable output period and pulse width 18. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 8 9 10 11 12 12.1 12.2 13 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Motor pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Time calibration . . . . . . . . . . . . . . . . . . . . . . . . 4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Programming possibilities. . . . . . . . . . . . . . . . . 5 Type recognition . . . . . . . . . . . . . . . . . . . . . . . . 6 Programming procedure . . . . . . . . . . . . . . . . . . 7 Programming the memory cells . . . . . . . . . . . . 8 Checking the memory content . . . . . . . . . . . . . 9 Frequency tuning at assembled watch . . . . . . 10 Measurement of the oscillator frequency and the inhibition time. . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 12 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 OTP programming characteristics . . . . . . . . . 14 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Packing information. . . . . . . . . . . . . . . . . . . . . 17 Tray information . . . . . . . . . . . . . . . . . . . . . . . 17 Unsawn wafer information . . . . . . . . . . . . . . . 19 Soldering of WLCSP packages. . . . . . . . . . . . 20 Introduction to soldering WLCSP packages . . 20 Board mounting . . . . . . . . . . . . . . . . . . . . . . . 20 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Quality of solder joint . . . . . . . . . . . . . . . . . . . 21 Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 November 2008 Document identifier: PCA2002_5