PCA2002
32 kHz watch circuit with programmable output period and
pulse width
Rev. 9 — 6 December 2019
Product data sheet
1. General description
The PCA2002 is a CMOS1 integrated circuit for battery operated wrist watches with a
32 kHz quartz crystal as the timing element and a bipolar stepping motor. The quartz
crystal oscillator and the frequency divider are optimized for minimum current
consumption. A timing accuracy of 1 ppm is achieved with a programmable, digital
frequency adjustment.
The output period and the output pulse width can be programmed. It can be selected
between a full output pulse or a chopped output pulse with a duty cycle of 75 %. In
addition, a stretching pulse can be added to the primary driving pulse.
A pad RESET is provided (used for stopping the motor) for accurate time setting and for
accelerated testing of the watch.
2. Features and benefits
Amplitude-regulated 32 kHz quartz crystal oscillator, with excellent frequency stability
and high immunity to leakage currents
Electrically programmable time calibration with 1 ppm resolution stored in One Time
Programmable (OTP) memory
The quartz crystal is the only external component required
Very low current consumption: typically 90 nA
Output pulses for bipolar stepping motors
Five different programmable output periods (1 s to 30 s)
Output pulse width programmable between 1 ms and 8 ms
Full or chopped motor pulse and pulse stretching, selectable
Stop function for accurate time setting and current saving during shelf life
Test mode for accelerated testing of the mechanical parts of the watch
Test bits for type recognition
3. Applications
Driver circuits for bipolar stepping motors
High immunity motor drive circuits
High production volumes
1.
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 14.
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
4. Ordering information
Table 1.
Ordering information
Type number
Topside
marking[1]
Package
Name
Description
Version
PCA2002U/AB/1
PC
2002-1
wire bond die
8 bonding pads;
1.16 0.86 0.22 mm
PCA200xU
PCA2002U/10AB/1
PC
2002-1
wire bond die
8 bonding pads;
1.16 0.86 0.22 mm
PCA200xU
PCA2002DUS/DA
PC
2002-1
WLCSP8
wafer level chip-size package; 8 bumps;
1.16 mm x 0.86 mm
SOT1455-1
[1]
Marking “PC2002-1” on active side of die
4.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
PCA2002U/AB/1
PCA2002U/AB/1,026
wire bond
die
bare die; chip in tray 36000
Tamb = 10 C to +60 C
PCA2002U/10AB/1
PCA2002U/10AB/1,00
wire bond
die
sawn wafer on Film 45192
Frame Carrier
(FFC), see Figure 17
Tamb = 10 C to +60 C
PCA2002DUS/DA
PCA2002DUS/DAZ
WLCSP8
Reel 7" Q1 in tape
reel dry pack
Tamb = 10 C to +60 C
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
Minimum
order
quantity
4000
Temperature
© NXP B.V. 2019. All rights reserved.
2 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
5. Block diagram
32 Hz
OSCIN
8 kHz
OSCILLATOR
DIVIDER
÷4
RESET
RESET
OSCOUT
reset
TIMING ADJUSTMENT,
INHIBITION
VDD
VSS
VOLTAGE DETECTOR,
OTP-CONTROLLER
OTP-MEMORY
1 Hz
MOTOR CONTROL
PCA2002
i.c.
mbl568
MOT1
n.c.
Fig 1.
PCA2002
Product data sheet
n.c.
MOT2
M
Block diagram of PCA2002
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
3 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
6. Pinning information
6.1 Pinning
PCA200xU
VSS
1
i.c.
2
8
RESET
7
MOT2
6
MOT1
5
VDD
x
0
OSCIN
3
OSCOUT
4
0
y
001aai177
Top view. For mechanical details, see Figure 11.
Fig 2.
Pin configuration of PCA2002U
PCA2002DUS/DA
VSS
i.c.
RESET
1
2
8
OSCIN
MOT2
7
3
4
6
5
OSCOUT
MOT1
VDD
aaa-033907
Viewed from active side. For mechanical details, see Figure 12.
Fig 3.
PCA2002
Product data sheet
Pin configuration of PCA2002DUS/DA
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
4 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
6.2 Pin description
Table 3.
Symbol
VSS
PCA2002
Product data sheet
[1]
Pin description
Pin
Description
1
ground
i.c.[2]
2
internally connected
OSCIN
3
oscillator input
OSCOUT
4
oscillator output
VDD
5
supply voltage
MOT1
6
motor 1 output
MOT2
7
motor 2 output
RESET
8
reset input
[1]
The substrate (rear side of the chip) is connected to VSS. Therefore the die pad must be either floating or
connected to VSS.
[2]
Pad i.c. is used for factory tests; in normal operation it should be left open-circuit, and it has an internal
pull-down resistance to VSS.
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
5 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
7. Functional description
7.1 Motor pulse
The motor driver delivers pulses with an alternating polarity. The output waveform across
the motor terminals is illustrated in Figure 4. Between the motor pulses, both terminals are
connected to VDD, which means that the motor is short-circuit.
The following parameters can be selected and are stored in a One Time Programmable
(OTP) memory:
•
•
•
•
Output periods of 1 s, 5 s, 10 s, 20 s and 30 s
Pulse width (tp) between 0.98 ms and 7.8 ms in steps of 0.98 ms
Full or chopped (75 %) output pulse
Pulse stretching: an enlargement pulse is added to the primary motor pulse. This
enlargement pulse has a duty cycle of 25 % and a width, which is twice the
programmed motor pulse width.
period
full pulse
chopped
pulse
full pulse
with stretching
chopped pulse
with stretching
tp
Fig 4.
2t p
tp
2t p
mgu718
Motor output waveforms
7.2 Time calibration
The quartz crystal oscillator has an integrated capacitance of 5.2 pF, which is lower than
the specified capacitance (CL) of 8.2 pF for the quartz crystal (see Table 10). Therefore,
the oscillator frequency is typically 60 ppm higher than 32.768 kHz. This positive
frequency offset is compensated by removing the appropriate number of 8192 Hz pulses
in the divider chain (maximum 127 pulses), every 1 or 2 minutes. The time correction is
given in Table 4.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
6 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
Table 4.
Time calibration
Calibration
period
Correction per step (n = 1)
Correction per step (n = 127)
ppm
seconds per day ppm
seconds per day
1 minute
2.03
0.176
258
22.3
2 minutes
1.017
0.088
129
11.15
After measuring the effective oscillator frequency, the number of correction pulses must
be calculated and stored together with the calibration period in the OTP memory (see
Section 7.6).
The oscillator frequency can be measured at pad RESET, where a square wave signal
1
with the frequency of ------------ f osc is provided.
1024
This frequency shows a jitter every minute or every two minutes, depending on the
programmed calibration period, which originates from the time calibration.
Details on how to measure the oscillator frequency and the programmed inhibition time
are given in Section 7.10.
7.3 Reset
1
At pin RESET an output signal with a frequency of ------------ f osc = 32Hz is provided.
1024
Connecting pin RESET to VDD stops the motor drive and opens the motor switches.
After releasing pin RESET, the first motor pulse is generated exactly one period later with
the opposite polarity to the last pulse before stopping. The debounce time for the reset
function is between 31 ms and 62 ms.
Connecting pin RESET to VSS activates the test mode. In this mode the motor output
frequency is 32 Hz, which can be used to test the mechanical function of the watch.
7.4 Programming possibilities
The programming data is organized in an array of 8-bit words (see Table 5): Word A
contains the time calibration, word B the setting for the monitor pulses, word C is not used
and word D contains the type recognition.
Table 5.
Word
Words and bits
Bit
1
2
3
4
A
number of 8192 Hz pulses to be removed
B
pulse width
5
6
7
8
calibration
period
output period
duty
cycle
pulse
stretching
C
D
PCA2002
Product data sheet
type
factory test bit
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
7 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
Table 6.
Description of word A bits
Bit
Value
Description
-
adjust the number of the 8192 Hz pulses to be removed;
bit 1 is the MSB and bit 7 is the LSB
0
1 minute
1
2 minutes
Inhibit time
1 to 7
Calibration period
8
Table 7.
Description of word B bits
Bit
Value
Description
Pulse width tp (ms)
1 to 3
000
0.98
001
1.95
010
2.9
011
3.9
100
4.9
101
5.9
110
6.8
111
7.8
000
1
001
5
010
10
011
20
100
30
Output period (s)
4 to 6
Duty cycle of motor pulse
7
0
75 %
1
100 %
0
no pulse stretching
1
a pulse width of 2 tp and a duty factor of 25 % are added
Pulse stretching
8
7.5 Type recognition
Byte D is read to determine, which type of the PCA200x family is used in a particular
application.
Table 8.
Description of word D bits
Bit
Value
Description
0000
PCA2002
1000
PCA2000
0100
PCA2001
1100
PCA2003
Type recognition
1 to 4
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
8 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
7.6 Programming procedure
To ensure that the oscillator starts up correctly you must execute a reset sequence (see
Figure 5).
VDD
tp(stop)
VP(prog)(stop)
td(start) > 500 ms
VDD(nom)
VSS
001aac503
td(start): start delay time.
VDD(nom): nominal supply voltage.
Fig 5.
Supply voltage at start-up during production and testing
For a watch it is essential that the timing calibration can be made after the watch is fully
assembled. In this situation, the supply pins are often the only terminals which are still
accessible.
Writing to the OTP cells and performing the related functional checks is achieved in the
PCA2002 by modulating the supply voltage. The necessary control circuit consists
basically of a voltage level detector, an instruction counter, which determines the function
to be performed, and an 8-bit shift register, which allows writing the OTP cells of an 8-bit
word in one step and which acts as data pointer for checking the OTP content.
•
•
•
•
•
•
State 1; measurement of the crystal oscillator frequency (divided by 1024)
State 2; measurement of the inhibition time
State 3; write/check word A
State 4; write/check word B
State 5; check word C (don’t care since no meaning)
State 6; check word D (type recognition)
Each instruction state is switched on with a pulse to VP(prog)(start). After this large pulse, an
initial waiting time of t0 is required. The programming instructions are then entered by
modulating the supply voltage with small pulses (amplitude VP(mod) and pulse width tmod).
The first small pulse defines the start time, the following pulses perform three different
functions, depending on the time delay (td) from the preceding pulse (see Figure 6,
Figure 7, Figure 8, Figure 9 and Figure 10):
• td = t1 (0.7 ms); increments the instruction counter
• td = t2 (1.7 ms); clocks the shift register with data = logic 0
• td = t3 (2.7 ms); clocks the shift register with data = logic 1
The programming procedure requires a stable oscillator, which means that a waiting time,
determined by the start-up time of the oscillator, is necessary after power-up of the circuit.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
9 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
After the VP(prog)(start) pulse, the instruction counter is in state 1 and the data shift register
is cleared.
The instruction state ends with a second pulse to VP(prog)(stop) or with the pulse to Vstore.
In any case, the instruction states are terminated automatically 2 seconds after the last
supply modulation pulse.
7.7 Programming the memory cells
Applying the two-stage programming pulse (see Figure 6) transfers the stored data in the
shift register to the OTP cells.
Perform the following to program a memory word:
1. Starting with a VP(prog)(start) pulse, wait for the time period t0 then set the instruction
counter to the word to be written (td = t1).
2. Enter the data to be stored into the shift register (td = t2 or t3), LSB first (bit 8) and
MSB last (bit 1).
3. Applying the two-stage programming pulse Vprestore followed by Vstore stores the word.
The delay between the last data bit and the pre-store pulse Vprestore is td = t4. Store the
word by raising the supply voltage to Vstore; the delay between the last data bit and the
store pulse is td.
The example shown in Figure 6 performs the following functions:
•
•
•
•
Start
Setting the instruction counter to state 4 (word B)
Entering data word 110101 into the shift register (sequence: LSB first and MSB last)
Writing the OTP cells for word B
tw(prestore)
VDD
Vstore
tp(start)
VP(prog)(start)
Vprestore
t0
t1 t1 t1
t3
t2
t3
t2
t3
t3
t4
tw(store)
VP(mod)
VDD(nom)
VSS
mgw356
The example shows the programming of B = 110101 (the sequence is MSB first and LSB last).
VDD(nom): nominal supply voltage.
Fig 6.
Supply voltage modulation for programming
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
10 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
7.8 Checking the memory content
The stored data of the OTP array can be checked bit wise by measuring the supply
current (see Figure 7). The array word is selected by the instruction state and the bit is
addressed by the shift register.
To read a word, the word is first selected (td = t1) and a logic 1 is written into the first cell of
the shift register (td = t3). This logic 1 is then shifted through the entire shift register
(td = t2), so that it points with each clock pulse to the next bit.
If the addressed OTP cell contains a logic 1, a 30 k resistor is connected between VDD
and VSS; this increases the supply current accordingly.
Figure 7 shows the supply voltage modulation for reading word B, with the corresponding
supply current variation for word B = 110101 (sequence: first MSB and last LSB).
VDD
tp(start)
tp(stop)
VP(prog)(start)
VP(prog)(stop)
t0
t1 t1 t1
t3
t2
t2
t2
t2
t2
VP(mod)
VDD(nom)
VSS
IDD
(1)
mgw357
VDD(nom): nominal supply voltage.
V DD
30 k
(1) I DD = ---------------
Fig 7.
PCA2002
Product data sheet
Supply voltage modulation for reading word B
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
11 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
7.9 Frequency tuning at assembled watch
Figure 8 shows the test set-up for frequency tuning the assembled watch.
32 kHz
M
PCA200x
FREQUENCY
COUNTER
PROGRAMMABLE
DC POWER SUPPLY
motor
battery
PC INTERFACE
PC
mgw568
Fig 8.
Frequency tuning the assembled watch
7.10 Measurement of the oscillator frequency and the inhibition time
The output of the two measuring states can either be monitored directly at pin RESET or
as a modulation of the supply current (a modulating resistor of 30 k is connected
between VDD and VSS when the signal at pin RESET is at HIGH-level).
The supply voltage modulation must be followed as shown in Figure 5 in order to
guarantee the correct start-up of the circuit during production and testing.
Measuring states:
• State 1; quartz crystal oscillator frequency divided by 1024; state 1 starts with a pulse
to VP and ends with a second pulse to VP
• State 2; inhibition time has a value of n 0.122 ms. A signal with the periodicity of
31.25 ms + n 0.122 ms appears at pin RESET and as current modulation at pin VDD
(see Figure 9 and Figure 10)
31.25 ms + inhibition time
VDD
VO(dif)
VSS
mgw355
Fig 9.
PCA2002
Product data sheet
Output waveform at pin RESET for instruction state 2
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
12 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
VDD
t p(stop)
t p(start)
VP(prog)(stop)
VP(prog)(start)
t0
t1
VP(mod)
VDD(nom)
VSS
mgu719
VDD(nom): nominal supply voltage.
Fig 10. Supply voltage modulation for start and stop of instruction state 2
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
13 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
8. Limiting values
Table 9.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
VDD
supply voltage
VI
input voltage
tsc
short circuit duration time
VSS = 0 V
[1][2]
Max
Unit
1.8
+7.0
V
0.5
+7.5
V
-
indefinite
s
HBM
-
2000
V
MM
[4]
-
200
V
latch-up current
[5]
-
100
mA
Tstg
storage temperature
[6]
30
+100
C
Tamb
ambient temperature
10
+60
C
Ilu
electrostatic discharge
voltage
output
Min
[3]
VESD
[1]
Conditions
When writing to the OTP cells, the supply voltage (VDD) can be raised to a maximum of 12 V for a time period of 1 s.
[2]
Connecting the battery with reversed polarity does not destroy the circuit, but in this condition a large
current flows which rapidly discharges the battery.
[3]
Pass level; Human Body Model (HBM), according to Ref. 6 “JESD22-A114”.
[4]
Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[5]
Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[6]
According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be stored at a temperature of
+8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
14 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
9. Characteristics
Table 10. Characteristics
VDD = 1.55 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = 25 C; quartz crystal: Rs = 40 k, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless
otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
normal operating mode;
Tamb = 10 C to +60 C
1.1
1.55
3.6
V
VDD
supply voltage variation
V/t = 1 V/s
-
-
0.25
V
IDD
supply current
between motor pulses
-
90
120
nA
between motor pulses at
VDD = 3.5 V
-
120
180
nA
Supplies
Tamb = 10 C to +60 C
-
-
200
nA
stop mode;
pin RESET connected to VDD
-
100
135
nA
Motor output
Vsat
saturation voltage
Rmotor = 2 k;
Tamb = 10 C to +60 C
-
150
200
mV
Zo(sc)
output impedance (short
circuit)
between motor pulses;
Imotor < 1 mA
-
200
300
1.1
-
-
V
5
10
-
S
-
0.3
0.9
s
-
0.05
0.2
ppm
4.3
5.2
6.3
pF
20
-
-
M
Oscillator
Vstart
start voltage
gm
transconductance
tstartup
start-up time
f/f
frequency stability
CL(itg)
integrated load
capacitance
Rpar
parasitic resistance
Vi(osc) 50 mV(p-p)
VDD = 100 mV
allowed resistance between
adjacent pins
Pad RESET
fo
output frequency
VO(dif)
differential output voltage
-
32
-
Hz
RL = 1 M; CL = 10 pF
[1]
1.4
-
-
V
-
1
-
s
-
1
-
s
-
10
20
nA
tr
rise time
RL = 1 M; CL = 10 pF
[1]
tf
fall time
RL = 1 M; CL = 10 pF
[1]
Ii(AV)
average input current
pin RESET connected to VDD
or VSS
[1]
RL and CL are a load resistor and load capacitor, externally connected to pad RESET.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
15 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
10. OTP programming characteristics
Table 11.
Specifications for OTP programming
Symbol
Parameter[1]
Conditions
Min
Typ
Max
Unit
VDD
supply voltage
during programming procedure
1.5
-
3.0
V
VP(prog)(start)
programming supply voltage (start)
6.6
-
6.8
V
VP(prog)(stop)
programming supply voltage (stop)
6.2
-
6.4
V
VP(mod)
supply voltage modulation
320
350
380
mV
Vprestore
prestore voltage
for prestore pulse
6.2
-
6.4
V
Vstore
supply voltage
for writing to the OTP cells
9.9
10.0
10.1
V
Istore
store current
for writing to the OTP cells
-
-
10
mA
tp(start)
start pulse width
8
10
12
ms
tp(stop)
pulse width of stop pulse
0.05
-
0.5
ms
tmod
modulation pulse width
25
30
40
s
tw(prestore)
prestore pulse width
0.05
-
0.5
ms
tw(store)
store pulse width
for writing to the OTP cells
95
100
110
ms
t0
time 0
waiting time after start pulse
20
-
30
ms
t1
time 1
pulse distance for incrementing
the state counter
0.6
0.7
0.8
ms
t2
time 2
pulse distance for clocking the
data register with data = logic 0
1.6
1.7
1.8
ms
t3
time 3
pulse distance for clocking the
data register with data = logic 1
2.6
2.7
2.8
ms
t4
time 4
waiting time for writing to OTP
cells
0.1
0.2
0.3
ms
SR
slew rate
for modulation of the supply
voltage
0.5
-
5.0
V/s
Rmod
modulation resistance
supply current modulation
read-out resistor
18
30
45
k
[1]
for entering instructions, referred
to VDD
Program each word once only.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
16 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
11. Bare die outline
Wire bond die; 8 bonding pads
PCA200xU
A
D
P1
1
P2
8
e1
(1)
e2
E
4
P4
P3
5
detail X
X
eD
Notes
1. Die marking code. Figure not drawn to scale.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EUROPEAN
PROJECTION
JEITA
ISSUE DATE
08-05-21
11-11-15
PCA200xU
(1) Marking code PC2002-1
Fig 11. Bare die outline of PCA2002U
Table 12. Dimensions of PCA2002U
Original dimensions are in mm.
PCA2002
Product data sheet
Unit (mm)
A
D
E
e1
e2
eD
P1
max
0.22
-
-
-
nom
0.20
1.16
0.86
0.17
min
0.18
-
-
-
-
-
-
0.32
0.96
-
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
P2
P3
P4
0.099
0.089
0.099
0.089
0.096
0.086
0.096
0.086
0.093
0.083
0.093
0.083
© NXP B.V. 2019. All rights reserved.
17 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
WLCSP8: wafer level chip-scale package; 8 bumps; 1.16 x 0.86 x 0.48 mm
E
A
SOT1455-1
B
ball A1
index area
A2
D
A
A1
detail X
e1
y1 C
e
Øv
Øw
b
C
C A B
C
y
C
e3
e4
B
e2
A
ball A1
index area
1
2
3
X
0
1 mm
scale
Dimensions (mm are the original dimensions)
Unit
mm
A
A1
A2
b
D
E
e
e1
e2
e3
e4
v
w
y
max 0.505 0.11 0.395 0.1958 1.19 0.89
nom 0.480 0.10 0.380 0.1780 1.16 0.86 0.28 0.56 0.86 0.43 0.45 0.15 0.05 0.05
min 0.455 0.09 0.365 0.1602 1.13 0.83
y1
0.1
SOT1455-1_po
Outline
version
References
IEC
JEDEC
JEITA
European
projection
Issue date
15-05-04
15-08-17
---
Fig 12. Package outline SOT1455-1 (WLCSP8)
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
18 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
12. Packing information
12.1 Tape and reel information
TOP VIEW
Ø D0
P0
W
T
B0
P1
X
A0
K0
direction of feed
pin 1
The die has active side facing down, pin 1 towards the
sprocket holes with a `dot' mark on topside.
detail X
Original dimensions are in mm.
Figure not drawn to scale.
aaa-034319
Fig 13. Tape and reel details for PCA2002DUS/DA
Table 13. Carrier tape dimensions of PCA2002DUS/DA
Nominal values with production tolerances.
Symbol
Description
Value
Unit
A0
pocket width in x direction
1.00 0.05
mm
B0
pocket width in y direction
1.30 0.05
mm
K0
pocket depth
0.62 0.05
mm
8
mm
Compartments
Overall dimensions
PCA2002
Product data sheet
W
tape width
T
tape thickness
0.2 0.02
mm
D0
sprocket hole diameter
1.5
mm
P0
sprocket hole pitch
4 0.1
mm
P1
pocket pitch
4 0.1
mm
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
19 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
12.2 Tray information
A
x
G
C
H
y
1,1
2,1 3,1
1,2
2,2
x,1
D
B
1,3
F
x,y
1,y
A
A
E
M
J
SECTION A-A
mgu653
Fig 14. Tray details
Table 14.
PCA2002
Product data sheet
Tray dimensions
Dimension
Description
Value
A
pocket pitch; x direction
2.15 mm
B
pocket pitch; y direction
2.43 mm
C
pocket width; x direction
1.01 mm
D
pocket width; y direction
1.39 mm
E
tray width; x direction
50.67 mm
F
tray width; y direction
50.67 mm
G
distance from cut corner to pocket
(1 and 1) center
4.86 mm
H
distance from cut corner to pocket
(1 and 1) center
4.66 mm
J
tray thickness
3.94 mm
M
pocket depth
0.61 mm
x
number of pockets in x direction
20
y
number of pockets in y direction
18
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
20 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
marking code
013aaa565
The orientation of the IC in a pocket is indicated by the position of the die marking code on the
surface of the die (see Figure 11 and Figure 12), with respect to the cut corner on the upper left of
the tray.
Fig 15. Tray alignment
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
21 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
12.3 Wafer and Film Frame Carrier (FFC) information
~18 μm(1)
~18 μm(1)
84 μm
84 μm
Saw lane
Saw lane
detail Y
detail X
~18 μm(1)
84 μm
(1)
1
8
1
8
4
5
4
5
1
8
1
8
Y
X
4
5
4
5
1
8
1
8
4
5
4
5
1
8
1
8
4
5
4
5
1
8
1
8
4
5
4
5
1
8
1
8
4
5
4
5
Straight edge of the wafer
001aai236
The die are grouped in arrays of 2 6 devices. Each array is edged with a metal path. All this metal
paths have to be cut while dicing.
Fig 16. Wafer layout of PCA2002U
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
22 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
214.50 mm
73.68 mm
71.79 mm
2.6 mm
metal frame
0.25
straight edge
of the wafer
214.50 mm
Ø 193.50 mm
Ø
22
5.
50
m
m
plastic film
013aaa350
Fig 17. Film Frame Carrier (FFC) for 6 inch wafer (PCA2002U/10AB/1)
Table 15.
PCA2002 wafer information
Type number
Wafer thickness
Wafer diameter
FFC for wafer size
Marking of bad die
PCA2002U/10AB/1
0.20 mm
6 inch
6 inch
wafer mapping
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
23 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
13. Soldering of WLCSP packages
13.1 Introduction to soldering WLCSP packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note
AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface
mount reflow soldering description”.
Wave soldering is not suitable for this package.
All NXP WLCSP packages are lead-free.
13.2 Board mounting
Board mounting of a WLCSP requires several steps:
1. Solder paste printing on the PCB
2. Component placement with a pick and place machine
3. The reflow soldering itself
13.3 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 18) than a SnPb process, thus
reducing the process window
• Solder paste printing issues, such as smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature), and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic) while being low enough that the packages and/or boards are not
damaged. The peak temperature of the package depends on package thickness and
volume and is classified in accordance with Table 16.
Table 16.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 18.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
24 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 18. Temperature profiles for large and small components
For further information on temperature profiles, refer to application note AN10365
“Surface mount reflow soldering description”.
13.3.1 Stand off
The stand off between the substrate and the chip is determined by:
• The amount of printed solder on the substrate
• The size of the solder land on the substrate
• The bump height on the chip
The higher the stand off, the better the stresses are released due to TEC (Thermal
Expansion Coefficient) differences between substrate and chip.
13.3.2 Quality of solder joint
A flip-chip joint is considered to be a good joint when the entire solder land has been
wetted by the solder from the bump. The surface of the joint should be smooth and the
shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps
after reflow can occur during the reflow process in bumps with high ratio of bump diameter
to bump height, i.e. low bumps with large diameter. No failures have been found to be
related to these voids. Solder joint inspection after reflow can be done with X-ray to
monitor defects such as bridging, open circuits and voids.
13.3.3 Rework
In general, rework is not recommended. By rework we mean the process of removing the
chip from the substrate and replacing it with a new chip. If a chip is removed from the
substrate, most solder balls of the chip will be damaged. In that case it is recommended
not to re-use the chip again.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
25 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
Device removal can be done when the substrate is heated until it is certain that all solder
joints are molten. The chip can then be carefully removed from the substrate without
damaging the tracks and solder lands on the substrate. Removing the device must be
done using plastic tweezers, because metal tweezers can damage the silicon. The
surface of the substrate should be carefully cleaned and all solder and flux residues
and/or underfill removed. When a new chip is placed on the substrate, use the flux
process instead of solder on the solder lands. Apply flux on the bumps at the chip side as
well as on the solder pads on the substrate. Place and align the new chip while viewing
with a microscope. To reflow the solder, use the solder profile shown in application note
AN10365 “Surface mount reflow soldering description”.
13.3.4 Cleaning
Cleaning can be done after reflow soldering.
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
26 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
14. Abbreviations
Table 17.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
FFC
Film Frame Carrier
HBM
Human Body Model
IC
Integrated Circuit
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
OTP
One Time Programmable
PCB
Printed-Circuit Board
TEC
Thermal Expansion Coefficient
WLCSP
Wafer Level Chip-Size Package
15. References
[1]
AN10365 — Surface mount reflow soldering description
[2]
AN10439 — Wafer Level Chip Size Package
[3]
AN10706 — Handling bare die
[4]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[5]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[6]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8]
JESD78 — IC Latch-Up Test
[9]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] NX3-00092 — NXP store and transport requirements
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
27 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
16. Revision history
Table 18.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA2002 v.9
20191206
Product data sheet
-
PCA2002 v.8
Modifications:
PCA2002 v.8
Modifications:
•
•
Removed discontinued parts PCA2002CX8/5/1 and PCA2002CX8/12/1
Added PCA2002DUS/DA
20111125
•
Product data sheet
-
PCA2002 v.7
Added die marking codes
PCA2002 v.7
20101005
Product data sheet
PCA2002_6
20100506
Product data sheet
-
PCA2002_5
PCA2002_5
20081111
Product data sheet
-
PCA2002_4
PCA2002_4
20050907
Product data sheet
-
PCA2002_3
PCA2002_3
20040120
Product specification
-
PCA2002_2
PCA2002_2
20030204
Objective specification
-
PCA2002_1
PCA2002_1
20021025
Objective specification
-
-
PCA2002
Product data sheet
PCA2002_6
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
28 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
17. Legal information
17.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
17.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA2002
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
29 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA2002
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 6 December 2019
© NXP B.V. 2019. All rights reserved.
30 of 31
PCA2002
NXP Semiconductors
32 kHz watch circuit with programmable output period and pulse width
19. Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 6
Motor pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Time calibration . . . . . . . . . . . . . . . . . . . . . . . . 6
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programming possibilities. . . . . . . . . . . . . . . . . 7
Type recognition . . . . . . . . . . . . . . . . . . . . . . . . 8
Programming procedure . . . . . . . . . . . . . . . . . . 9
Programming the memory cells . . . . . . . . . . . 10
Checking the memory content . . . . . . . . . . . . 11
Frequency tuning at assembled watch . . . . . . 12
Measurement of the oscillator frequency and the
inhibition time . . . . . . . . . . . . . . . . . . . . . . . . . 12
8
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14
9
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 15
10
OTP programming characteristics . . . . . . . . . 16
11
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 17
12
Packing information . . . . . . . . . . . . . . . . . . . . 19
12.1
Tape and reel information . . . . . . . . . . . . . . . . 19
12.2
Tray information . . . . . . . . . . . . . . . . . . . . . . . 20
12.3
Wafer and Film Frame Carrier (FFC) information.
22
13
Soldering of WLCSP packages. . . . . . . . . . . . 24
13.1
Introduction to soldering WLCSP packages . . 24
13.2
Board mounting . . . . . . . . . . . . . . . . . . . . . . . 24
13.3
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 24
13.3.1
Stand off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.3.2
Quality of solder joint . . . . . . . . . . . . . . . . . . . 25
13.3.3
Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.3.4
Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27
15
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 28
17
Legal information. . . . . . . . . . . . . . . . . . . . . . . 29
17.1
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 29
17.2
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.3
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
17.4
18
19
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Contact information . . . . . . . . . . . . . . . . . . . . 30
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2019.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 December 2019
Document identifier: PCA2002
工商网监
湘ICP备2023018690号
