PCA2129T/Q900/2,51

PCA2129 Automotive accurate RTC with integrated quartz crystal Rev. 5 — 19 December 2014 Product data sheet 1. General description The PCA2129 is a CMOS1 Real Time Clock (RTC) and calendar with an integrated Temperature Compensated Crystal (Xtal) Oscillator (TCXO) and a 32.768 kHz quartz crystal optimized for very high accuracy and very low power consumption. The PCA2129 has a selectable I2C-bus or SPI-bus, a backup battery switch-over circuit, a programmable watchdog function, a timestamp function, and many other features. For a selection of NXP Real-Time Clocks, see Table 83 on page 73 2. Features and benefits                      1. AEC-Q100 compliant for automotive applications Operating temperature range from 40 C to +85 C Temperature Compensated Crystal Oscillator (TCXO) with integrated capacitors Typical accuracy: 3 ppm from 30 C to +80 C Integration of a 32.768 kHz quartz crystal and oscillator in the same package Provides year, month, day, weekday, hours, minutes, seconds, and leap year correction Timestamp function  with interrupt capability  detection of two different events on one multilevel input pin (for example, for tamper detection) Two line bidirectional 400 kHz Fast-mode I2C-bus interface 3 line SPI-bus with separate data input and output (maximum speed 6.5 Mbit/s) Battery backup input pin and switch-over circuitry Battery backed output voltage Battery low detection function Power-On Reset Override (PORO) Oscillator stop detection function Interrupt output (open-drain) Programmable 1 second or 1 minute interrupt Programmable watchdog timer with interrupt Programmable alarm function with interrupt capability Programmable square output Clock operating voltage: 1.8 V to 4.2 V Low supply current: typical 0.70 A at VDD = 3.3 V The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21. PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 3. Applications       Electronic metering for electricity, water, and gas Precision timekeeping Access to accurate time of the day GPS equipment to reduce time to first fix Applications that require an accurate process timing Products with long automated unattended operation time 4. Ordering information Table 1. Ordering information Type number Package PCA2129T Name Description Version SO16 plastic small outline package; 16 leads; SOT162-1 body width 7.5 mm 4.1 Ordering options Table 2. Ordering options Product type number Orderable part number Sales item (12NC) Delivery form IC revision PCA2129T/Q900/2 PCA2129T/Q900/2,51 tape and reel, 13 inch, dry pack 2 935296923518 5. Marking Table 3. PCA2129 Product data sheet Marking codes Product type number Marking code PCA2129T/Q900/2 PCA2129T/Q All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 2 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 6. Block diagram ,17 7&;2 26&, ',9,'(5 $1' 7,0(5 N+] 26&2 &/.287 9'' 9%$7 966 %$77(5 VBAT OR VDD > Vth(sw)bat: Voper(int) is at VDD potential. If VDD < VBAT AND VDD < Vth(sw)bat: Voper(int) is at VBAT potential. EDFNXSEDWWHU\RSHUDWLRQ 9'' 9RSHULQW 9%$7 9RSHULQW LQWHUQDORSHUDWLQJYROWDJH9RSHULQW 9WKVZEDW  9 9'' 9 %) ,17 FOHDUHGYLDLQWHUIDFH DDM Vth(sw)bat is the battery switch threshold voltage. Typical value is 2.5 V. In standard mode, the battery switch-over works only for VDD > 2.5 V. VDD may be lower than VBAT (for example VDD = 3 V, VBAT = 4.1 V). Fig 5. PCA2129 Product data sheet Battery switch-over behavior in standard mode with bit BIE set logic 1 (enabled) All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 18 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 8.5.1.2 Direct switching mode If VDD > VBAT: Voper(int) is at VDD potential. If VDD < VBAT: Voper(int) is at VBAT potential. The direct switching mode is useful in systems where VDD is always higher than VBAT. This mode is not recommended if the VDD and VBAT values are similar (for example, VDD = 3.3 V, VBAT  3.0 V). In direct switching mode, the power consumption is reduced compared to the standard mode because the monitoring of VDD and Vth(sw)bat is not performed. EDFNXSEDWWHU\RSHUDWLRQ 9'' 9RSHULQW 9%$7 9RSHULQW LQWHUQDORSHUDWLQJYROWDJH9RSHULQW 9WKVZEDW  9 9'' 9 %) ,17 FOHDUHGYLDLQWHUIDFH DDM Fig 6. 8.5.1.3 Battery switch-over behavior in direct switching mode with bit BIE set logic 1 (enabled) Battery switch-over disabled: only one power supply (VDD) When the battery switch-over function is disabled: • • • • PCA2129 Product data sheet The power supply is applied on the VDD pin The VBAT pin must be connected to ground Voper(int) is at VDD potential The battery flag (BF) is always logic 0 All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 19 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 8.5.1.4 Battery switch-over architecture The architecture of the battery switch-over circuit is shown in Figure 7. FRPSDUDWRUV ORJLF VZLWFKHV 9'' 9WKVZEDW 9'' 9RSHULQW /2*,& 9WKVZEDW 9%$7 9%$7 DDJ Fig 7. Battery switch-over circuit, simplified block diagram Voper(int) is at VDD or VBAT potential. Remark: It has to be assured that there are decoupling capacitors on the pins VDD, VBAT, and BBS. 8.5.2 Battery low detection function The PCA2129 has a battery low detection circuit which monitors the status of the battery VBAT. When VBAT drops below the threshold value Vth(bat)low (typically 2.5 V), the BLF flag (register Control_3) is set to indicate that the battery is low and that it must be replaced. Monitoring of the battery voltage also occurs during battery operation. An unreliable battery cannot prevent that the supply voltage drops below Vlow (typical 1.2 V) and with that the data integrity gets lost. (For further information about Vlow see Section 8.6.) When VBAT drops below the threshold value Vth(bat)low, the following sequence occurs (see Figure 8): 1. The battery low flag BLF is set logic 1. 2. An interrupt is generated if the control bit BLIE (register Control_3) is enabled (see Section 8.12.7). 3. The flag BLF remains logic 1 until the battery is replaced. BLF cannot be cleared by command. It is automatically cleared by the battery low detection circuit when the battery is replaced or when the voltage rises again above the threshold value. This could happen if a super capacitor is used as a backup source and the main power is applied again. PCA2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 20 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 9'' 9RSHULQW LQWHUQDORSHUDWLQJYROWDJH9RSHULQW 9%$7 9WKEDWORZ  9 9%$7 %/) ,17 DDM Fig 8. Battery low detection behavior with bit BLIE set logic 1 (enabled) 8.5.3 Battery backup supply The VBBS voltage on the output pin BBS is at the same potential as the internal operating voltage Voper(int), depending on the selected battery switch-over function mode: Table 20. Output pin BBS Battery switch-over function mode Conditions Potential of Voper(int) and VBBS standard VDD > VBAT OR VDD > Vth(sw)bat VDD VDD < VBAT AND VDD < Vth(sw)bat VBAT direct switching VDD > VBAT VDD VDD < VBAT VBAT disabled only VDD available, VBAT must be put to ground VDD The output pin BBS can be used as a supply for external devices with battery backup needs, such as SRAM (see Ref. 3 “AN11186”). For this case, Figure 9 shows the typical driving capability when VBBS is driven from VDD. PCA2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 21 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal DDM  9%%6 9'' P9   9'' 9   9'' 9 9'' 9          ,%%6P$ Fig 9. Typical driving capability of VBBS: (VBBS  VDD) with respect to the output load current IBBS 8.6 Oscillator stop detection function The PCA2129 has an on-chip oscillator detection circuit which monitors the status of the oscillation: whenever the oscillation stops, a reset occurs and the oscillator stop flag OSF (in register Seconds) is set logic 1. • Power-on: a. The oscillator is not running, the chip is in reset (OSF is logic 1). b. When the oscillator starts running and is stable after power-on, the chip exits from reset. c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. • Power supply failure: a. When the power supply of the chip drops below a certain value (Vlow), typically 1.2 V, the oscillator stops running and a reset occurs. b. When the power supply returns to normal operation, the oscillator starts running again, the chip exits from reset. c. The flag OSF is still logic 1 and can be cleared (OSF set logic 0) by command. PCA2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 22 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 9'' 9RSHULQW 9'' 9RSHULQW 9%$7 9%$7 9WKVZEDW  9 9'' 9'' EDWWHU\GLVFKDUJH 9ORZ  9 9RSHULQW 9%$7 966 966   26) DDM (1) Theoretical state of the signals since there is no power. (2) The oscillator stop flag (OSF), set logic 1, indicates that the oscillation has stopped and a reset has occurred since the flag was last cleared (OSF set logic 0). In this case, the integrity of the clock information is not guaranteed. The OSF flag is cleared by command. Fig 10. Power failure event due to battery discharge: reset occurs 8.7 Reset function The PCA2129 has a Power-On Reset (POR) and a Power-On Reset Override (PORO) function implemented. 8.7.1 Power-On Reset (POR) The POR is active whenever the oscillator is stopped. The oscillator is considered to be stopped during the time between power-on and stable crystal resonance (see Figure 11). This time may be in the range of 200 ms to 2 s depending on temperature and supply voltage. Whenever an internal reset occurs, the oscillator stop flag is set (OSF set logic 1). The OTP refresh (see Section 8.3.2 on page 13) should ideally be executed as the first instruction after start-up and also after a reset due to an oscillator stop. PCA2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 23 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal FKLSLQUHVHW FKLSQRWLQUHVHW FKLSIXOO\RSHUDWLYH &/.287 DYDLODEOH 9'' RVFLOODWLRQ LQWHUQDO UHVHW 2735 W DDD Fig 11. Dependency between POR and oscillator After POR, the following mode is entered: • • • • • 32.768 kHz CLKOUT active Power-On Reset Override (PORO) available to be set 24-hour mode is selected Battery switch-over is enabled Battery low detection is enabled The register values after power-on are shown in Table 5 on page 8. 8.7.2 Power-On Reset Override (PORO) The POR duration is directly related to the crystal oscillator start-up time. Due to the long start-up times experienced by these types of circuits, a mechanism has been built in to disable the POR and therefore speed up the on-board test of the device. 26&,//$725 6&/ 6'$&( 5(6(7 29(55,'( RVFVWRSSHG  VWRSSHG UXQQLQJ UHVHW  RYHUULGHLQDFWLYH  RYHUULGHDFWLYH &/($5 325B295'  FOHDURYHUULGHPRGH  RYHUULGHSRVVLEOH DDM Fig 12. Power-On Reset (POR) system The setting of the PORO mode requires that POR_OVRD in register Control_1 is set logic 1 and that the signals at the interface pins SDA/CE and SCL are toggled as illustrated in Figure 13. All timings shown are required minimum. PCA2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 24 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal SRZHUXS PV PLQLPXPQV PLQLPXPQV 6'$&( 6&/ UHVHWRYHUULGH DDM Fig 13. Power-On Reset Override (PORO) sequence, valid for both I2C-bus and SPI-bus Once the override mode is entered, the device is immediately released from the reset state and the set-up operation can commence. The PORO mode is cleared by writing logic 0 to POR_OVRD. POR_OVRD must be logic 1 before a re-entry into the override mode is possible. Setting POR_OVRD logic 0 during normal operation has no effect except to prevent accidental entry into the PORO mode. 8.8 Time and date function Most of these registers are coded in the Binary Coded Decimal (BCD) format. 8.8.1 Register Seconds Table 21. Seconds - seconds and clock integrity register (address 03h) bit allocation Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 Symbol 6 5 4 OSF Reset value 1 3 2 1 0 X X X SECONDS (0 to 59) X X X X Table 22. Seconds - seconds and clock integrity register (address 03h) bit description Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol 7 OSF Value Place value Description 0 - clock integrity is guaranteed 1 - clock integrity is not guaranteed: oscillator has stopped and chip reset has occurred since flag was last cleared 6 to 4 SECONDS 3 to 0 PCA2129 Product data sheet 0 to 5 ten’s place 0 to 9 unit place actual seconds coded in BCD format All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 25 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal Table 23. Seconds coded in BCD format Seconds value in decimal Upper-digit (ten’s place) Digit (unit place) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 0 0 0 0 0 0 01 0 0 0 0 0 0 1 02 0 0 0 0 0 1 0 : : : : : : : : 09 0 0 0 1 0 0 1 10 0 0 1 0 0 0 0 : : : : : : : : 58 1 0 1 1 0 0 0 59 1 0 1 1 0 0 1 8.8.2 Register Minutes Table 24. Minutes - minutes register (address 04h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 Symbol - Reset value - 6 5 4 3 2 1 0 X X X MINUTES (0 to 59) X X X X Table 25. Minutes - minutes register (address 04h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 - - - unused 6 to 4 MINUTES 0 to 5 ten’s place actual minutes coded in BCD format 0 to 9 unit place 3 to 0 PCA2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 26 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 8.8.3 Register Hours Table 26. Hours - hours register (address 05h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 Symbol - - AMPM 4 3 2 1 0 HOURS (1 to 12) in 12-hour mode HOURS (0 to 23) in 24-hour mode Reset value - - X X X X X X Table 27. Hours - hours register (address 05h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 6 - - - unused - indicates AM 12-hour mode[1] 5 AMPM 0 1 - indicates PM 4 HOURS 0 to 1 ten’s place 0 to 9 unit place actual hours coded in BCD format when in 12-hour mode 0 to 2 ten’s place 0 to 9 unit place 3 to 0 24-hour mode[1] 5 to 4 HOURS 3 to 0 [1] actual hours coded in BCD format when in 24-hour mode Hour mode is set by the bit 12_24 in register Control_1 (see Table 7). 8.8.4 Register Days Table 28. Days - days register (address 06h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 Symbol - - Reset value - - Table 29. 5 4 3 2 X X X X 0 X X Days - days register (address 06h) bit description Bit Symbol Value Place value Description 7 to 6 - - - unused 5 to 4 DAYS[1] 0 to 3 ten’s place actual day coded in BCD format 0 to 9 unit place 3 to 0 [1] 1 DAYS (1 to 31) If the year counter contains a value which is exactly divisible by 4, including the year 00, the RTC compensates for leap years by adding a 29th day to February. PCA2129 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 27 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 8.8.5 Register Weekdays Table 30. Weekdays - weekdays register (address 07h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 4 3 Symbol - - - - - Reset value - - - - - 2 1 0 WEEKDAYS (0 to 6) X X X Table 31. Weekdays - weekdays register (address 07h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Description 7 to 3 - - unused 2 to 0 WEEKDAYS 0 to 6 actual weekday value, see Table 32 Although the association of the weekdays counter to the actual weekday is arbitrary, the PCA2129 assumes that Sunday is 000 and Monday is 001 for the purpose of determining the increment for calendar weeks. Table 32. Weekday assignments Day[1] 2 1 0 Sunday 0 0 0 Monday 0 0 1 Tuesday 0 1 0 Wednesday 0 1 1 Thursday 1 0 0 Friday 1 0 1 Saturday 1 1 0 [1] PCA2129 Product data sheet Bit Definition may be reassigned by the user. All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 28 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 8.8.6 Register Months Table 33. Months - months register (address 08h) bit allocation Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 Symbol - - - Reset value - - - 4 3 2 1 0 X X MONTHS (1 to 12) X X X Table 34. Months - months register (address 08h) bit description Bit positions labeled as - are not implemented and return 0 when read. Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 5 - - - unused 4 MONTHS 0 to 1 ten’s place actual month coded in BCD format, see Table 35 0 to 9 unit place 3 to 0 Table 35. Month PCA2129 Product data sheet Month assignments in BCD format Upper-digit (ten’s place) Digit (unit place) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 January 0 0 0 0 1 February 0 0 0 1 0 March 0 0 0 1 1 April 0 0 1 0 0 May 0 0 1 0 1 June 0 0 1 1 0 July 0 0 1 1 1 August 0 1 0 0 0 September 0 1 0 0 1 October 1 0 0 0 0 November 1 0 0 0 1 December 1 0 0 1 0 All information provided in this document is subject to legal disclaimers. Rev. 5 — 19 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 29 of 84 PCA2129 NXP Semiconductors Automotive accurate RTC with integrated quartz crystal 8.8.7 Register Years Table 36. Years - years register (address 09h) bit allocation Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit 7 6 5 X X X Symbol 4 3 2 1 0 X X X YEARS (0 to 99) Reset value X X Table 37. Years - years register (address 09h) bit description Bits labeled as X are undefined at power-on and unchanged by subsequent resets. Bit Symbol Value Place value Description 7 to 4 YEARS 0 to 9 ten’s place 0 to 9 unit place 3 to 0 actual year coded in BCD format 8.8.8 Setting and reading the time Figure 14 shows the data flow and data dependencies starting from the 1 Hz clock tick. During read/write operations, the time counting circuits (memory locations 03h through 09h) are blocked. This prevents • Faulty reading of the clock and calendar during a carry condition • Incrementing the time registers during the read cycle +]WLFN 6(&21'6 0,187(6 BKRXUPRGH +2856 /($3