PCA24S08AD

PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection Rev. 01 — 19 January 2010 Product data sheet 1. General description The PCA24S08A provides 8192 bits of serial Electrically Erasable and Programmable Read-Only Memory (EEPROM) organized as 1024 words of 8 bits each. Data bytes are received and transmitted via the serial I2C-bus. Access permissions limiting reads or writes are set via the I2C-bus to isolate blocks of memory from improper access. The PCA24S08A is intended to be pin compatible with standard 24C08 serial EEPROM devices except for pins 1, 2, and 3, which are address pins in the standard part. Other exceptions to the PCA24S08A serial EEPROM data sheet are noted in Section 6.6. All bits are sent to or read from the device, most significant bit first, in a manner consistent with the 24C08 serial EEPROM. The bit fields in this document are correspondingly listed with the MSB on the left and the LSB on the right. The EEPROM memory is broken up into 8 blocks of 1 kbit (128 bytes) each. Within each block, the memory is physically organized in to 8 pages of 128 bits (16 bytes) each. In addition to these 8 kbits, there are two more 128-bit pages that are used to store the access protection and ID information. There are a total of 8448 bits of EEPROM memory available in the PCA24S08A. Access protection (both read and write) is organized on a block basis for block 1 through block 7 and on a page and a block basis for block 0. Protection information for these blocks and pages is stored in one of the additional pages of EEPROM memory that is addressed separately from the main data storage array. SeeSection 6.4 for more details. The ID value is located in the ID page of the EEPROM, the second of the additional 16 byte pages. Writes from the serial interface may include from one byte to 16 bytes at a time, depending on the protocol followed by the bus master. All page accesses must be properly aligned to the internal EEPROM page. The EEPROM memory offers an endurance of 100,000 write cycles per byte, with 10 year data retention. Writes to the EEPROM take less than 5 ms to complete. After manufacturing, all EEPROM bits will be set to a value of ‘1’. NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 2. Features Non-volatile storage of 8 kbits organized as 8 blocks of 128 bytes each I2C-bus interface logic Compatible with 24C08 serial EEPROM, and alternate source of Atmel AT24RF08C without the RF interface Write operation: Byte write mode 16-byte page write mode Read operation: Sequential read Random read Programmable access protection to limit reads and writes Lock/unlock function Write protect feature protecting the full memory array against write operations Self timed write cycle Internal power-on reset High reliability: Ten years non-volatile data retention time 100,000 write cycle endurance Low power CMOS technology Operating power supply voltage range of 2.5 V to 3.6 V 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO8, TSSOP8 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C Type number PCA24S08AD PCA24S08ADP Topside mark P24S08A PS08A Package Name SO8 TSSOP8 Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm Version SOT96-1 SOT505-1 PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 2 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 4. Block diagram PCA24S08A SDA SCL INPUT FILTER I2C-BUS CONTROL LOGIC WP PROT BYTE COUNTER EEPROM 8 PAGES (8 × 128 BYTES EACH) ACCESS PROTECTION SEQUENCER DIVIDER (÷ 128) BYTE LATCH (8 BYTES) ADDRESS POINTER IDENTIFICATION NUMBER EE CONTROL VDD POWER-ON RESET TIMER (÷ 16) OSCILLATOR 002aae786 VSS Fig 1. Block diagram 5. Pinning information 5.1 Pinning n.c. n.c. PROT VSS 1 2 8 7 VDD WP SCL SDA n.c. n.c. PROT VSS 1 2 3 4 002aae785 8 7 VDD WP SCL SDA PCA24S08AD 3 4 002aae784 6 5 PCA24S08ADP 6 5 Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 3 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 5.2 Pin description Table 2. Symbol n.c. PROT VSS SDA SCL WP VDD Pin description Pin 1, 2 3 4 5 6 7 8 Description not connected active LOW protect reset input ground supply voltage serial data; open-drain I/O serial clock; open-drain input active HIGH write protect input supply voltage 6. Functional description Refer to Figure 1 “Block diagram”. 6.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA24S08A is shown in Figure 4. 1 0 1 fixed 0 1 B2 B1 R/W sofware selectable 002aae789 Fig 4. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read operation is selected, while logic 0 selects a write operation. Bits B2 and B1 in the slave address represent the 2 most significant bits of the word to be addressed. The third device address bit in the I2C-bus protocol that is usually matched to A2 (pin 3) on a standard 24C08 serial EEPROM is internally connected HIGH, so device addresses A8h through AFh (hex) are used to access the memory on the chip. 6.2 Write operations Write operations on the device can be performed only when WP is held LOW. When the WP pin is held HIGH, content of the full memory is protected (Block 0 to Block 7, APP registers, ID Page), and no write operation is allowed. 6.2.1 Byte/word write Write command may be used to set the address for a subsequent Read command. For a write operation, the PCA24S08A requires a second address field. The address field associated with the two software selectable bits in the slave address is a word address providing access to the 1024 bytes of memory, as shown in Figure 5. Upon receipt of the word address, the PCA24S08A responds with an acknowledge and awaits the next 8 bits of data, again responding with an acknowledge. Word address is automatically incremented. PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 4 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection BYTE 0 0 PAGE 0 0 0 0 BYTE 15 BLOCK 0 0 0 0 BYTE 0 0 PAGE 7 1 1 1 BYTE 15 1 1 1 1 0 0 0 1 1 1 1 0 0 0 BYTE 0 0 PAGE 0 0 0 0 BYTE 15 BLOCK 7 1 1 1 BYTE 0 0 PAGE 7 1 1 1 BYTE 15 1 1 1 1 0 0 0 1 1 1 1 0 0 0 1 0 1 fixed 0 1 B2 B1 R/W B0 P2 P1 page number P0 A3 A2 A1 A0 block number byte address 002aae790 Fig 5. Memory addressing Figure 6 shows how the memory array is addressed when the slave address byte and address field byte are sent. The master terminates the transfer by generating a STOP condition. After this STOP condition, the Erase/Write (E/W) cycle starts and the I2C-bus is free for another transmission. Up to 16 bytes of data can be written in the slave writing sequence (E/W cycle). PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 5 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection word address S 1 0 1 0 1 B2 B1 0 auto-increment word address word address A B0 P2 P1 P0 A3 A2 A1 A0 A DATA A DATA auto-increment word address A P START condition R/W acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave STOP condition 002aae791 Fig 6. Auto-increment memory word address (2 byte write) The general command encoding used by the serial port for EEPROM accesses is shown in Figure 11, where B[2:0] is the block number, P[2:0] is the page number within the block and A[3:0] is the byte address within the page. Bits denoted as ‘X’ are ignored by the device. 6.2.2 Page write The PCA24S08A is capable of a 16-byte page write operation. It is initiated in the same manner as the byte write operation. The master can transit 16 data bytes within one transmission. After receipt of each byte, the PCA24S08A will respond with an acknowledge. The typical E/W time in this mode is 5 ms. After the receipt of each data byte, the four low-order bits of the word address are internally incremented. The six high-order bits of the address remain unchanged. The slave acknowledges the reception of each data byte with an ACK. The I2C-bus data transfer is terminated by the master after the 16th byte of data with a STOP condition. After a write to the last byte in a page, the internal address is wrapped around to point to the beginning of that page. If the master transmits more than 16 bytes prior to generating the STOP condition, no acknowledge will be given on the 17th (and following) data bytes and the whole transmission will be ignored and no programming will be done. As in the byte write operation, all inputs are disabled until completion of the internal write cycles. After this STOP condition, the E/W cycle starts and the I2C-bus is free for another transmission. During the E/W cycle the slave receiver does not acknowledge if addressed via the I2C-bus. PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 6 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection word address S 1 0 1 0 1 B2 B1 0 auto-increment word address word address A B0 P2 P1 P0 A3 A2 A1 A0 A DATA A DATA + 1 auto-increment word address A (cont.) START condition R/W acknowledge from slave acknowledge from slave acknowledge from slave acknowledge from slave auto-increment word address last byte (cont.) DATA + 15 A P acknowledge from slave STOP condition 002aae792 Fig 7. Page write operation (16 bytes) 6.3 Read operations Read operations are initiated in the same manner as write operations with the exception that the LSB of the slave address is set to logic 1. The lower 7 bits of the word address are incremented after each transmission of a data byte during a read. The three MSBs of the word address are not changed when the word counter overflows. Thus, the word address overflows from 127 to 0, and from 255 to 128. After the read of the last byte within a block, the internal serial address wraps around to point at the beginning of that block. word address first part S 1 0 1 0 1 B2 B1 0 word address second part A B0 P2 P1 P0 A3 A2 A1 A0 A (cont.) START condition R/W acknowledge from slave acknowledge from slave auto-increment word address auto-increment word address at this moment master transmitter becomes master receiver and EEPROM slave transmitter (cont.) S 1 0 1 0 1 X X 1 A DATA n bytes A DATA last byte A P ReSTART condition R/W acknowledge from master acknowledge from master no acknowledge from master STOP condition 002aae793 Fig 8. PCA24S08A_1 Master reads PCA24S08A slave after setting word address (write word address: read data); sequential read © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 7 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection auto-increment word address auto-increment word address S 1 0 1 0 1 X X 1 A DATA n bytes A DATA last byte A P START condition R/W acknowledge from slave acknowledge from master no acknowledge from master STOP condition 002aae794 Fig 9. Master read PCA24S08A immediately after first byte (read mode); current address read 6.4 Access protection Write operation on the Access protection registers can be performed when WP pin is LOW. If the WP pin is HIGH, all write operations are prohibited from the serial port, although write commands may be used to set the address for a subsequent read command. All access protection bits are stored on a separate page of the EEPROM that is not accessed using the normal commands of a PCA24S08A memory. See Section 6.4.2.2 “Access Protection Page (APP)” for more detail on this information. 6.4.1 RFID access fields (RF) Even though the PCA24S08A does not have the RFID capability, RFID access fields (RF) can be stored in order to keep existing software compatibility. The fields are stored in the EEPROM and organized as shown in Table 3. Table 3. MSB 0 0 1 1 0 1 0 1 RFID access field organization LSB Function no accesses permitted from RFID port no accesses permitted from RFID port read only from RFID port no restrictions for RFID accesses 6.4.2 Protection bits (PB) The protection bits fields in the Access Protection Page determine what type of accesses will be permitted via the serial port for each of the blocks on the chip. If an illegal access is attempted, the command will be NACKed. The MSB (if clear) prohibits all access to the block, and the LSB (if clear) prohibits writes. The fields are stored in the EEPROM and are organized as shown in Table 4. Table 4. MSB 0 0 1 1 PCA24S08A_1 PB organization LSB 0 1 0 1 Function no accesses permitted in the block no accesses permitted in the block read only; writes cause a NACK read/write; no access constraints for data within this block © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 8 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection Accessed within the Access Protection Page is an individual CMOS Sticky Bit (SB) for each of the 8 blocks on the device. When the value of the sticky bit is ‘0’, the Protection Bits (PB) for the corresponding block may not be changed via the software. These bits are all set to logic 1 when power is initially applied or when the PROT pin is LOW. These sticky bits may be written only to a ‘0’ via the serial interface using the standard serial write operations. Reading the sticky bits does not affect their state. Because permissions are set individually for each of the blocks, all reads via serial port will only read bytes within the block that was specified when the current address was latched in the device (with a write command). The block address bits (B2 or B1) that are sent with the write command are ignored on a read command. When a sticky bit is cleared (programmed at 0), the byte containing the sticky bit cannot be changed anymore. If a write operation to this byte is attempted, it will be normally acknowledged but no change will happen in the byte value. The device does not go to an E/W cycle and can be accessed immediately. If a block is protected and only read operation is allowed (the corresponding APP register has its PB bits programmed to 10b), a write operation to this block is not acknowledged (Slave Address and Register pointer only are acknowledged). The device does not go to an E/W cycle and can be accessed immediately. S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK This applies to: • EEPROM block 0 to block 7, controlled by PB0 to PB7. • The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled by PBAP. If a block is protected and neither read operation nor write operation is allowed (the corresponding APP register has its PB bits programmed to 00b or 01b), a write operation to this block is not acknowledged (Slave Address and Register pointer only are acknowledged). S – Addr+W – ACK – Reg Pointer – ACK – Data – NACK A read operation to this block is not allowed. S – Addr+W – ACK – Reg Pointer – ACK – Sr – Addr+R – NACK S – Addr+W – ACK – Reg Pointer – ACK – P – S – Addr+R – NACK This applies to: • EEPROM block 0 to block 7, controlled by PB0 to PB7. • The last 7 bytes of the APP block (09h to 0Fh) and the ID page (10h to 1Fh) controlled by PBAP. PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 9 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 6.4.2.1 Block 0 write protection bits The PCA24S08A provides a mechanism to divide block 0 into eight 128-bit (16-byte) pages that can be individually protected against writes. These eight write protection (WPN) bits are stored within a byte of the access protection page and are organized such that the LSB protects the first 128 bits, and so on. If a bit in this byte is set to a one and the PB0 field is set to 11b, then writes are permitted on the page corresponding to the WPN bit. If the WPN bit is set to a logic 0 or the PB0 is any value other than 11b, then writes are not permitted in that page. The Write Protection hierarchy for serial accesses is shown in Figure 10. In this drawing the bits within the boxes to the left of the arrows are the only thing that determine whether or not the bit in the box to the right of the arrow can be written. Read access control is not shown in this diagram. Addresses listed in this diagram are for the serial port assuming that the R/W bit in the command byte is set to ‘0’. WP SB0 PB0 Page 0 16 bytes WPN0 WPN1 Page 1 16 bytes A800 A80F A810 A81F Block 0 SBAP PBAP WPN7 Page 7 16 bytes Block 1 128 bytes A870 A87F A880 SB1 PB1 A8FF AE80 SB7 PB7 Block 7 128 bytes AEFF SB0 SB0 SB1 SB1 PB0 B800 PB1 B801 Access Protection Page SB7 SB7 SBAP 7 bytes PB7 B807 PBAP B808 B809 B80F B810 B81F SBAP PBAP ID page 16 bytes 002aae842 Fig 10. Write protection example PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 10 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection For example, when SB1 is a 1, the PB1 field can be written to any value by the system. When the PB1 field is 11b, Block 1 can be written to by the system. Note that the state of the SB1 bit does not affect whether or not Block 1 can be written. There is no individual page Write Protection for any other block other than block 0 within the device. Within the remaining blocks on the chip, access permissions are controlled on a block basis (BP bits) or full chip basis (WP pin) only. 6.4.2.2 Access Protection Page (APP) The serial port may be used to read and write the Access Protection Page (APP) and ID Page using device access codes B8h and B9h instead of the normal value of A8h through AFh (hex) that are used to access the rest of the EEPROM memory. The second byte of write commands (the word address) should be in the range of 00h through 0Fh for the APP page and 10h through 1Fh for the ID page. This coding is shown in Figure 11. Reads and writes to these two pages may take place on a single byte basis only. Multi-byte operations will be NACKed. As an example, the bit encoding for a single byte read and write command are shown in Figure 11. The PCA24S08A will acknowledge all device addresses of B8h or B9h. If the most significant three its of the word address are not all 0 (indicating an address outside the Access protection and ID pages), the chip will NACK the access. Byte 0 through byte 7 of the APP contain 8 identical sets of access control fields (PBx and SBx) for each of the eight blocks of memory on the chip, which operate according to Table 4. When the sticky bit in one of these bytes is set, that byte can be written by the system. Once a sticky bit is reset (written to zero) by the software, the byte containing it can no longer be modified by the software until the next power cycle. These bytes can always be read by the system. Byte 8 contains another PB field (PBAP) as bit 0 and bit 1, and an additional sticky bit (SBAP) as bit 7. The value of the PBAP bits controls read and write access to the last 7 bytes (byte 9 through byte 15) of the APP and all 16 bytes of the ID page according to the encoding listed in Section 6.4. The value of the PBAP bits can only be changed, a write from the serial port, when SBAP is HIGH. This byte can always be read by the system. Bit 0 through bit 6 of this byte are stored in EEPROM memory and do not change when the power is cycled or the PROT pin changes state. Byte 9 contains the eight block 0 write protection bits (WPN) for each page within block 0. Byte 10 emulates a coil detection feature to keep compatibility with existing software controlling device. Even though the PCA24S08A does not have the RFID capability of the AT24RF03C, it gives a ‘coil non-detected’ information when the detection feature is initiated. The detection feature uses the Detection Enable bit (DE) and the Detect Coil bit (DC). At power-up, DE = 0 and DC = 1. Detection is enabled by setting DE bit at 1. Since no coil is detected, DC is then automatically reset and equal to 0. DE is a read/write bit; DC is a read-only bit. Attempts to write to this bit will be ignored. PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 11 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection Bit 0 in the same byte emulates a TAMPER bit and is always equal to 0. TAMPER is a read-only bit. Attempt to write a ‘1’ to this bit will be ignored. Byte 11 through byte 14 are currently reserved and should not be used by the system. Byte 14 may not be written by the device at any time. Byte 11 to byte 13 are read/write bytes that are stored in the EEPROM. Byte 14 is a read-only byte and the returned value during a read operation is FFh. A write on it is acknowledged, but the write will be ignored. 1 0 1 1 1 0 0 0 0 0 0 P0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 002aae843 P0 is used to distinguish between the APP and RFID pages: 0 = APP pages 1 = RFID pages a. Write operations 1 0 1 1 1 0 0 1 D7 D6 D5 D4 D3 D2 D1 D0 002aae844 b. Read operations Fig 11. Device access examples Byte 15 contains device revision information stored in the EEPROM. It is set at the wafer production facility and cannot be changed in the field, so any write to this byte will be ignored but acknowledged. The value of this byte is 10h. The memory map for the Access Protection Page is shown in Table 5 “APP memory map”. In this table, an ‘X’ means that the value is a ‘Don’t care’ upon writing, and that it is undefined upon reading. The PB fields are all 2 bits wide, and the Device Revision field is 8 bits wide. All other fields are 1 bit wide. With the exception of the 9 Sticky Bits (SB), the two coil detect bits (DE and DC), the tamper bit (TAMPER), and bytes 14 and 15, all bits within the Access Protection Page are stored in EEPROM memory. Their state does not change if power is removed or when the PROT pin is held LOW. The following page of memory (accessed with A4 = 1) emulate the ID field that would be transmitted by the device from the RFID port. Bytes within it are accessed with the address byte at B8h or B9h (write/read). Reading and writing to this page is permitted when PBAP is 11. PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 12 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection Table 5. APP memory map X = ‘Don’t care’ upon writing and undefined upon reading. Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Bit 7 SB0 SB1 SB2 SB3 SB4 SB5 SB6 SB7 SBAP WPN7 DE Bit 6 X X X X X X X X X WPN6 DC X WPN5 X Bit 5 RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 X WPN4 X Bit 4 Bit 3 X X X X X X X X X WPN3 X Bit 2 X X X X X X X X X WPN2 X X WPN1 Bit 1 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PBAP WPN0 TAMPER Bit 0 reserved; R/W reserved; R/W reserved; R/W reserved; read-only device revision 6.5 PROT pin The PROT pin is used as a power good signal. When this pin is held LOW, the serial port is held in reset and all sticky bits are set to one. When HIGH, activity on the serial bus is permitted and sticky bits can be set to their values. 6.6 Serial EEPROM exceptions In general, the two-wire serial interface on the PCA24S08A functions identically to the 24C08. The following exceptions exist, as noted elsewhere in this document. • Pins 1, 2, and 3 have different usage. • Access to various blocks may be restricted via the access protection circuitry. • The two block address bits (B2 and B1) in the command byte are ignored with all read commands. They are set only via the write command. • Multi-byte reads do not cross block boundaries, but instead wrap to the beginning of the block. • The serial port will be reset whenever the PROT pin is LOW. • If more than 16 bytes are written to the EEPROM with a page write, overlapping bytes will have their values corrupted. • If VDD is 0 V, the device draws current on the SDA, SCL, WP, and PROT pins when they are brought above 0 V. PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 13 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 7. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Functional operation under these conditions is not implied. Symbol VDD VI Tstg Tamb Parameter supply voltage input voltage storage temperature ambient temperature Conditions with respect to ground SDA, SCL, PROT, WP pins Min −0.1 to VDD −55 −40 Max 4.6 +0.3 +125 +85 Unit V V °C °C 8. Static characteristics Table 7. Static characteristics VDD = 2.5 V to 3.6 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol VDD IDD Parameter supply voltage supply current VDD = 3.6 V; fSCL = 100 kHz EEPROM read EEPROM write Istb II/O II VIL VIH VOL Ci Cio standby current input/output current input current LOW-level input voltage HIGH-level input voltage LOW-level output voltage input capacitance input/output capacitance IOL = 2.1 mA SCL, PROT, WP not tested SDA not tested VDD = 3.6 V; SDA, SCL = VSS PROT, SDA, SCL pins; VI = VDD or VSS WP pin; VI = VDD = 5.5 V −0.1 VDD × 0.7 50 0.325 11.4 0.25 100 1.0 18 3.0 20 VDD × 0.3 VDD 0.4 6 8 μA mA μA μA μA V V V pF pF Conditions Min 2.5 Typ Max 3.6 Unit V PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 14 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 9. Dynamic characteristics Table 8. Dynamic characteristics CL = 1 TTL gate and 100 pF, except as noted. VDD = 2.5 V to 3.6 V. Symbol Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tVD;ACK tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data valid acknowledge time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF. [1] Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] Max 400 600 600 600 300 300 50 Unit Max 100 600 600 1500 300 1000 50 0 4.7 4.0 4.7 4.0 0 250 4.7 4.0 LOW level HIGH level [2] [2] kHz μs μs μs μs ns ns ns ns ns μs μs ns ns ns [1] [2] [3] SDA tBUF tLOW SCL tr tf tHD;STA tSP tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P 002aaa986 Fig 12. Timing diagram for serial interface PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 15 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 10. EEPROM memory Table 9. Parameter data retention at operating temperature endurance per byte EEPROM memory specifications Specification 10 years (minimum) 100,000 cycles (minimum) PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 16 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 11. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 A1 pin 1 index (A 3) θ Lp L A 1 4 e bp wM detail X 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ o 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 13. Package outline SOT96-1 (SO8) PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 17 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 D E A X c y HE vMA Z 8 5 A2 pin 1 index A1 (A3) A θ Lp L 1 e bp 4 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 θ 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 Fig 14. Package outline SOT505-1 (TSSOP8) PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 18 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 12.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 19 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 11. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15. PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 20 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 15. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13. Abbreviations Table 12. Acronym ACK APP CDM CMOS E/W EEPROM ESD HBM I2C-bus I/O LSB MM MSB NACK PB RF RFID SB Abbreviations Description Acknowledge Access Protection Page Charged-Device Model Complementary Metal-Oxide Semiconductor Erase/Write Electrically Erasable Programmable Read-Only Memory ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Input/Output Least Significant Bit Machine Model Most Significant Bit Not Acknowledge Protection Bit Radio Frequency Radio Frequency Identification Sticky Bit PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 21 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 14. Revision history Table 13. Revision history Release date 20100119 Data sheet status Product data sheet Change notice Supersedes Document ID PCA24S08A_1 PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 22 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 15. Legal information 15.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA24S08A_1 © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 01 — 19 January 2010 23 of 24 NXP Semiconductors PCA24S08A 1024 × 8-bit CMOS EEPROM with access protection 17. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.3 6.4 6.4.1 6.4.2 6.4.2.1 6.4.2.2 6.5 6.6 7 8 9 10 11 12 12.1 12.2 12.3 12.4 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Device addressing . . . . . . . . . . . . . . . . . . . . . . 4 Write operations . . . . . . . . . . . . . . . . . . . . . . . . 4 Byte/word write . . . . . . . . . . . . . . . . . . . . . . . . . 4 Page write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Read operations . . . . . . . . . . . . . . . . . . . . . . . . 7 Access protection . . . . . . . . . . . . . . . . . . . . . . . 8 RFID access fields (RF) . . . . . . . . . . . . . . . . . . 8 Protection bits (PB). . . . . . . . . . . . . . . . . . . . . . 8 Block 0 write protection bits . . . . . . . . . . . . . . 10 Access Protection Page (APP) . . . . . . . . . . . . 11 PROT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial EEPROM exceptions . . . . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 15 EEPROM memory . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering of SMD packages . . . . . . . . . . . . . . 19 Introduction to soldering . . . . . . . . . . . . . . . . . 19 Wave and reflow soldering . . . . . . . . . . . . . . . 19 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 19 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 20 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 22 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Contact information. . . . . . . . . . . . . . . . . . . . . 23 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 January 2010 Document identifier: PCA24S08A_1