PCA6408A
Low-voltage, 8-bit I2C-bus and SMBus I/O expander with
interrupt output, reset, and configuration registers
Rev. 1 — 27 September 2012
Product data sheet
1. General description
The PCA6408A is an 8-bit general purpose I/O expander that provides remote I/O
expansion for most microcontroller families via the I2C-bus interface.
NXP I/O expanders provide a simple solution when additional I/Os are needed while
keeping interconnections to a minimum, for example, in battery-powered mobile
applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing
a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage
level to I/O devices operating at a different (usually higher) voltage level. The PCA6408A
has built-in level shifting feature that makes these devices extremely flexible in mixed
signal environments where communication between incompatible I/O voltages is required.
Its wide VDD range of 1.65 V to 5.5 V on the dual power rail allows seamless
communications with next-generation low voltage microprocessors and microcontrollers
on the interface side (SDA/SCL) and peripherals at a higher voltage on the port side.
There are two supply voltages for PCA6408A: VDD(I2C-bus) and VDD(P). VDD(I2C-bus)
provides the supply voltage for the interface at the master side (for example, a
microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The
bidirectional voltage level translation in the PCA6408A is provided through VDD(I2C-bus).
VDD(I2C-bus) should be connected to the VDD of the external SCL/SDA lines. This indicates
the VDD level of the I2C-bus to the PCA6408A. The voltage level on Port P of the
PCA6408A is determined by the VDD(P).
The PCA6408A consists of one 8-bit Configuration (input or output selection), Input,
Output, and Polarity Inversion (active HIGH) register. At power-on, the I/Os are configured
as inputs. However, the system master can enable the I/Os as either inputs or outputs by
writing to the I/O configuration bits. The data for each input or output is kept in the
corresponding Input or Output register. The polarity of the Input port register can be
inverted with the Polarity Inversion register, saving interrupts.
The system master can reset the PCA6408A in the event of a time-out or other improper
operation by asserting a LOW in the RESET input. The power-on reset puts the registers
in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin
causes the same reset/initialization to occur without de-powering the part.
The PCA6408A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the PCA6408A can
remain a simple slave device.
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
The device Port P outputs have 25 mA sink capabilities for directly driving LEDs while
consuming low device current.
One hardware pin (ADDR) can be used to program and vary the fixed I2C-bus address
and allow up to two devices to share the same I2C-bus or SMBus.
2. Features and benefits
I2C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Allows bidirectional voltage-level translation and GPIO expansion between:
1.8 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
2.5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
3.3 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
5 V SCL/SDA and 1.8 V, 2.5 V, 3.3 V or 5 V Port P
Low standby current consumption of 1 A
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
Vhys = 0.18 V (typical) at 1.8 V
Vhys = 0.25 V (typical) at 2.5 V
Vhys = 0.33 V (typical) at 3.3 V
Vhys = 0.5 V (typical) at 5 V
5 V tolerant I/O ports
Active LOW reset input (RESET)
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I2C-bus
Input/Output Configuration register
Polarity Inversion register
Internal power-on reset
Power-up with all channels configured as inputs
No glitch on power-up
Noise filter on SCL/SDA inputs
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD 78, Class II
ESD protection exceeds JESD 22
2000 V Human-Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: HVQFN16, TSSOP16, XQFN16
PCA6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 September 2012
© NXP B.V. 2012. All rights reserved.
2 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
3. Ordering information
Table 1.
Ordering information
Type number
Topside
mark
Package
Name
Description
Version
PCA6408ABS
P8A
HVQFN16
plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3 3 0.85 mm
SOT758-1
PCA6408APW
PA6408A
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA6408AHK
P8
XQFN16
plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 2.60 0.50 mm
SOT1161-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
Minimum
order quantity
Temperature
PCA6408ABS
PCA6408ABSHP
HVQFN16
Reel pack, SMD,
13-inch, Turned
6000
Tamb = 40 C to +85 C
PCA6408APW
PCA6408APW,118
TSSOP16
Reel pack, SMD,
13-inch
2500
Tamb = 40 C to +85 C
PCA6408AHK
PCA6408AHKX
XQFN16
Reel pack, SMD
4000
Tamb = 40 C to +85 C
4. Block diagram
PCA6408A
INT
INTERRUPT
LOGIC
LP FILTER
ADDR
SCL
SDA
INPUT
FILTER
I2C-BUS
CONTROL
VDD(I2C-bus)
VDD(P)
RESET
SHIFT
REGISTER
8 BITS
I/O
PORT
P0 to P7
write pulse
read pulse
POWER-ON
RESET
VSS
002aaf823
All I/Os are set to inputs at reset.
Fig 1.
PCA6408A
Product data sheet
Block diagram (positive logic)
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© NXP B.V. 2012. All rights reserved.
3 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
5. Pinning information
13 SDA
2
15 SDA
P0
3
14 SCL
P1
3
10 P7
P0
4
13 INT
P1
5
P2
4
9
P2
6
11 P6
8
P3
7
10 P5
P5
11 INT
ADDR
RESET
7
2
12 SCL
P4
1
6
RESET
VSS
8
VSS
16 VDD(P)
5
1
P3
VDD(I2C-bus)
14 VDD(P)
terminal 1
index area
15 VDD(I2C-bus)
16 ADDR
5.1 Pinning
PCA6408APW
PCA6408ABS
12 P7
9
P4
P6
002aaf830
Transparent top view
002aaf821
The exposed center pad, if used, must be
connected only as a secondary VSS or
must be left electrically open.
Pin configuration for HVQFN16
13 SDA
14 VDD(P)
terminal 1
index area
Fig 3.
15 VDD(I2C-bus)
Pin configuration for TSSOP16
16 ADDR
Fig 2.
RESET 1
12 SCL
P0 2
11 INT
PCA6408AHK
P5 8
9 P6
P4 7
P2 4
VSS 6
10 P7
P3 5
P1 3
002aaf822
Transparent top view
Fig 4.
PCA6408A
Product data sheet
Pin configuration for XQFN16
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Rev. 1 — 27 September 2012
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4 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
5.2 Pin description
Table 3.
Symbol
Pin description
Pin
Description
TSSOP16 HVQFN16 XQFN16
VDD(I2C-bus)
1
15
15
Supply voltage of I2C-bus. Connect directly to
the VDD of the external I2C master. Provides
voltage-level translation.
ADDR
2
16
16
Address input. Connect directly to VDD(P) or
ground.
RESET
3
1
1
Active LOW reset input. Connect to VDD(I2C-bus)
through a pull-up resistor if no active connection
is used.
P0[1]
4
2
2
Port P input/output 0.
P1[1]
5
3
3
Port P input/output 1.
P2[1]
6
4
4
Port P input/output 2.
P3[1]
7
5
5
Port P input/output 3.
VSS
8
6
6
Ground.
P4[1]
9
7
7
Port P input/output 4.
P5[1]
10
8
8
Port P input/output 5.
P6[1]
11
9
9
Port P input/output 6.
P7[1]
12
10
10
Port P input/output 7.
INT
13
11
11
Interrupt output. Connect to VDD(I2C-bus) through
a pull-up resistor.
SCL
14
12
12
Serial clock bus. Connect to VDD(I2C-bus) through
a pull-up resistor.
SDA
15
13
13
Serial data bus. Connect to VDD(I2C-bus) through
a pull-up resistor.
VDD(P)
16
14
14
Supply voltage of PCA6408A for Port P.
[1]
PCA6408A
Product data sheet
All I/O are configured as input at power-on.
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PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
6. Voltage translation
Table 4 shows how to set up VDD levels for the necessary voltage translation between the
I2C-bus and the PCA6408A.
Table 4.
Voltage translation
VDD(I2C-bus) (SDA and SCL of I2C master)
VDD(P) (Port P)
1.8 V
1.8 V
1.8 V
2.5 V
1.8 V
3.3 V
1.8 V
5V
2.5 V
1.8 V
2.5 V
2.5 V
2.5 V
3.3 V
2.5 V
5V
3.3 V
1.8 V
3.3 V
2.5 V
3.3 V
3.3 V
3.3 V
5V
5V
1.8 V
5V
2.5 V
5V
3.3 V
5V
5V
7. Functional description
Refer to Figure 1 “Block diagram (positive logic)”.
7.1 Device address
The address of the PCA6408A is shown in Figure 5.
slave address
0
1
0
0
0
0
fixed
AD
R/W
DR
programmable
002aaf539
Fig 5.
PCA6408A address
ADDR is the hardware address package pin and is held to either HIGH (logic 1) or LOW
(logic 0) to assign one of the two possible slave addresses. The last bit of the slave
address defines the operation (read or write) to be performed. A HIGH (logic 1) selects a
read operation, while a LOW (logic 0) selects a write operation.
PCA6408A
Product data sheet
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Rev. 1 — 27 September 2012
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6 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
7.2 Interface definition
Table 5.
Interface definition
Byte
Bit
I2C-bus
slave address
I/O data bus
7 (MSB)
6
5
4
3
2
1
0 (LSB)
L
H
L
L
L
L
ADDR
R/W
P7
P6
P5
P4
P3
P2
P1
P0
7.3 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA6408A. Two bits of this
data byte state the operation (read or write) and the internal registers (Input, Output,
Polarity Inversion, or Configuration) that will be affected. This register is write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 6.
Table 6.
Pointer register bits
Command byte
Pointer register bits
Command byte Register
(hexadecimal)
Protocol
Power-up
default
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
00h
Input port
read byte
xxxx xxxx[1]
0
0
0
0
0
0
0
1
01h
Output port
read/write byte
1111 1111
0
0
0
0
0
0
1
0
02h
Polarity Inversion
read/write byte
0000 0000
0
0
0
0
0
0
1
1
03h
Configuration
read/write byte
1111 1111
[1]
Undefined.
PCA6408A
Product data sheet
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PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
7.4 Register descriptions
7.4.1 Input port register (00h)
The Input port register (register 0) reflects the incoming logic levels of the pins, regardless
of whether the pin is defined as an input or an output by the Configuration register. The
Input port register is read only; writes to this register have no effect. The default value ‘X’
is determined by the externally applied logic level. An Input port register read operation is
performed as described in Section 8.2 “Read commands”.
Table 7.
Input port register (address 00h)
Bit
7
6
5
4
3
2
1
0
Symbol
I7
I6
I5
I4
I3
I2
I1
I0
Default
X
X
X
X
X
X
X
X
7.4.2 Output port register (01h)
The Output port register (register 1) shows the outgoing logic levels of the pins defined as
outputs by the Configuration register. Bit values in these registers have no effect on pins
defined as inputs. In turn, reads from this register reflect the value that was written to this
register, not the actual pin value.
Table 8.
Bit
Output port register (address 01h)
7
6
5
4
3
2
1
0
Symbol
O7
O6
O5
O4
O3
O2
O1
O0
Default
1
1
1
1
1
1
1
1
7.4.3 Polarity inversion register (02h)
The Polarity inversion register (register 2) allows polarity inversion of pins defined as
inputs by the Configuration register. If a bit in this register is set (written with ‘1’), the
corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with a
‘0’), the corresponding port pin’s original polarity is retained.
Table 9.
Bit
Register 2: Polarity inversion register (address 02h)
7
6
5
4
3
2
1
0
Symbol
N7
N6
N5
N4
N3
N2
N1
N0
Default
0
0
0
0
0
0
0
0
7.4.4 Configuration register (03h)
The Configuration register (register 3) configures the direction of the I/O pins. If a bit in this
register is set to 1, the corresponding port pin is enabled as a high-impedance input. If a
bit in this register is cleared to 0, the corresponding port pin is enabled as an output.
Table 10.
Bit
PCA6408A
Product data sheet
Register 3: Configuration register (address 03h)
7
6
5
4
3
2
1
0
Symbol
C7
C6
C5
C4
C3
C2
C1
C0
Default
1
1
1
1
1
1
1
1
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PCA6408A
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
7.5 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD(P) or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
shift register
data from
shift register
output port
register data
configuration
register
D
VDD(P)
Q1
Q
FF
write
configuration
pulse
write pulse
CK
Q
D
Q
FF
P0 to P7
Q2
CK
output port
register
input port
register
D
Q
FF
read pulse
ESD
protection
diode
VSS
input port
register data
CK
to INT
polarity
inversion
register
data from
shift register
D
Q
FF
write polarity
pulse
polarity
inversion
register data
CK
002aaf824
On power-up or reset, all registers return to default values.
Fig 7.
PCA6408A
Product data sheet
Simplified schematic of P0 to P7
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PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
7.6 Power-on reset
When power (from 0 V) is applied to VDD(P), an internal power-on reset holds the
PCA6408A in a reset condition until VDD(P) has reached VPOR. At that time, the reset
condition is released and the PCA6408A registers and I2C-bus/SMBus state machine
initialize to their default states. After that, VDD(P) must be lowered to below VPORF and
back up to the operating voltage for a power-reset cycle. See Section 9.2 “Power-on reset
requirements”.
7.7 Reset input (RESET)
The RESET input can be asserted to initialize the system while keeping the VDD(P) at its
operating level. A reset can be accomplished by holding the RESET pin LOW for a
minimum of tw(rst). The PCA6408A registers and I2C-bus/SMBus state machine are
changed to their default state once RESET is LOW (0). When RESET is HIGH (1), the I/O
levels at the P port can be changed externally or through the master. This input requires a
pull-up resistor to VDD(I2C-bus) if no active connection is used.
7.8 Interrupt output (INT)
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. Resetting the interrupt circuit is achieved when
data on the port is changed to the original setting or when data is read from the port that
generated the interrupt (see Figure 11). Resetting occurs in the Read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the resetting of the interrupt during this pulse. Each change of the I/Os after
resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input port register.
The INT output has an open-drain structure and requires a pull-up resistor to VDD(P) or
VDD(I2C-bus) depending on the application. INT should be connected to the voltage source
of the device that requires the interrupt information.
PCA6408A
Product data sheet
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PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
8. Bus transactions
The PCA6408A is an I2C-bus slave device. Data is exchanged between the master and
PCA6408A through write and read commands using I2C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Write commands
Data is transmitted to the PCA6408A by sending the device address and setting the Least
Significant Bit (LSB) to a logic 0 (see Figure 5 for device address). The command byte is
sent after the address and determines which register receives the data that follows the
command byte. There is no limitation on the number of data bytes sent in one write
transmission.
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
1
0
0
0
AD
0
0 DR 0
START condition
A
R/W
0
0
0
0
0
STOP
condition
data to port
command byte
0
0
acknowledge
from slave
1
A
DATA 1
A
P
acknowledge
from slave
acknowledge
from slave
write to port
tv(Q)
data out from port
DATA 1 VALID
002aaf825
Fig 8.
Write to Output port register
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
0
1
0
0
START condition
0
AD
0 DR 0
R/W
A
0
0
0
0
0
0
acknowledge
from slave
STOP
condition
data to register
command byte
1 1/0 A
acknowledge
from slave
DATA 1
A
P
acknowledge
from slave
002aaf826
Fig 9.
Write to Configuration or Polarity inversion registers
PCA6408A
Product data sheet
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PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
8.2 Read commands
To read data from the PCA6408A, the bus master must first send the PCA6408A address
with the least significant bit set to a logic 0 (see Figure 5 for device address). The
command byte is sent after the address and determines which register is to be accessed.
After a restart the device address is sent again, but this time the LSB is set to a logic 1.
Data from the register defined by the command byte then is sent by the PCA6408A (see
Figure 10 and Figure 11).
Data is clocked into the register on the rising edge of the ACK clock pulse. There is no
limit on the number of data bytes received in one read transmission, but on the final byte
received the bus master must not acknowledge the data.
slave address
SDA S
0
1
0
0
0
command byte
AD
DR
0
START condition
0
A
0
0
0
0
R/W
slave address
0
1
0
0
0
(repeated)
START condition
0
1 1/0 A
(cont.)
acknowledge
from slave
acknowledge
from slave
(cont.) S
0
data from register
0 AD 1
A
DR
DATA (first byte)
R/W
data from register
A
DATA (last byte)
acknowledge
from master
acknowledge
from slave
NA P
STOP
condition
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
002aaf827
Fig 10. Read from register
SCL
1
2
3
4
5
6
7
8
9
slave address
SDA S
0
1
0
0
0
START condition
data from port
0
AD
DR
1
R/W
DATA 1
A
data from port
A
acknowledge from slave
DATA 4
acknowledge from master
read from
port
data into
port
DATA 1
DATA 2
th(D)
DATA 3
tsu(D)
INT
tv(INT)
trst(INT)
DATA 4
no acknowledge
from master
1
P
STOP
condition
DATA 5
INT is cleared by
read from port
STOP not needed
to clear INT
002aaf828
Transfer of data can be stopped at any time by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been programmed with 00h (read Input port
register).
This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and
actual data transfer from P port (see Figure 10).
Fig 11. Read Input port register
PCA6408A
Product data sheet
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PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
9. Application design-in information
VDD(I2C-bus) VDD(P)
VDD(I2C-bus) = 1.8 V
10 kΩ
10 kΩ
VDD
10 kΩ
10 kΩ
10 kΩ (× 3)
VDD(I2C-bus) VDD(P)
MASTER
CONTROLLER
SCL
SDA
INT
RESET
P0
SCL
SDA
SUBSYSTEM 1
(e.g., alarm system)
A
INT
RESET
VSS
ALARM(1)
P1
controlled
switch
enable
B
PCA6408A
P2
P3
ADDR
P4
P5
KEYPAD
P6
VSS
P7
002aaf829
Device address configured as 0100 000x for this example.
P0 and P2 through P4 are configured as inputs.
P1 and P5 through P7 are configured as outputs.
(1) Resistors are required for inputs (on P port) that may float. If a driver to an input will never let the
input float, a resistor is not needed. Outputs (in the P port) do not need pull-up resistors.
Fig 12. Typical application
9.1 Minimizing IDD when I/Os control LEDs
When the I/Os are used to control LEDs, normally they are connected to VDD(P) through a
resistor as shown in Figure 12. The LED acts as a diode, so when the LED is off, the I/O
VI is about 1.2 V less than VDD(P). The IDD parameter in Table 15 “Static characteristics”
shows how IDD(P) increases as VI becomes lower than VDD(P). Designs that must minimize
current consumption, such as battery power applications, should consider maintaining the
I/O pins greater than or equal to VDD(P) when the LED is off.
Figure 13 shows a high-value resistor in parallel with the LED. Figure 14 shows VDD(P)
less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O
VI at or above VDD(P) and prevent additional supply current consumption when the LED
is off.
PCA6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 September 2012
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13 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
3.3 V
VDD
VDD(P)
LED
5V
VDD(P)
100 kΩ
LED
Pn
Pn
002aah278
002aah279
Fig 13. High-value resistor in parallel
with the LED
Fig 14. Device supplied by a lower voltage
9.2 Power-on reset requirements
In the event of a glitch or data corruption, PCA6408A can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
The two types of power-on reset are shown in Figure 15 and Figure 16.
VDD(P)
ramp-up
ramp-down
re-ramp-up
td(rst)
time
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD(P) drops
below 0.2 V or to VSS
(dV/dt)r
002aag960
Fig 15. VDD(P) is lowered below 0.2 V or 0 V and then ramped up to VDD(P)
VDD(P)
ramp-down
ramp-up
td(rst)
VI drops below POR levels
(dV/dt)f
time to re-ramp
when VDD(P) drops
to VPOR(min) − 50 mV
time
(dV/dt)r
002aag961
Fig 16. VDD(P) is lowered below the POR threshold, then ramped back up to VDD(P)
Table 11 specifies the performance of the power-on reset feature for PCA6408A for both
types of power-on reset.
PCA6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 September 2012
© NXP B.V. 2012. All rights reserved.
14 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
Table 11. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 15
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 15
0.1
-
2000
ms
td(rst)
reset delay time
Figure 15; re-ramp time when
VDD(P) drops to VSS
1
-
-
s
Figure 16; re-ramp time when
VDD(P) drops to VPOR(min) 50 mV
1
-
-
s
VDD(gl)
glitch supply voltage difference
Figure 17
[1]
-
-
1.0
V
[2]
-
-
10
s
tw(gl)VDD
supply voltage glitch pulse width
Figure 17
VPOR(trip)
power-on reset trip voltage
falling VDD(P)
0.7
-
-
V
rising VDD(P)
-
-
1.4
V
[1]
Level that VDD(P) can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2]
Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD(P).
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 17 and Table 11 provide more information on
how to measure these specifications.
VDD(P)
∆VDD(gl)
tw(gl)VDD
time
002aag962
Fig 17. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD(P) being lowered to or from
0 V. Figure 18 and Table 11 provide more details on this specification.
VDD(P)
VPOR (rising VDD(P))
VPOR (falling VDD(P))
time
POR
time
002aag963
Fig 18. Power-on reset voltage (VPOR)
PCA6408A
Product data sheet
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Rev. 1 — 27 September 2012
© NXP B.V. 2012. All rights reserved.
15 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
10. Limiting values
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD(I2C-bus)
I2C-bus
Conditions
Min
Max
Unit
0.5
+6.5
V
VDD(P)
supply voltage port P
VI
input voltage
[1]
0.5
+6.5
V
0.5
+6.5
VO
output voltage
[1]
V
0.5
+6.5
V
IIK
input clamping current
ADDR, RESET, SCL; VI < 0 V
-
20
mA
IOK
IIOK
output clamping current
INT; VO < 0 V
-
20
mA
input/output clamping current
P port; VO < 0 V or VO > VDD(P)
-
20
mA
SDA; VO < 0 V or VO > VDD(I2C-bus)
-
20
mA
supply voltage
IOL
LOW-level output current
continuous; P port; VO = 0 V to VDD(P)
-
50
mA
continuous; SDA, INT; VO = 0 V to VDD(I2C-bus)
-
25
mA
IOH
HIGH-level output current
continuous; P port; VO = 0 V to VDD(P)
-
25
mA
IDD
supply current
continuous through VSS
-
200
mA
IDD(P)
supply current port P
continuous through VDD(P)
-
160
mA
IDD(I2C-bus)
I2C-bus
continuous through VDD(I2C-bus)
-
10
mA
Tstg
storage temperature
65
+150
C
Tj(max)
maximum junction temperature
-
125
C
[1]
supply current
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
11. Recommended operating conditions
Table 13.
Operating conditions
Symbol
Parameter
VDD(I2C-bus)
I2C-bus
VDD(P)
supply voltage port P
VIH
HIGH-level input voltage
Conditions
supply voltage
Min
Max
Unit
1.65
5.5
V
1.65
5.5
V
SCL, SDA, RESET
0.7 VDD(I2C-bus)
5.5
V
ADDR, P7 to P0
0.7 VDD(P)
5.5
V
0.5
0.3 VDD(I2C-bus)
V
VIL
LOW-level input voltage
SCL, SDA, RESET
ADDR, P7 to P0
0.5
0.3 VDD(P)
V
IOH
HIGH-level output current
P7 to P0
-
10
mA
IOL
LOW-level output current
P7 to P0
-
25
mA
Tamb
ambient temperature
operating in free air
40
+85
C
PCA6408A
Product data sheet
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16 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
12. Thermal characteristics
Table 14.
Symbol
Zth(j-a)
Thermal characteristics
Parameter
Conditions
transient thermal impedance from junction to ambient
[1]
Max
Unit
TSSOP16 package
[1]
108
K/W
HVQFN16 package
[1]
53
K/W
XQFN16 package
[1]
184
K/W
The package thermal impedance is calculated in accordance with JESD 51-7.
13. Static characteristics
Table 15. Static characteristics
Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1] Max
Unit
VIK
input clamping voltage
II = 18 mA
1.2
-
-
V
VPOR
power-on reset voltage
VI = VDD(P) or VSS; IO = 0 mA
-
1.1
1.4
V
VOH
HIGH-level output
voltage
P port
VOL
IOL
LOW-level
output voltage
LOW-level
output current
IOH = 8 mA; VDD(P) = 1.65 V
[2]
1.2
-
-
V
IOH = 10 mA; VDD(P) = 1.65 V
[2]
1.1
-
-
V
IOH = 8 mA; VDD(P) = 2.3 V
[2]
1.8
-
-
V
IOH = 10 mA; VDD(P) = 2.3 V
[2]
1.7
-
-
V
IOH = 8 mA; VDD(P) = 3.0 V
[2]
2.6
-
-
V
IOH = 10 mA; VDD(P) = 3.0 V
[2]
2.5
-
-
V
IOH = 8 mA; VDD(P) = 4.5 V
[2]
4.1
-
-
V
IOH = 10 mA; VDD(P) = 4.5 V
[2]
4.0
-
-
V
VDD(P) = 1.65 V
[2]
-
-
0.45
V
VDD(P) = 2.3 V
[2]
-
-
0.25
V
VDD(P) = 3 V
[2]
-
-
0.25
V
VDD(P) = 4.5 V
[2]
-
-
0.2
V
SDA
[3]
3
-
-
mA
INT
[3]
3
15[4]
-
mA
VOL = 0.5 V; VDD(P) = 1.65 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD(P) = 1.65 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD(P) = 2.3 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD(P) = 2.3 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD(P) = 3.0 V
[3]
8
14
-
mA
VOL = 0.7 V; VDD(P) = 3.0 V
[3]
10
19
-
mA
VOL = 0.5 V; VDD(P) = 4.5 V
[3]
8
17
-
mA
VOL = 0.7 V; VDD(P) = 4.5 V
[3]
10
24
-
mA
P port; IOL = 8 mA
VOL = 0.4 V; VDD(P) = 1.65 V to 5.5 V
P port
PCA6408A
Product data sheet
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© NXP B.V. 2012. All rights reserved.
17 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
Table 15. Static characteristics …continued
Tamb = 40 C to +85 C; VDD(I2C-bus) = 1.65 V to 5.5 V; unless otherwise specified.
Min
Typ[1] Max
SCL, SDA, RESET; VI = VDD(I2C-bus) or VSS
-
-
1
ADDR; VI = VDD(P) or VSS
Symbol
Parameter
Conditions
II
input current
VDD(P) = 1.65 V to 5.5 V
Unit
A
-
-
1
A
IIH
HIGH-level input current P port; VI = VDD(P); VDD(P) = 1.65 V to 5.5 V
-
-
1
A
IIL
LOW-level input current
P port; VI = VSS; VDD(P) = 1.65 V to 5.5 V
-
-
1
A
IDD
supply current
IDD(I2C-bus) + IDD(P);
SDA, P port, ADDR, RESET;
VI on SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port and ADDR = VDD(P);
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
VDD(P) = 3.6 V to 5.5 V
-
10
25
A
VDD(P) = 2.3 V to 3.6 V
-
6.5
15
A
VDD(P) = 1.65 V to 2.3 V
-
4
9
A
IDD(I2C-bus) + IDD(P);
SCL, SDA, P port, ADDR, RESET;
VI on SCL, SDA and RESET = VDD(I2C-bus) or VSS;
VI on P port and ADDR = VDD(P);
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
VDD(P) = 3.6 V to 5.5 V
-
1.5
7
A
VDD(P) = 2.3 V to 3.6 V
-
1
3.2
A
VDD(P) = 1.65 V to 2.3 V
-
0.5
1.7
A
VDD(P) = 3.6 V to 5.5 V
-
60
125
A
VDD(P) = 2.3 V to 3.6 V
-
40
75
A
VDD(P) = 1.65 V to 2.3 V
-
20
45
A
SCL, SDA, RESET;
one input at VDD(I2C-bus) 0.6 V,
other inputs at VDD(I2C-bus) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
-
25
A
P port, ADDR; one input at VDD(P) 0.6 V,
other inputs at VDD(P) or VSS;
VDD(P) = 1.65 V to 5.5 V
-
-
80
A
VI = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
-
6
7
pF
-
7
8
pF
-
7.5
8.5
pF
Active mode; IDD(I2C-bus) + IDD(P);
P port, ADDR, RESET;
VI on RESET = VDD(I2C-bus);
VI on P port and ADDR = VDD(P);
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz, continuous register read
IDD
additional quiescent
supply current
Ci
input capacitance
Cio
input/output capacitance VI/O = VDD(I2C-bus) or VSS; VDD(P) = 1.65 V to 5.5 V
VI/O = VDD(P) or VSS; VDD(P) = 1.65 V to 5.5 V
[1]
For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the
typical values are at VDD(P) = VDD(I2C-bus) = 3.3 V and Tamb = 25 C.
[2]
The total current sourced by all I/Os must be limited to 80 mA.
[3]
Each I/O must be externally limited to a maximum of 25 mA, for a device total of 200 mA.
[4]
Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
PCA6408A
Product data sheet
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Rev. 1 — 27 September 2012
© NXP B.V. 2012. All rights reserved.
18 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
13.1 Typical characteristics
002aag973
20
002aag974
1400
IDD
(μA)
IDD(stb)
(nA)
16
VDD(P) = 5.5 V
5.0 V
3.6 V
12
3.3 V
2.5 V
2.3 V
8
VDD(P) = 5.5 V
5.0 V
3.6 V
3.3 V
1000
800
600
400
2.5 V
2.3 V
1.8 V
1.65 V
4
0
−40
200
VDD(P) = 1.8 V
1.65 V
−15
10
35
0
−40
60
85
Tamb (°C)
−15
10
35
60
85
Tamb (°C)
IDD = IDD(I2C-bus) + IDD(P)
Fig 19. Supply current versus ambient temperature
Fig 20. Standby supply current versus
ambient temperature
002aag975
20
IDD
(μA)
16
12
8
4
0
1.5
2.5
3.5
4.5
5.5
VDD(P) (V)
Tamb = 25 C
IDD = IDD(I2C-bus) + IDD(P)
Fig 21. Supply current versus supply voltage
PCA6408A
Product data sheet
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Rev. 1 — 27 September 2012
© NXP B.V. 2012. All rights reserved.
19 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
Isink
(mA)
002aaf578
35
Isink
(mA)
30
Tamb = −40 °C
25 °C
85 °C
25
002aaf579
35
30
Tamb = −40 °C
25 °C
85 °C
25
20
20
15
15
10
10
5
5
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
a. VDD(P) = 1.65 V
Isink
(mA)
b. VDD(P) = 1.8 V
002aaf580
50
002aaf581
60
Isink
(mA)
40
Tamb = −40 °C
25 °C
85 °C
30
0.3
VOL (V)
Tamb = −40 °C
25 °C
85 °C
40
20
20
10
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
c. VDD(P) = 2.5 V
Isink
(mA)
d. VDD(P) = 3.3 V
002aaf582
70
Isink
(mA)
Tamb = −40 °C
25 °C
85 °C
60
50
0.3
VOL (V)
002aaf583
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
40
30
30
20
20
10
10
0
0
0
0.1
0.2
0.3
0
0.1
VOL (V)
0.2
0.3
VOL (V)
e. VDD(P) = 5.0 V
f. VDD(P) = 5.5 V
Fig 22. I/O sink current versus LOW-level output voltage
PCA6408A
Product data sheet
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© NXP B.V. 2012. All rights reserved.
20 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
002aaf561
30
Isource
(mA)
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
20
002aaf562
35
Tamb = −40 °C
25 °C
85 °C
30
25
20
15
10
10
5
0
0
0
0.2
0.4
0.6
VDD(P) − VOH (V)
0
a. VDD(P) = 1.65 V
002aaf563
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
40
0.4
0.6
VDD(P) − VOH (V)
b. VDD(P) = 1.8 V
60
Isource
(mA)
0.2
002aaf564
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
30
20
20
10
0
0
0
0.2
0.4
0.6
VDD(P) − VOH (V)
c. VDD(P) = 2.5 V
002aaf565
0.4
0.6
VDD(P) − VOH (V)
002aaf566
90
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
60
0.2
d. VDD(P) = 3.3 V
90
Isource
(mA)
0
Tamb = −40 °C
25 °C
85 °C
60
30
30
0
0
0
0.2
0.4
0.6
VDD(P) − VOH (V)
e. VDD(P) = 5.0 V
0
0.2
0.4
0.6
VDD(P) − VOH (V)
f. VDD(P) = 5.5 V
Fig 23. I/O source current versus HIGH-level output voltage
PCA6408A
Product data sheet
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21 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
VOL
(mV)
002aah056
120
100
002aah057
200
VDD(P) − VOH (mV)
160
(1)
80
120
VDD(P) = 1.8 V
5V
60
(2)
80
40
(4)
20
0
−40
40
(3)
−15
10
35
60
85
Tamb (°C)
0
−40
−15
10
35
60
85
Tamb (°C)
Isource = 10 mA
(1) VDD(P) = 1.8 V; Isink = 10 mA
(2) VDD(P) = 5 V; Isink = 10 mA
(3) VDD(P) = 1.8 V; Isink = 1 mA
(4) VDD(P) = 5 V; Isink = 1 mA
Fig 24. LOW-level output voltage versus temperature
PCA6408A
Product data sheet
Fig 25. I/O high voltage versus temperature
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22 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
14. Dynamic characteristics
Table 16. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 26.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
s
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tSP
pulse width of spikes that must
be suppressed by the input filter
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
kHz
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20
(VDD / 5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4
-
0.6
-
s
tVD;DAT
data valid time
SCL LOW
to SDA output valid
-
3.45
-
0.9
s
tVD;ACK
data valid acknowledge time
ACK signal
from SCL LOW
to SDA (out) LOW
-
3.45
-
0.9
s
Table 17. Reset timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 29.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Min
Max
Min
Max
Unit
tw(rst)
reset pulse width
30
-
30
-
ns
trec(rst)
reset recovery time
200
-
200
-
ns
trst
reset time
600
-
600
-
ns
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
Table 18. Switching characteristics
Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 28.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Min
Max
Min
Max
Unit
tv(INT)
valid time on pin INT
from P port to INT
-
1
-
1
s
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns
15. Parameter measurement information
VDD(I2C-bus)
RL = 1 kΩ
DUT
SDA
CL = 50 pF
002aag977
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
ACK
(A)
Data
Bit 7
(MSB)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SCL
tBUF
tVD;DAT
tr
tf
tf(o)
tVD;ACK
tSU;STA
0.7 × VDD(I2C-bus)
SDA
tf
tHD;STA
tr
0.3 × VDD(I2C-bus)
tVD;ACK
tSU;DAT
tSU;STO
tHD;DAT
repeat START condition
STOP condition
002aag978
c. Voltage waveforms
CL includes probe and jig capacitance. tf(o) is measured with CL of 10 pF or 400 pF.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2 = Input register port data.
(1) See Figure 11.
Fig 26. I2C-bus interface load circuit and voltage waveforms
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
VDD(I2C-bus)
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
002aag979
a. Interrupt load configuration
acknowledge
from slave
START condition
R/W
8 bits (one data byte)
from port
slave address
SDA S
SCL
0
1
0
1
2
3
0
4
0
5
0 AD 1
DR
6
7
8
acknowledge
from slave
DATA 1
A
no acknowledge
from master
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
0.5 × VDD(I2C-bus)
SCL
DATA 2
R/W
0.3 × VDD(I2C-bus)
tv(INT)
trst(INT)
0.5 × VDD(P)
Pn
0.7 × VDD(I2C-bus)
A
0.5 × VDD(I2C-bus)
INT
View A - A
View B - B
002aag980
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 27. Interrupt load circuit and voltage waveforms
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
500 Ω
Pn
DUT
2 × VDD(P)
CL = 50 pF
500 Ω
002aag981
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag982
b. Write mode (R/W = 0)
SCL
P0
0.7 × VDD(I2C-bus)
0.3 × VDD(I2C-bus)
tsu(D)
th(D)
Pn
0.5 × VDD(P)
002aag983
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 28. P port load circuit and voltage waveforms
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
VDD(I2C-bus)
RL = 1 kΩ
SDA
DUT
500 Ω
Pn
DUT
CL = 50 pF
2 × VDD(P)
CL = 50 pF
500 Ω
002aag977
002aag981
a. SDA load configuration
b. P port load configuration
START
SCL
ACK or read cycle
SDA
0.3 × VDD(I2C-bus)
trst
RESET
0.5 × VDD(I2C-bus)
trec(rst)
tw(rst)
trec(rst)
trst
Pn
0.5 × VDD(P)
002aag984
c. RESET timing
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
I/Os are configured as inputs.
All parameters and waveforms are not applicable to all devices.
Fig 29. Reset load circuits and voltage waveforms
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
16. Package outline
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
MO-153
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
Fig 30. Package outline SOT403-1 (TSSOP16)
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
HVQFN16: plastic thermal enhanced very thin quad flat package; no leads;
16 terminals; body 3 x 3 x 0.85 mm
A
B
D
SOT758-1
terminal 1
index area
A
E
A1
c
detail X
e1
C
1/2
e
e
5
y
y1 C
v M C A B
w M C
b
8
L
4
9
e
e2
Eh
1/2
e
12
1
16
terminal 1
index area
13
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
3.1
2.9
1.75
1.45
3.1
2.9
1.75
1.45
0.5
1.5
1.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT758-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
02-03-25
02-10-21
Fig 31. Package outline SOT758-1 (HVQFN16)
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PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
XQFN16: plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 x 2.60 x 0.50 mm
SOT1161-1
X
A
B
D
terminal 1
index area
A
E
A1
A3
detail X
e1
e
5
8
C
C A B
C
v
w
b
y1 C
y
L
4
9
e
e2
1
12
terminal 1
index area
16
L1
13
0
1
scale
Dimensions
Unit(1)
mm
max
nom
min
2 mm
A
A1
0.5
0.05
A3
b
0.25
0.127 0.20
0.15
0.00
D
E
1.9
1.8
1.7
2.7
2.6
2.5
e
e1
0.4
1.2
L
e2
1.2
L1
0.45 0.55
0.40 0.50
0.35 0.45
v
0.1
w
y
y1
0.05 0.05 0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
References
Outline
version
IEC
JEDEC
JEITA
SOT1161-1
---
---
---
sot1161-1_po
European
projection
Issue date
09-12-28
09-12-29
Fig 32. Package outline SOT1161-1 (XQFN16)
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17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
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17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 33) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 19 and 20
Table 19.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 20.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 33.
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 33. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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18. Soldering: PCB footprints
Footprint information for reflow soldering of HVQFN16 package
SOT758-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
Hy
SPy tot
nSPx
Gy
SPy
nSPy
SLy
By
Ay
SPx tot
SLx
Bx
Ax
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
0.50
4.00
4.00
2.20
2.20
0.90
0.24
1.50
1.50
Issue date
SPx tot SPy tot
0.90
0.90
SPx
SPy
Gx
Gy
Hx
Hy
0.30
0.30
3.30
3.30
4.25
4.25
12-03-07
12-03-08
sot758-1_fr
Fig 34. PCB footprint for SOT758-1 (HVQFN16); reflow soldering
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
Footprint information for reflow soldering of TSSOP16 package
SOT403-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
5.600
5.300
5.800
7.450
sot403-1_fr
Fig 35. PCB footprint for SOT403-1 (TSSOP16); reflow soldering
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
Footprint information for reflow soldering of XQFN16 package
SOT1161-1
2.35
2.1 CU
1.65
0.4 (12×)
0.45
0.22
CU
(16×)
3.15
1.8
CU
1.65
2.9
CU
0.9
CU
1
CU
placement area
solder land plus solder paste
solder land
solder resist, 0.0625 around copper
solder paste deposit, −0.02 around copper,
stencil thickness 0.1
clearance, 0.125 around occupied area
occupied area
Dimensions in mm
sot1161-1_fr
Fig 36. PCB footprint for SOT1161-1 (XQFN16); reflow soldering
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Low-voltage, 8-bit I2C-bus and SMBus I/O expander
19. Abbreviations
Table 21.
Abbreviations
Acronym
Description
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
GPIO
General Purpose Input/Output
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light-Emitting Diode
LSB
Least Significant Bit
MSB
Most Significant Bit
PCB
Printed-Circuit Board
POR
Power-On Reset
SMBus
System Management Bus
20. Revision history
Table 22.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA6408A v.1
20120927
Product data sheet
-
-
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21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA6408A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 September 2012
© NXP B.V. 2012. All rights reserved.
38 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA6408A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 27 September 2012
© NXP B.V. 2012. All rights reserved.
39 of 40
PCA6408A
NXP Semiconductors
Low-voltage, 8-bit I2C-bus and SMBus I/O expander
23. Contents
1
2
3
3.1
4
5
5.1
5.2
6
7
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.5
7.6
7.7
7.8
8
8.1
8.2
9
9.1
9.2
10
11
12
13
13.1
14
15
16
17
17.1
17.2
17.3
17.4
18
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Voltage translation . . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 6
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interface definition . . . . . . . . . . . . . . . . . . . . . . 7
Pointer register and command byte . . . . . . . . . 7
Register descriptions . . . . . . . . . . . . . . . . . . . . 8
Input port register (00h) . . . . . . . . . . . . . . . . . . 8
Output port register (01h) . . . . . . . . . . . . . . . . . 8
Polarity inversion register (02h) . . . . . . . . . . . . 8
Configuration register (03h) . . . . . . . . . . . . . . . 8
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset input (RESET) . . . . . . . . . . . . . . . . . . . 10
Interrupt output (INT) . . . . . . . . . . . . . . . . . . . 10
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11
Write commands. . . . . . . . . . . . . . . . . . . . . . . 11
Read commands . . . . . . . . . . . . . . . . . . . . . . 12
Application design-in information . . . . . . . . . 13
Minimizing IDD when I/Os control LEDs . . . . . 13
Power-on reset requirements . . . . . . . . . . . . . 14
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16
Recommended operating conditions. . . . . . . 16
Thermal characteristics . . . . . . . . . . . . . . . . . 17
Static characteristics. . . . . . . . . . . . . . . . . . . . 17
Typical characteristics . . . . . . . . . . . . . . . . . . 19
Dynamic characteristics . . . . . . . . . . . . . . . . . 23
Parameter measurement information . . . . . . 24
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 28
Soldering of SMD packages . . . . . . . . . . . . . . 31
Introduction to soldering . . . . . . . . . . . . . . . . . 31
Wave and reflow soldering . . . . . . . . . . . . . . . 31
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 32
Soldering: PCB footprints. . . . . . . . . . . . . . . . 34
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 37
21
21.1
21.2
21.3
21.4
22
23
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
38
38
38
39
39
40
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2012.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 September 2012
Document identifier: PCA6408A
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