PCA85063A
Automotive tiny Real-Time Clock/calendar with alarm function
2
and I C-bus
Rev. 4.1 — 16 September 2021
1
Product data sheet
General description
1
The PCA85063A is a CMOS Real-Time Clock (RTC) and calendar optimized for low
power consumption. An offset register allows fine-tuning of the clock. All addresses and
2
data are transferred serially via the two-line bidirectional I C-bus. Maximum data rate is
400 kbit/s. The register address is incremented automatically after each written or read
data byte.
For a selection of NXP Real-Time Clocks, see Section 20.1.
2
Features and benefits
• AEC-Q100 grade 2 compliant for automotive applications
• High temperature operation range: -40 °C to +105 °C
• Provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768
kHz quartz crystal
• Clock operating voltage: 0.9 V to 5.5 V
• Low current; typical 0.25 μA at VDD = 3.0 V and Tamb = 25 °C
2
• 400 kHz two-line I C-bus interface
(at VDD = 1.8 V to 5.5 V)
• Programmable clock output for peripheral devices (32.768 kHz, 16.384 kHz, 8.192 kHz,
4.096 kHz, 2.048 kHz, 1.024 kHz, and 1 Hz)
• Selectable integrated oscillator load capacitors for CL = 7 pF or CL = 12.5 pF
• Alarm function
• Countdown timer
• Minute and half minute interrupt
• Oscillator stop detection function
• Internal Power-On Reset (POR)
• Programmable offset register for frequency adjustment
3
Applications
•
•
•
•
•
•
•
•
Tracking time of the day
Accurate timing
Dashboard
Infotainment unit
Air condition
Center stack
Telematics
Body control and battery management
1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
4
Ordering information
Table 1. Ordering information
Topside
Type number
mark
Package
063Q
PCA85063ATT/A
Name
Description
Version
TSSOP8
plastic thin shrink small outline package; 8
leads; body width 3 mm
SOT505-1
4.1 Ordering options
Table 2. Ordering options
Type number
PCA85063ATT/A
[1]
5
[1]
Orderable part
number
Package
Packing method
Minimum order
quantity
Temperature
PCA85063ATT/AJ
SOT505-1
REEL 13" Q1 NDP
2500
-40 °C to +105 °C
Not Recommended for New Design (NRND). NXP will continue to manufacture to support existing customers through typical 5 to 7 year platform lifespan.
PCA85073ADP/Q900 has identical performance specifications with improved package and is recommend for all new designs.
Block diagram
OSCO
OSCI
32 kHz
OSCILLATOR
DIVIDER
POWER-ON
RESET
CLOCK
CALIBRATION
OFFSET
VDD
SYSTEM
CONTROL
VSS
SDA
SCL
l2C-BUS
INTERFACE
CLOCK OUT
CLKOUT
INTERRUPT
CONTROL
INT
REAL-TIME
CLOCK
ALARM AND
TIMER
CONTROL
PCA85063A
aaa-013712
Figure 1. Block diagram of PCA85063A
PCA85063A
Product data sheet
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
6
Pinning information
6.1 Pinning
OSCI 1
OSCO 2
INT 3
8 VDD
PCA85063ATT
VSS 4
7 CLKOUT
6 SCL
5 SDA
aaa-013714
For mechanical details, see Figure 30.
Figure 2. Pin configuration for TSSOP8 (PCA85063ATT)
6.2 Pin description
Table 3. Pin description
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise
specified.
Symbol
Pin
Type
Description
PCA85063ATT
OSCI
1
input
oscillator input
OSCO
2
output
oscillator output
3
output
interrupt output (open-drain)
INT
[1]
VSS
4
supply
ground supply voltage
[1]
5
input/output
serial data line
[1]
6
input
serial clock input
CLKOUT
7
output
clock output (push-pull)
VDD
8
supply
supply voltage
SDA
SCL
[1]
7
NXP recommends tying VDD of the device and VDD of all the external pull-up resistors to the same Power Supply.
Functional description
The PCA85063A contains 18 8-bit registers with an auto-incrementing register address,
an on-chip 32.768 kHz oscillator with integrated capacitors, a frequency divider which
2
provides the source clock for the Real-Time Clock (RTC) and calender, and an I C-bus
interface with a maximum data rate of 400 kbit/s.
The built-in address register will increment automatically after each read or write of
a data byte up to the register 11h. After register 11h, the auto-incrementing will wrap
around to address 00h (see Figure 3).
PCA85063A
Product data sheet
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
address register
00h
01h
02h
auto-increment
03h
...
0Fh
10h
11h
wrap around
aaa-004431
Figure 3. Handling address registers
All registers (see Table 4) are designed as addressable 8-bit parallel registers although
not all bits are implemented. The first two registers (memory address 00h and 01h) are
used as control and status register. The register at address 02h is an offset register
allowing the fine-tuning of the clock; and at 03h is a free RAM byte. The addresses 04h
through 0Ah are used as counters for the clock function (seconds up to years counters).
Address locations 0Bh through 0Fh contain alarm registers which define the conditions
for an alarm. The registers at 10h and 11h are for the timer function.
The Seconds, Minutes, Hours, Days, Months, and Years as well as the corresponding
alarm registers are all coded in Binary Coded Decimal (BCD) format. When one of the
RTC registers is written or read, the contents of all time counters are frozen. Therefore,
faulty writing or reading of the clock and calendar during a carry condition is prevented.
For details on maximum access time, see Section 7.4.
PCA85063A
Product data sheet
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
7.1 Registers organization
Table 4. Registers overview
Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 7.
Address
Register name
Bit
Reference
7
6
5
4
3
2
1
0
12_24
CAP_SEL
Control and status registers
00h
Control_1
EXT_TEST
-
STOP
SR
-
CIE
01h
Control_2
AIE
AF
MI
HMI
TF
COF[2:0]
02h
Offset
MODE
OFFSET[6:0]
03h
RAM_byte
B[7:0]
Section 7.2.1
Section 7.2.2
Section 7.2.3
Section 7.2.4
Time and date registers
04h
Seconds
OS
SECONDS (0 to 59)
Section 7.3.1
05h
Minutes
-
MINUTES (0 to 59)
Section 7.3.2
06h
Hours
-
-
AMPM
HOURS (1 to 12) in 12-hour mode
Section 7.3.3
HOURS (0 to 23) in 24-hour mode
07h
Days
-
-
DAYS (1 to 31)
Section 7.3.4
08h
Weekdays
-
-
-
-
09h
Months
-
-
-
MONTHS (1 to 12)
0Ah
Years
YEARS (0 to 99)
Section 7.3.7
-
WEEKDAYS (0 to 6)
Section 7.3.5
Section 7.3.6
Alarm registers
0Bh
Second_alarm
AEN_S
SECOND_ALARM (0 to 59)
Section 7.5.1
0Ch
Minute_alarm
AEN_M
MINUTE_ALARM (0 to 59)
Section 7.5.2
0Dh
Hour_alarm
AEN_H
-
AMPM
HOUR_ALARM (1 to 12) in 12-hour mode
Section 7.5.3
HOUR_ALARM (0 to 23) in 24-hour mode
0Eh
Day_alarm
AEN_D
-
DAY_ALARM (1 to 31)
0Fh
Weekday_alarm
AEN_W
-
-
-
Section 7.5.4
-
WEEKDAY_ALARM (0 to 6)
Section 7.5.5
Timer registers
PCA85063A
Product data sheet
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 4. Registers overview...continued
Bit positions labeled as - are not implemented. After reset, all registers are set according to Table 7.
Address
Register name
Bit
7
10h
Timer_value
T[7:0]
11h
Timer_mode
-
PCA85063A
Product data sheet
Reference
6
5
4
3
2
1
0
Section 7.6.1
-
-
TCF[1:0]
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Rev. 4.1 — 16 September 2021
TE
TIE
TI_TP
Section 7.6.2
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
7.2 Control registers
To ensure that all control registers will be set to their default values, the VDD level must
be at zero volts at initial power-up. If this is not possible, a reset must be initiated with the
software reset command when power is stable. Refer to Section 7.2.1.3 for details.
7.2.1 Register Control_1
Table 5. Control_1 - control and status register 1 (address 00h) bit description
Bit
Symbol
7
EXT_TEST
Value
0
[1]
1
6
-
5
STOP
[1]
1
4
[1]
CIE
[1]
1
STOP bit
Section 7.2.1.2
RTC clock runs
Section 7.2.1.3
no software reset
unused
-
correction interrupt enable
Section 7.2.3
no correction interrupt generated
12 or 24-hour mode
0
[1]
1
24-hour mode is selected
internal oscillator capacitor selection for
quartz crystals with a corresponding load
capacitance
1
Section 7.3.3
Section 7.5.3
12-hour mode is selected
CAP_SEL
0
[1]
[2]
-
interrupt pulses are generated at every
correction cycle
12_24
0
unused
initiate software reset ; this bit always
returns a 0 when read
0
0
1
normal mode
[2]
1
2
Section 7.2.1.1
software reset
0
-
external clock test mode
RTC clock is stopped; all RTC divider chain
flip-flops are asynchronously set logic 0
SR
3
Reference
external clock test mode
0
0
Description
[1]
-
7 pF
12.5 pF
Default value.
For a software reset, 0101 1000 (58h) must be sent to register Control_1 (see Section 7.2.1.3).
7.2.1.1 EXT_TEST: external clock test mode
A test mode is available which allows for on-board testing. In this mode, it is possible to
set up test conditions and control the operation of the RTC.
The test mode is entered by setting bit EXT_TEST in register Control_1. Then pin
CLKOUT becomes an input. The test mode replaces the internal clock signal with the
signal applied to pin CLKOUT.
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PCA85063A
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2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
The signal applied to pin CLKOUT should have a minimum pulse width of 300 ns and a
maximum period of 1 000 ns. The internal clock, now sourced from CLKOUT, is divided
6
down to 1 Hz by a 2 divide chain called a prescaler. The prescaler can be set into a
known state by using bit STOP. When bit STOP is set, the prescaler is reset to 0. (STOP
must be cleared before the prescaler can operate again.)
From a stop condition, the first 1 second increment will take place after 32 positive edges
on pin CLKOUT. Thereafter, every 64 positive edges cause a 1 second increment.
Remark: Entry into test mode is not synchronized to the internal 64 Hz clock. When
entering the test mode, no assumption as to the state of the prescaler can be made.
Operation example:
1.
2.
3.
4.
5.
6.
7.
8.
Set EXT_TEST test mode (register Control_1, bit EXT_TEST = 1).
Set STOP (register Control_1, bit STOP = 1).
Clear STOP (register Control_1, bit STOP = 0).
Set time registers to desired value.
Apply 32 clock pulses to pin CLKOUT.
Read time registers to see the first change.
Apply 64 clock pulses to pin CLKOUT.
Read time registers to see the second change.
Repeat 7 and 8 for additional increments.
7.2.1.2 STOP: STOP bit function
The function of the STOP bit (see Figure 4) is to allow for accurate starting of the time
circuits. The STOP bit function causes the upper part of the prescaler (F2 to F14) to
be held in reset and thus no 1 Hz ticks are generated. It also stops the output of clock
frequencies below 8 kHz on pin CLKOUT.
OSCILLATOR STOP
DETECTOR
OSCILLATOR
32768 Hz
F0
16384 Hz
F1
8192 Hz
F2
setting the OS flag
4096 Hz
RESET
F13
RESET
2 Hz
F14
RESET
1 Hz tick
STOP
aaa-004415
Figure 4. STOP bit functional diagram
The time circuits can then be set and do not increment until the STOP bit is released (see
Figure 5 and Table 6).
Table 6. First increment of time circuits after STOP bit release
Bit
Prescaler bits
STOP
F0F1-F2 to F14
[1]
1 Hz tick
Time
Comment
hh:mm:ss
Clock is running normally
0
01-0 0001 1101
0100
PCA85063A
Product data sheet
12:45:12
prescaler counting normally
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 6. First increment of time circuits after STOP bit release...continued
Bit
Prescaler bits
STOP
F0F1-F2 to F14
[1]
1 Hz tick
Time
Comment
hh:mm:ss
STOP bit is activated by user. F0F1 are not reset and values cannot be predicted externally
1
12:45:12
prescaler is reset; time circuits are frozen
08:00:00
prescaler is reset; time circuits are frozen
08:00:00
prescaler is now running
08:00:00
-
XX-0 1000 0000
0000
08:00:00
-
XX-1 1000 0000
0000
08:00:00
-
:
:
:
08:00:00
-
00-0 0000 0000
0001
08:00:01
0 to 1 transition of F14 increments the time circuits
10-0 0000 0000
0001
08:00:01
-
:
:
11-1 1111 1111
1111
08:00:01
-
00-0 0000 0000
0000
08:00:01
-
10-0 0000 0000
0000
08:00:01
-
:
:
:
11-1 1111 1111
1110
08:00:01
-
00-0 0000 0000
0001
08:00:02
0 to 1 transition of F14 increments the time circuits
XX-0 0000 0000
0000
New time is set by user
1
XX-0 0000 0000
0000
STOP bit is released by user
0
XX-0 0000 0000
0000
XX-1 0000 0000
0000
11-1 1111 1111
1110
:
[1]
0.507813
to
0.507935 s
1.000000 s
aaa-004416
F0 is clocked at 32.768 kHz.
2
The lower two stages of the prescaler (F0 and F1) are not reset. And because the I Cbus is asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is
between zero and one 8.192 kHz cycle (see Figure 5).
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PCA85063A
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
8192 Hz
stop released
0 µs to 122 µs
aaa-004417
Figure 5. STOP bit release timing
The first increment of the time circuits is between 0.507 813 s and 0.507 935 s after
STOP bit is released. The uncertainty is caused by the prescaler bits F0 and F1 not being
reset (see Table 6) and the unknown state of the 32 kHz clock.
7.2.1.3 Software reset
A reset is automatically generated at power-on. There is a low probability that some
devices will have corruption of the registers after the automatic power-on reset if the
device is powered up with a residual VDD level. It is required that the VDD starts at zero
volts at power up or upon power cycling to ensure that there is no corruption of the
registers. If this is not possible, a reset must be initiated after power-up (i.e. when power
is stable) with the software reset command. Software reset command means setting bits
6, 4, and 3 in register Control_1 (00h) logic 1 and all other bits logic 0 by sending the bit
sequence 0101 1000 (58h), see Figure 6.
slave address
SDA
s
1
0
1
0
0
address 00h
R/W
0
1
0
A
0
0
0
0
0
0
software reset 58h
0
0
A
0
1
0
1
1
0
0
0
A P/S
SCL
internal
reset signal
aaa-004418
After sending the software reset command, it is recommended to re-initialize the interface by a STOP and START.
Figure 6. Software reset command
In reset state, all registers are set according to Table 7 and the address pointer returns to
address 00h.
Table 7. Registers reset values
Address
PCA85063A
Product data sheet
Register name
Bit
7
6
5
4
3
2
1
0
00h
Control_1
0
0
0
0
0
0
0
0
01h
Control_2
0
0
0
0
0
0
0
0
02h
Offset
0
0
0
0
0
0
0
0
03h
RAM_byte
0
0
0
0
0
0
0
0
04h
Seconds
1
0
0
0
0
0
0
0
05h
Minutes
0
0
0
0
0
0
0
0
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 7. Registers reset values...continued
Address
Register name
Bit
7
6
5
4
3
2
1
0
06h
Hours
0
0
0
0
0
0
0
0
07h
Days
0
0
0
0
0
0
0
1
08h
Weekdays
0
0
0
0
0
1
1
0
09h
Months
0
0
0
0
0
0
0
1
0Ah
Years
0
0
0
0
0
0
0
0
0Bh
Second_alarm
1
0
0
0
0
0
0
0
0Ch
Minute_alarm
1
0
0
0
0
0
0
0
0Dh
Hour_alarm
1
0
0
0
0
0
0
0
0Eh
Day_alarm
1
0
0
0
0
0
0
0
0Fh
Weekday_alarm
1
0
0
0
0
0
0
0
10h
Timer_value
0
0
0
0
0
0
0
0
11h
Timer_mode
0
0
0
1
1
0
0
0
The PCA85063A resets to:
Time
00:00:00
Date
20000101
Weekday
Saturday
7.2.2 Register Control_2
Table 8. Control_2 - control and status register 2 (address 01h) bit description
Bit
Symbol
7
AIE
Value
0
[1]
1
6
Description
Reference
alarm interrupt
Section 7.2.2.1
Section 7.5.6
disabled
enabled
alarm flag
AF
0
[1]
read: alarm flag inactive
Section 7.2.2.1
Section 7.5.6
write: alarm flag is cleared
read: alarm flag active
1
write: alarm flag remains unchanged
5
minute interrupt
MI
0
1
PCA85063A
Product data sheet
[1]
disabled
Section 7.2.2.2
Section 7.2.2.3
enabled
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 8. Control_2 - control and status register 2 (address 01h) bit description...continued
Bit
Symbol
4
HMI
Value
0
[1]
[1]
no timer interrupt generated
1
[1]
Section 7.2.2.2
Section 7.2.2.3
timer flag
0
COF[2:0]
half minute interrupt
enabled
TF
2 to 0
Reference
disabled
1
3
Description
flag set when timer interrupt generated
see Table 10
CLKOUT control
Section 7.2.2.1
Section 7.2.2.3
Section 7.6.3
Section 7.2.2.4
Default value.
PCA85063A
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
7.2.2.1 Alarm interrupt
HMI
SECONDS COUNTER
HMI/MI
MINUTES COUNTER
HMI MI
SET
MI
0
CLEAR
1
PULSE
GENERATOR 1
TRIGGER
CLEAR
from interface:
clear TF
TI_TP
TIMER FLAG
TF
SET
COUNTDOWN COUNTER
CLEAR
TE
to interface:
read TF
TIE
0
PULSE
GENERATOR 2
TRIGGER
1
INT
CLEAR
set alarm
flag, AF
ALARM FLAG
AF
SET
to interface:
read AF
AIE
example
AIE
CLEAR
from interface:
clear AF
offset circuit:
add/substract
pulse
PULSE
GENERATOR 3
TRIGGER
CIE
0
1
CLEAR
from interface:
set CIE
aaa-004432
Figure 7. Interrupt scheme
AIE
This bit activates or deactivates the generation of an interrupt when AF is asserted,
respectively.
AF
When an alarm occurs, AF is set logic 1. This bit maintains its value until overwritten by
command. To prevent one flag being overwritten while clearing another, a logic AND is
performed during a write access.
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
7.2.2.2 MI and HMI: minute and half minute interrupt
The minute interrupt (bit MI) and half minute interrupt (bit HMI) are pre-defined timers for
generating interrupt pulses on pin INT; see Figure 8. The timers are running in sync with
the seconds counter (see Table 18).
The minute and half minute interrupts must only be used when the frequency offset is set
to normal mode (MODE = 0), see Section 7.2.3. In normal mode, the interrupt pulses on
1
pin INT are ⁄64 s wide.
When starting MI, the first interrupt will be generated after 1 second to 59 seconds.
When starting HMI, the first interrupt will be generated after 1 second to 29 seconds.
Subsequent periods do not have such a delay. The timers can be enabled independently
from one another. However, a minute interrupt enabled on top of a half minute interrupt is
not distinguishable.
seconds counter
58
59
minutes counter
59
00
11
12
00
01
INT when MI enabled
TF when MI enabled
aaa-004419
In this example, the TF flag is not cleared after an interrupt.
Figure 8. INT example for MI
Table 9. Effect of bits MI and HMI on INT generation
Minute interrupt (bit MI)
Half minute interrupt (bit HMI)
Result
0
0
no interrupt generated
1
0
an interrupt every minute
0
1
an interrupt every 30 s
1
1
an interrupt every 30 s
The duration of the timer is affected by the register Offset (see Section 7.2.3). Only when
OFFSET[6:0] has the value 00h the periods are consistent.
7.2.2.3 TF: timer flag
The timer flag (bit TF) is set logic 1 on the first trigger of MI, HMI, or the countdown timer.
The purpose of the flag is to allow the controlling system to interrogate what caused the
interrupt: timer or alarm. The flag can be read and cleared by command.
The status of the timer flag TF can affect the INT pulse generation depending on the
setting of TI_TP (see Section 7.6.2):
• When TI_TP is set logic 1
– an INT pulse is generated independent of the status of the timer flag TF
– TF stays set until it is cleared
– TF does not affect INT
– the countdown timer runs in a repetitive loop and keeps generating timed periods
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• When TI_TP is set logic 0
– the INT generation follows the TF flag
– TF stays set until it is cleared
– If TF is not cleared before the next coming interrupt, no INT is generated
– the countdown timer stops after the first countdown
7.2.2.4 COF[2:0]: Clock output frequency
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
COF[2:0] bits in the register Control_2. Frequencies of 32.768 kHz (default) down to 1
Hz can be generated for use as a system clock, microcontroller clock, input to a charge
pump, or for calibration of the oscillator.
Pin CLKOUT is a push-pull output and enabled at power-on. CLKOUT can be disabled
by setting COF[2:0] to 111. When disabled, the CLKOUT is LOW.
The duty cycle of the selected clock is not controlled. However, due to the nature of the
clock generation, all clock frequencies except 32.768 kHz have a duty cycle of 50 : 50.
The STOP bit function can also affect the CLKOUT signal, depending on the selected
frequency. When the STOP bit is set logic 1, the CLKOUT pin generates a continuous
LOW for those frequencies that can be stopped. For more details of the STOP bit
function, see Section 7.2.1.2.
Table 10. CLKOUT frequency selection
COF[2:0]
[2]
CLKOUT frequency (Hz) Typical duty cycle
[1]
Effect of STOP bit
000
32 768
60 : 40 to 40 : 60
no effect
001
16 384
50 : 50
no effect
010
8 192
50 : 50
no effect
011
4 096
50 : 50
CLKOUT = LOW
100
2 048
50 : 50
CLKOUT = LOW
101
1 024
50 : 50
CLKOUT = LOW
50 : 50
CLKOUT = LOW
-
-
[3]
110
1
111
CLKOUT = LOW
[1]
[2]
[3]
Duty cycle definition: % HIGH-level time : % LOW-level time.
Default value.
1 Hz clock pulses are affected by offset correction pulses.
7.2.3 Register Offset
The PCA85063A incorporates an offset register (address 02h) which can be used to
implement several functions, such as:
• Accuracy tuning
• Aging adjustment
• Temperature compensation
Table 11. Offset - offset register (address 02h) bit description
PCA85063A
Product data sheet
Bit
Symbol
7
MODE
Value
Description
offset mode
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 11. Offset - offset register (address 02h) bit description...continued
Bit
Symbol
Value
0
Description
[1]
normal mode: offset is made once every two
hours
1
6 to 0
[1]
OFFSET[6:0]
course mode: offset is made every 4
minutes
offset value
see Table 12
Default value.
For MODE = 0, each LSB introduces an offset of 4.34 ppm. For MODE = 1, each LSB
introduces an offset of 4.069 ppm. The offset value is coded in two’s complement giving a
range of +63 LSB to -64 LSB.
Table 12. Offset values
OFFSET[6:0]
Offset value in
decimal
Offset value in ppm
Normal mode
MODE = 0
Fast mode
MODE = 1
011 1111
+63
+273.420
+256.347
011 1110
+62
+269.080
+252.278
:
:
:
:
000 0010
+2
+8.680
+8.138
000 0001
+1
+4.340
+4.069
[1]
[1]
0
0
111 1111
-1
-4.340
-4.069
111 1110
-2
-8.680
-8.138
:
:
:
:
100 0001
-63
-273.420
-256.347
100 0000
-64
-277.760
-260.416
[1]
0
[1]
000 0000
Default value.
The correction is made by adding or subtracting clock correction pulses, thereby
changing the period of a single second but not by changing the oscillator frequency.
It is possible to monitor when correction pulses are applied. To enable correction interrupt
generation, bit CIE (register Control_1) has to be set logic 1. At every correction cycle,
a pulse is generated on pin INT. The pulse width depends on the correction mode. If
multiple correction pulses are applied, an interrupt pulse is generated for each correction
pulse applied.
7.2.3.1 Correction when MODE = 0
The correction is triggered once every two hours and then correction pulses are applied
once per minute until the programmed correction values have been implemented.
PCA85063A
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 13. Correction pulses for MODE = 0
th
Correction value
Update every n hour Minute
Correction pulses on
[1]
INT per minute
+1 or -1
2
00
1
+2 or -2
2
00 and 01
1
+3 or -3
2
00, 01, and 02
1
:
:
:
:
+59 or -59
2
00 to 58
1
+60 or -60
2
00 to 59
1
+61 or -61
2
00 to 59
1
2nd and next hour
00
1
2
00 to 59
1
2nd and next hour
00 and 01
1
02
00 to 59
1
2nd and next hour
00, 01, and 02
1
02
00 to 59
1
2nd and next hour
00, 01, 02, and 03
1
+62 or -62
+63 or -63
-64
[1]
1
The correction pulses on pin INT are ⁄64 s wide.
In MODE = 0, any timer or clock output using a frequency below 64 Hz is affected by the
clock correction (see Table 14).
Table 14. Effect of correction pulses on frequencies for MODE = 0
Frequency (Hz)
Effect of correction
CLKOUT
32 768
no effect
16 384
no effect
8 192
no effect
4 096
no effect
2 048
no effect
1 024
no effect
1
affected
Timer source clock
4 096
no effect
64
no effect
1
affected
1
affected
⁄60
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7.2.3.2 Correction when MODE = 1
The correction is triggered once every four minutes and then correction pulses are
applied once per second up to a maximum of 60 pulses. When correction values greater
th
than 60 pulses are used, additional correction pulses are made in the 59 second.
Clock correction is made more frequently in MODE = 1; however, this can result in higher
power consumption.
Table 15. Correction pulses for MODE = 1
th
Correction value
Update every n
minute
Second
Correction pulses on
[1]
INT per second
+1 or -1
2
00
1
+2 or -2
2
00 and 01
1
+3 or -3
2
00, 01, and 02
1
:
:
:
:
+59 or -59
2
00 to 58
1
+60 or -60
2
00 to 59
1
+61 or -61
2
00 to 58
1
2
59
2
2
00 to 58
1
2
59
3
2
00 to 58
1
2
59
4
2
00 to 58
1
2
59
5
+62 or -62
+63 or -63
-64
[1]
1
1
The correction pulses on pin INT are ⁄1 024 s wide. For multiple pulses, they are repeated at an interval of ⁄512 s.
In MODE = 1, any timer source clock using a frequency below 1.024 kHz is also affected
by the clock correction (see Table 16).
Table 16. Effect of correction pulses on frequencies for MODE = 1
Frequency (Hz)
Effect of correction
CLKOUT
32 768
no effect
16 384
no effect
8 192
no effect
4 096
no effect
2 048
no effect
1 024
no effect
1
affected
Timer source clock
4 096
PCA85063A
Product data sheet
no effect
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 16. Effect of correction pulses on frequencies for MODE = 1...continued
Frequency (Hz)
Effect of correction
64
affected
1
affected
1
affected
⁄60
7.2.3.3 Offset calibration workflow
The calibration offset has to be calculated based on the time. Figure 9 shows the
workflow how the offset register values can be calculated:
Measure the frequency on pin CLKOUT:
fmeas
sample calculation:
32768.48 Hz
Convert to time:
tmeas = 1 / fmeas
30.517131 µs
Calculate the difference to the ideal
period of 1 / 32768.00:
Dmeas = 1 / 32768 - tmeas
0.000447 µs
Calculate the ppm deviation compared
to the measured value:
Eppm = 1000000 × Dmeas / tmeas
14.648 ppm
Calculate the offset register value:
Mode = 0 (low power):
Offset value = Eppm / 4.34
3.375
Mode = 1 (fast correction)
Offset value = Eppm / 4.069
3 correction pulses
are needed
3.600
4 correction pulses
are needed
aaa-004375
Figure 9. Offset calibration calculation workflow
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
(2)
(1)
(3)
-6
-4
-2
deviation after
correction in
MODE = 1
-1.628 ppm
0
2
4
6
8
10
12
deviation after
correction in
MODE = 0
+1.628 ppm
14
16
measured/calculated
deviation 14.648 ppm
aaa-004371
With the offset calibration an accuracy of ±2 ppm (0.5 × offset per LSB) can be reached (see
Table 12).
±1 ppm corresponds to a time deviation of 0.0864 seconds per day.
1. 3 correction pulses in MODE = 0 correspond to -13.02 ppm.
2. 4 correction pulses in MODE = 1 correspond to -16.276 ppm.
3. Reachable accuracy zone.
Figure 10. Result of offset calibration
7.2.4 Register RAM_byte
The PCA85063A provides a free RAM byte, which can be used for any purpose, for
example, status byte of the system.
Table 17. RAM_byte - 8-bit RAM register (address 03h) bit description
Bit
Symbol
7 to 0
[1]
Value
B[7:0]
0000 0000
1111 1111
Description
[1]
to RAM content
Default value.
7.3 Time and date registers
Most of the registers are coded in the BCD format to simplify application use.
7.3.1 Register Seconds
Table 18. Seconds - seconds register (address 04h) bit description
Bit
Symbol
7
OS
Value
oscillator stop
0
6 to 4
3 to 0
PCA85063A
Product data sheet
Place value Description
SECONDS
-
clock integrity is guaranteed
-
clock integrity is not
guaranteed; oscillator
has stopped or has been
interrupted
1
[1]
0
[1]
to 5
ten’s place
0
[1]
to 9
unit place
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actual seconds coded in BCD
format, see Table 19
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
[1]
Default value.
Table 19. Seconds coded in BCD format
Seconds value in
decimal
Upper-digit (ten’s place)
Digit (unit place)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
0
0
0
01
0
0
0
0
0
0
1
02
0
0
0
0
0
1
0
:
:
:
:
:
:
:
:
09
0
0
0
1
0
0
1
10
0
0
1
0
0
0
0
:
:
:
:
:
:
:
:
58
1
0
1
1
0
0
0
59
1
0
1
1
0
0
1
00
[1]
[1]
Default value.
7.3.1.1 OS: Oscillator stop
When the oscillator of the PCA85063A is stopped, the OS flag is set. The oscillator can
be stopped, for example, by connecting one of the oscillator pins OSCI or OSCO to
ground. The oscillator is considered to be stopped during the time between power-on and
stable crystal resonance. This time can be in the range of 200 ms to 2 s depending on
crystal type, temperature, and supply voltage.
The flag remains set until cleared by command (see Figure 11). If the flag cannot be
cleared, then the oscillator is not running. This method can be used to monitor the
oscillator and to determine if the supply voltage has reduced to the point where oscillation
fails.
OS = 1 and flag can not be cleared
OS = 1 and flag can be cleared
VDD
oscillation
OS flag
OS flag cleared
by software
oscillation now stable
OS flag set when
oscillation stops
t
aaa-004420
Figure 11. OS flag
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7.3.2 Register Minutes
Table 20. Minutes - minutes register (address 05h) bit description
Bit
Symbol
Value
Place value Description
7
-
0
-
unused
actual minutes coded in BCD
format
6 to 4
MINUTES
3 to 0
[1]
0
[1]
to 5
ten’s place
0
[1]
to 9
unit place
Default value.
7.3.3 Register Hours
Table 21. Hours - hours register (address 06h) bit description
Bit
Symbol
Value
Place value Description
7 to 6
-
00
-
unused
[1]
12-hour mode
5
AM/PM indicator
AMPM
0
[2]
1
4
HOURS
3 to 0
-
AM
-
PM
0
[2]
to 1
ten’s place
0
[2]
to 9
unit place
0
[2]
to 2
ten’s place
0
[2]
to 9
unit place
actual hours in 12-hour mode
coded in BCD format
[1]
24-hour mode
5 to 4
HOURS
3 to 0
[1]
[2]
actual hours in 24-hour mode
coded in BCD format
Hour mode is set by the 12_24 bit in register Control_1.
Default value.
7.3.4 Register Days
Table 22. Days - days register (address 07h) bit description
Bit
Symbol
Value
Place value Description
7 to 6
-
00
-
unused
actual day coded in BCD format
5 to 4
[1]
DAYS
3 to 0
[1]
[2]
[3]
0
[2]
to 3
ten’s place
0
[3]
to 9
unit place
If the year counter contains a value, which is exactly divisible by 4 (including the year 00), the PCA85063A compensates
for leap years by adding a 29th day to February.
Default value.
Default value is 1.
7.3.5 Register Weekdays
Table 23. Weekdays - weekdays register (address 08h) bit description
PCA85063A
Product data sheet
Bit
Symbol
Value
Description
7 to 3
-
0000 0
unused
2 to 0
WEEKDAYS
0 to 6
actual weekday values, see Table 24
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Table 24. Weekday assignments
Day
[1]
Bit
2
1
0
Sunday
0
0
0
Monday
0
0
1
Tuesday
0
1
0
Wednesday
0
1
1
Thursday
1
0
0
Friday
1
0
1
1
1
0
[2]
Saturday
[1]
[2]
Definition may be reassigned by the user.
Default value.
7.3.6 Register Months
Table 25. Months - months register (address 09h) bit description
Bit
Symbol
Value
Place value Description
7 to 5
-
000
-
unused
4
MONTHS
0 to 1
ten’s place
0 to 9
unit place
actual month coded in BCD
format, see Table 26
3 to 0
Table 26. Month assignments in BCD format
Upper-digit
(ten’s place)
Digit (unit place)
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
February
0
0
0
1
0
March
0
0
0
1
1
April
0
0
1
0
0
May
0
0
1
0
1
June
0
0
1
1
0
July
0
0
1
1
1
August
0
1
0
0
0
September
0
1
0
0
1
October
1
0
0
0
0
November
1
0
0
0
1
December
1
0
0
1
0
Month
January
[1]
PCA85063A
Product data sheet
[1]
Default value.
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
7.3.7 Register Years
Table 27. Years - years register (0Ah) bit description
Bit
Symbol
7 to 4
Value
YEARS
3 to 0
[1]
Place value Description
0
[1]
to 9
ten’s place
0
[1]
to 9
unit place
actual year coded in BCD format
Default value.
7.4 Setting and reading the time
Figure 12 shows the data flow and data dependencies starting from the 1 Hz clock tick.
1 Hz tick
SECONDS
MINUTES
12_24 hour mode
LEAP YEAR
CALCULATION
HOURS
DAYS
WEEKDAY
MONTHS
YEARS
aaa-004421
Figure 12. Data flow for the time function
During read/write operations, the time counting circuits (memory locations 04h through
0Ah) are blocked.
The blocking prevents
• Faulty reading of the clock and calendar during a carry condition
• Incrementing the time registers during the read cycle
After this read/write access is completed, the time circuit is released again and any
pending request to increment the time counters that occurred during the read/write
access is serviced. A maximum of 1 request can be stored; therefore, all accesses must
be completed within 1 second (see Figure 13).
t1
4 096
1
1
64
1
1
1
1
1
1
1
1
⁄60
[1]
PCA85063A
Product data sheet
[1]
T=1
⁄8 192
⁄128
⁄64
⁄64
⁄4 096
⁄64
⁄64
⁄64
T = loaded countdown value. Timer stops when T = 0.
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
8
2
Characteristics of the I C-bus interface
2
The I C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor. Data transfer may be
initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse, as changes in the data line at
this time are interpreted as a control signal (see Figure 16).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Figure 16. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the
START condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 17).
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc 622
Figure 17. Definition of START and STOP conditions
8.3 System configuration
A device generating a message is a transmitter; a device receiving a message is a
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves (see Figure 18).
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
mga807
Figure 18. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver, which is addressed, must generate an acknowledge after the
reception of each byte
• Also a master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered)
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition
2
Acknowledgement on the I C-bus is shown in Figure 19.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
2
Figure 19. Acknowledgement on the I C-bus
2
8.5 I C-bus protocol
8.5.1 Addressing
2
2
One I C-bus slave address (1010 001) is reserved for the PCA85063A. The entire I Cbus slave address byte is shown in Table 38.
PCA85063A
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
2
Table 38. I C slave address byte
Slave address
7
Bit
6
5
4
3
2
1
MSB
0
LSB
1
0
1
0
0
0
1
R/W
2
After a START condition, the I C slave address has to be sent to the PCA85063A device.
The R/W bit defines the direction of the following single or multiple byte data transfer
(R/W = 0 for writing, R/W = 1 for reading). For the format and the timing of the START
2
condition (S), the STOP condition (P) and the acknowledge bit (A) refer to the I C-bus
characteristics (see [5]). In the write mode, a data transfer is terminated by sending either
the STOP condition or the START condition of the next data transfer.
8.5.2 Clock and calendar READ or WRITE cycles
2
The I C-bus configuration for the different PCA85063A READ and WRITE cycles is
shown in Figure 20 and Figure 21. The register address is a 5-bit value that defines
which register is to be accessed next. The upper 3 bits of the register address are not
used.
acknowledge
from PCA85063A
S
1
0
1
0
0
0
1
slave address
0
acknowledge
from PCA85063A
acknowledge
from PCA85063A
A
A
A
write bit
register address
00h to 11h
0 to n
data bytes
P/S
START/
STOP
aaa-013716
Figure 20. Master transmits to slave receiver (WRITE mode)
acknowledge
from PCA85063A
S
1
0
1
0
0
0
1
slave address
0
acknowledge
from PCA85063A
A
write bit
A
register address
00h to 11h
acknowledge
from PCA85063A
S
1
0
1
0
0
slave address
0
1
1
read bit
A
DATA BYTE
set register
address
P
STOP
acknowledge
from master
no acknowledge
A
A
LAST DATA BYTE
read register
data
P
0 to n data bytes
auto increment
memory register address
auto increment
memory register address
aaa-013717
For multimaster configurations and to fasten the communication, the STOP-START sequence can be replaced by a
repeated START (Sr).
Figure 21. Master reads after setting register address (write register address; READ data)
PCA85063A
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2
8.5.3 I C-bus error recovery technique
2
Slave devices like the PCA85063A use a state machine to implement the I C protocol
and expect a certain sequence of events to occur to function properly. Unexpected
2
events at the I C master can wreak havoc with the slaves connected on the bus.
However, it is usually possible to recover deterministically to a known bus state with
careful protocol manipulation.
A deterministic method to clear this situation if SDA is stuck LOW (it effectively blocks
any other I2C-bus transaction, once the master recognizes a ‘stuck bus’ state), is for
the master to blindly transmit nine clocks on SCL. If the slave was transmitting data or
acknowledging, nine or more clocks ensures the slave state machine returns to a known,
idle state since the protocol calls for eight data bits and one ACK bit. It does not matter
when the slave state machine finishes its transmission; extra clocks are recognized as
STOP conditions.
2
With careful design of the bus master error recovery firmware, many I C-bus protocol
problems can be avoided.
S/W considerations: NXP recommends customers allow for S/W reset capability to
enable the bus error recovery technique. The 9-clock pulse method as described above
involves a bus-master capable of providing such a signal.
Further comments/additional information are available in [6] and [5]"UM10204".
9
Internal circuitry
PCA85063A
VDD
OSCI
CLKOUT
OSCO
SCL
INT
SDA
VSS
aaa-013718
Figure 22. Device diode protection diagram of PCA85063A
10 Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
PCA85063A
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
11 Limiting values
[1]
Table 39. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Conditions
Min
Max
Unit
supply voltage
-0.5
+6.5
V
IDD
supply current
-50
+50
mA
VI
input voltage
-0.5
+6.5
V
VO
output voltage
-0.5
+6.5
V
II
input current
at any input
-10
+10
mA
IO
output current
at any output
-10
+10
mA
Ptot
total power dissipation
on pins SCL, SDA, OSCI
-
300
mW
electrostatic discharge HBM
voltage
CDM
[2]
-
±5 000
V
[3]
-
±2 000
V
latch-up current
[4]
-
200
mA
Tstg
storage temperature
[5]
-65
+150
°C
Tamb
ambient temperature
-40
+105
°C
VESD
Ilu
[1]
[2]
[3]
[4]
[5]
operating device
Remark: The PCA85063A part is not guaranteed (nor characterized) above the operating range as denoted in the datasheet. NXP recommends not to
bias the PCA85063A device during reflow (e.g. if utilizing a 'coin' type battery in the assembly). If customer so chooses to continue to use this assembly
method, there must be the allowance for a full '0 V' level Power supply 'reset' to re-enable the device. Without a proper POR, the device may remain in an
indeterminate state.
Pass level; Human Body Model (HBM) according to [1].
Pass level; Charged-Device Model (CDM), according to [2].
Pass level; latch-up testing, according to [3] at maximum ambient temperature (Tamb(max)).
According to the store and transport requirements (see [7]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to
75 %.
12 Characteristics
Table 40. Static characteristics
VDD = 0.9 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +105 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise
specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
interface inactive; fSCL = 0 Hz
[1]
0.9
-
5.5
V
interface active; fSCL = 400 kHz
[1]
1.8
-
5.5
V
CLKOUT disabled;
VDD = 5 V
[2]
Tamb = 25 °C
-
250
450
nA
Tamb = 85 °C
-
550
750
nA
Tamb = 105 °C
-
900
1 800
nA
interface active;
fSCL = 400 kHz
-
35
50
μA
Supplies
VDD
IDD
supply current
interface inactive; fSCL = 0 Hz
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Table 40. Static characteristics...continued
VDD = 0.9 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +105 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise
specified.
Symbol
Inputs
Parameter
Conditions
Min
Typ
Max
Unit
[3]
VI
input voltage
VSS
-
5.5
V
VIL
LOW-level input
voltage
VSS
-
0.3VDD
V
VIH
HIGH-level input
voltage
0.7VDD
-
VDD
V
ILI
input leakage current
-
0
-
μA
-0.15
-
+0.15
μA
-
-
7
pF
VI = VSS or VDD
post ESD event
Ci
[4]
input capacitance
Outputs
VOH
HIGH-level output
voltage
on pin CLKOUT
0.8VDD
-
VDD
V
VOL
LOW-level output
voltage
on pins SDA, INT, CLKOUT
VSS
-
0.2VDD
V
IOH
HIGH-level output
current
output source current;
VOH = 4.6 V;
VDD = 5 V;
on pin CLKOUT
1
3
-
mA
IOL
LOW-level output
current
output sink current; VOL = 0.4 V;
VDD = 5 V
on pin SDA
3
8.5
-
mA
on pin INT
2
6
-
mA
on pin CLKOUT
1
3
-
mA
-
0.075
-
ppm
CL = 7 pF
4.2
7
9.8
pF
CL = 12.5 pF
7.5
12.5
17.5
pF
-
-
100
kΩ
Oscillator
Δfosc/fosc
relative oscillator
frequency variation
ΔVDD = 200 mV; Tamb = 25 °C
CL(itg)
integrated load
capacitance
on pins OSCO, OSCI
Rs
[1]
[2]
[3]
[4]
[5]
[5]
series resistance
For reliable oscillator start-up at power-on use VDD greater than 1.2 V. If powered up at 0.9 V the oscillator will start but it might be a bit slow, especially if
at high temperature. Normally the power supply is not 0.9 V at start-up and only comes at the end of battery discharge. VDD min of 0.9 V is specified so
that the customer can calculate how large a battery or capacitor they need for their application. VDD min of 1.2 V or greater is needed to ensure speedy
oscillator start-up time. For a restart condition, NXP recommends a full '0 V' VDD value upon re-biasing.
1
Timer source clock = ⁄60 Hz, level of pins SCL and SDA is VDD or VSS.
2
The I C-bus interface of PCA85063A is 5 V tolerant.
Implicit by design.
Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series:
.
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
IDD
(µA)
aaa-005740
50
40
30
(1)
20
(2)
10
0
0
100
200
300
400
fSCL (kHz)
500
Tamb = 25 °C; CLKOUT disabled.
1. VDD = 5.0 V.
2. VDD = 3.3 V.
Figure 23. Typical IDD with respect to fSCL
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
aaa-017376
1200
IDD
(nA)
1000
800
(1)
(2)
600
400
200
0
-50
-10
30
70
Tamb (ºC)
110
CL(itg) = 7 pF; CLKOUT disabled.
1. VDD = 5.5 V.
2. VDD = 3.3 V.
aaa-017381
1200
IDD
(nA)
1000
800
(1)
(2)
600
400
200
0
-50
-10
30
70
Tamb (ºC)
110
CL(itg) = 12.5 pF; CLKOUT disabled.
1. VDD = 5.5 V.
2. VDD = 3.3 V.
Figure 24. Typical IDD as a function of temperature
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
IDD
(µA)
aaa-005739
12
10
(1)
(2)
8
(1)
6
(2)
4
2
0
0
1
2
3
4
5
6
VDD (V)
Tamb = 25 °C; fCLKOUT = 32 768 Hz.
1. 47 pF CLKOUT load.
2. 22 pF CLKOUT load.
aaa-005741
500
IDD
(nA)
400
300
(1)
(2)
200
100
0
0
1
2
3
4
5
VDD (V)
6
Tamb = 25 °C; CLKOUT disabled.
1. CL(itg) = 12.5 pF.
2. CL(itg) = 7 pF.
Figure 25. Typical IDD with respect to VDD
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
aaa-005841
800
IDD
(nA)
(1)
600
(2)
400
(3)
(4)
200
0
20
30
40
50
60
70
80
90
RS (kΩ)
100
VDD = 5 V; CLKOUT disabled.
1. CL(itg) = 12.5 pF; 50 °C; maximum value.
2. CL(itg) = 7 pF; 50 °C; maximum value.
3. CL(itg) = 12.5 pF; 25 °C; typical value.
4. CL(itg) = 7 pF; 25 °C; typical value.
Figure 26. IDD with respect to quartz RS
Δfosc
(ppm)
aaa-005743
3
1.5
0
(1)
(2)
-1.5
-3
0
1
2
3
4
5
VDD (V)
6
Tamb = -40 °C to +105 °C.
1. CL(itg) = 7 pF.
2. CL(itg) = 12.5 pF.
Figure 27. Oscillator frequency variation with respect to VDD
2
Table 41. I C-bus characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +105 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise
specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and
[1]
VIH with an input voltage swing of VSS to VDD .
Symbol
Parameter
Cb
capacitive load for
each bus line
fSCL
SCL clock frequency
tHD;STA
hold time (repeated)
START condition
PCA85063A
Product data sheet
Conditions
[2]
Min
Max
Unit
-
400
pF
0
400
kHz
0.6
-
μs
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2
Table 41. I C-bus characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = -40 °C to +105 °C; fosc = 32.768 kHz; quartz Rs = 60 kΩ; CL = 7 pF; unless otherwise
specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and
[1]
VIH with an input voltage swing of VSS to VDD .
Symbol
Parameter
tSU;STA
Min
Max
Unit
set-up time for a
repeated START
condition
0.6
-
μs
tLOW
LOW period of the
SCL clock
1.3
-
μs
tHIGH
HIGH period of the
SCL clock
0.6
-
μs
tr
rise time of both SDA
and SCL signals
20
300
ns
tf
fall time of both SDA
and SCL signals
20 × (VDD / 5.5 V) 300
ns
tBUF
bus free time between
a STOP and START
condition
1.3
-
μs
tSU;DAT
data set-up time
100
-
ns
tHD;DAT
data hold time
0
-
ns
tSU;STO
set-up time for STOP
condition
0.6
-
μs
tVD;DAT
data valid time
0
0.9
μs
tVD;ACK
data valid
acknowledge time
0
0.9
μs
tSP
pulse width of
spikes that must be
suppressed by the
input filter
0
50
ns
[1]
[2]
[3]
[4]
Conditions
[3] [4]
2
A detailed description of the I C-bus specification is given in [5].
2
I C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second.
A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined
region of the falling edge of SCL.
The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This
allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum
specified tf.
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
protocol
START
condition
(S)
bit 7
MSB
(A7)
tSU;STA
tLOW
bit 6
(A6)
tHIGH
1/f
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SCL
tBUF
tf
tr
SDA
tSU;DAT
tHD;STA
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
013aaa417
2
Figure 28. I C-bus timing diagram; rise and fall times refer to 30 % and 70 %
13 Application information
VDD(2)
TP(3)
SDA
R1(1)
SCL
1F
MASTER
TRANSMITTER/
RECEIVER
100 nF
VDD
CLKOUT
SCL
OSCI
OSCO
INT
VDD(2)
PCA85063A
SDA
R
VSS
R
R: pull-up resistor
R=
SDA SCL
(I2C-bus)
tr
Cb
aaa-013719
A 1 farad super capacitor combined with a low VF diode can be used as a standby or back-up
supply. With the RTC in its minimum power configuration that is, timer off and CLKOUT off, the
RTC may operate for weeks.
1. R1 limits the inrush current to the super capacitor at power-on.
2. NXP recommends tying VDD of the device and VDD of all the external pull-up resistors to the
same Power Supply.
3. NXP also recommends the customer place accessible 'Pads/TP-test point' on the layout so as
to enable a 'hard'' grounding of the power supply VDD in the event a full discharge cannot be
attained.
Figure 29. Application diagram for PCA85063A
PCA85063A
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14 Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
PCA85063A
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
15 Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
D
E
SOT505-1
A
X
c
y
HE
v M A
Z
5
8
A2
pin 1 index
(A3)
A1
A
θ
Lp
L
1
4
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D(1)
E(2)
e
HE
L
Lp
v
w
y
Z(1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.45
0.25
0.28
0.15
3.1
2.9
3.1
2.9
0.65
5.1
4.7
0.94
0.7
0.4
0.1
0.1
0.1
0.70
0.35
6°
0°
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-04-09
03-02-18
SOT505-1
Figure 30. Package outline SOT505-1 (TSSOP8) of PCA85063ATT
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16 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC61340-5 or equivalent
standards.
17 Packing information
17.1 Tape and reel information
For tape and reel packing information, please see [4].
18 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 31) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 42 and Table 43
Table 42. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 43. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
PCA85063A
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Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 31.
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 31. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
19 Footprint information
3.600
2.950
0.725
0.125
0.125
5.750
3.600
3.200
5.500
1.150
0.600
0.450
0.650
solder lands
occupied area
Dimensions in mm
sot505-1_fr
Figure 32. Footprint information for reflow soldering of SOT505-1 (TSSOP8) of
PCA85063ATT
PCA85063A
Product data sheet
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Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
20 Appendix
20.1 Real-time clock selection
Table 44. Selection of Real-Time Clocks
Type name
Alarm, Timer,
Watchdog
Interrupt
output
Interface
IDD,
typical (nA)
Battery
backup
Timestamp,
tamper input
AEC-Q100
compliant
Special features
PCF85063TP
-
1
Packages
I C
2
220
-
-
-
basic functions only, no alarm HXSON8
2
PCF85063A
X
1
I C
220
-
-
-
tiny package
SO8, DFN2626-10,
TSSOP8
PCF85063B
X
1
SPI
220
-
-
-
tiny package
DFN2626-10
2
PCF85263A
X
2
I C
230
X
X
-
time stamp, battery backup,
1
stopwatch ⁄100 s
SO8, TSSOP10,
TSSOP8, DFN2626-10
PCF85263B
X
2
SPI
230
X
X
-
time stamp, battery backup,
1
stopwatch ⁄100s
TSSOP10, DFN2626-10
PCF85363A
X
2
I C
230
X
X
-
time stamp, battery backup,
1
stopwatch ⁄100s, 64 Byte
RAM
TSSOP10, TSSOP8,
DFN2626-10
PCF85363B
X
2
SPI
230
X
X
-
time stamp, battery backup,
1
stopwatch ⁄100s, 64 Byte
RAM
TSSOP10, DFN2626-10
PCF2123
X
1
SPI
100
-
-
-
lowest power 100 nA in
operation
TSSOP14, HVQFN16
PCF8523
X
2
I C
2
150
X
-
-
lowest power 150 nA in
operation, FM+ 1 MHz
SO8, HVSON8,
TSSOP14, WLCSP
PCF8563
X
1
I C
2
250
-
-
-
-
SO8, TSSOP8,
HVSON10
PCA8565
X
1
I C
2
600
-
-
grade 1
high robustness,
Tamb= -40 °C to 125 °C
TSSOP8, HVSON10
PCA8565A
X
1
I C
2
600
-
-
-
integrated oscillator caps,
Tamb= -40 °C to 125 °C
WLCSP
PCF8564A
X
1
I C
2
250
-
-
-
integrated oscillator caps
WLCSP
PCA85063A
Product data sheet
2
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 44. Selection of Real-Time Clocks...continued
Type name
Alarm, Timer,
Watchdog
Interrupt
output
Interface
PCF2127
X
1
I C and
SPI
PCF2127A
X
1
I C and
SPI
PCF2129
X
1
I C and
SPI
PCF2129A
X
1
I C and
SPI
PCA2129
X
1
PCA21125
X
1
PCA85063A
Product data sheet
IDD,
typical (nA)
Battery
backup
Timestamp,
tamper input
AEC-Q100
compliant
Special features
2
500
X
X
-
temperature compensated,
SO16
quartz built in, calibrated, 512
Byte RAM
2
500
X
X
-
temperature compensated,
SO20
quartz built in, calibrated, 512
Byte RAM
2
500
X
X
-
temperature compensated,
quartz built in, calibrated
SO16
2
500
X
X
-
temperature compensated,
quartz built in, calibrated
SO20
I C and
SPI
2
500
X
X
grade 3
temperature compensated,
quartz built in, calibrated
SO16
SPI
820
-
-
grade 1
high robustness,
Tamb= -40 °C to 125 °C
TSSOP14
All information provided in this document is subject to legal disclaimers.
Rev. 4.1 — 16 September 2021
Packages
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
21 Abbreviations
Table 45. Abbreviations
Acronym
Description
BCD
Binary Coded Decimal
CMOS
Complementary Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
2
I C
Inter-Integrated Circuit
IC
Integrated Circuit
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
PCB
Printed-Circuit Board
POR
Power-On Reset
RTC
Real-Time Clock
SCL
Serial CLock line
SDA
Serial DAta line
SMD
Surface Mount Device
22 References
[1]
[2]
[3]
[4]
[5]
[6]
[7]
JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM)
JESD22-C101 Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components
JESD78 IC Latch-Up Test
SOT505-1_118 TSSOP8; Reel pack; SMD, 13", packing information
2
UM10204 I C-bus specification and user manual
UM10301 User Manual for NXP Real Time Clocks PCF85x3, PCA8565 and
PCF2123, PCA2125
UM10569 Store and transport requirements
23 Revision history
Table 46. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA85063A v.4.1
20210916
Product data sheet
-
PCA85063A v.4
Modifications:
• Updated Section 4 "Ordering information"
PCA85063A v.4
20180330
Product data sheet
201801008I
PCA85063A v.3
PCA85063A v.3
20160420
Product data sheet
-
PCA85063A v.2
Modifications:
• Clarified reset information in Section 7.2 and Section 7.2.1.3.
PCA85063A
Product data sheet
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Table 46. Revision history...continued
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA85063A v.2
20150601
Product data sheet
-
PCA85063A v.1
PCA85063A v.1
20150407
Objective data sheet
-
-
PCA85063A
Product data sheet
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PCA85063A
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2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
24 Legal information
24.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
24.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
PCA85063A
Product data sheet
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
All information provided in this document is subject to legal disclaimers.
Rev. 4.1 — 16 September 2021
© NXP B.V. 2021. All rights reserved.
52 / 56
PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
24.4 Trademarks
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
I C-bus — logo is a trademark of NXP B.V.
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
2
NXP — wordmark and logo are trademarks of NXP B.V.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
PCA85063A
Product data sheet
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53 / 56
PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Ordering information ..........................................2
Ordering options ................................................2
Pin description ...................................................3
Registers overview ............................................ 5
Control_1 - control and status register 1
(address 00h) bit description .............................7
First increment of time circuits after STOP
bit release ..........................................................8
Registers reset values .....................................10
Control_2 - control and status register 2
(address 01h) bit description ...........................11
Effect of bits MI and HMI on INT generation ....14
CLKOUT frequency selection ..........................15
Offset - offset register (address 02h) bit
description ....................................................... 15
Offset values ................................................... 16
Correction pulses for MODE = 0 ..................... 17
Effect of correction pulses on frequencies
for MODE = 0 ................................................. 17
Correction pulses for MODE = 1 ..................... 18
Effect of correction pulses on frequencies
for MODE = 1 ................................................. 18
RAM_byte - 8-bit RAM register (address
03h) bit description ..........................................20
Seconds - seconds register (address 04h)
bit description .................................................. 20
Seconds coded in BCD format ........................21
Minutes - minutes register (address 05h) bit
description ....................................................... 22
Hours - hours register (address 06h) bit
description ....................................................... 22
Days - days register (address 07h) bit
description ....................................................... 22
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Tab. 31.
Tab. 32.
Tab. 33.
Tab. 34.
Tab. 35.
Tab. 36.
Tab. 37.
Tab. 38.
Tab. 39.
Tab. 40.
Tab. 41.
Tab. 42.
Tab. 43.
Tab. 44.
Tab. 45.
Tab. 46.
Weekdays - weekdays register (address
08h) bit description ..........................................22
Weekday assignments .................................... 23
Months - months register (address 09h) bit
description ....................................................... 23
Month assignments in BCD format ..................23
Years - years register (0Ah) bit description ......24
Second_alarm - second alarm register
(address 0Bh) bit description .......................... 25
Minute_alarm - minute alarm register
(address 0Ch) bit description .......................... 25
Hour_alarm - hour alarm register (address
0Dh) bit description ......................................... 26
Day_alarm - day alarm register (address
0Eh) bit description ......................................... 26
Weekday_alarm - weekday alarm register
(address 0Fh) bit description ...........................26
Timer_value - timer value register (address
10h) bit description ..........................................28
Timer_mode - timer control register
(address 11h) bit description ........................... 28
Timer clock frequency and timer durations ...... 29
First period delay for timer counter value T ..... 30
INT operation .................................................. 30
I2C slave address byte ................................... 33
Limiting values ................................................ 35
Static characteristics ....................................... 35
I2C-bus characteristics ....................................40
SnPb eutectic process (from J-STD-020D) ..... 46
Lead-free process (from J-STD-020D) ............ 46
Selection of Real-Time Clocks ........................ 48
Abbreviations ...................................................50
Revision history ...............................................50
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Block diagram of PCA85063A ...........................2
Pin configuration for TSSOP8
(PCA85063ATT) ................................................ 3
Handling address registers ............................... 4
STOP bit functional diagram ............................. 8
STOP bit release timing .................................. 10
Software reset command ................................ 10
Interrupt scheme ............................................. 13
INT example for MI ......................................... 14
Offset calibration calculation workflow .............19
Result of offset calibration ...............................20
OS flag ............................................................ 21
Data flow for the time function ........................ 24
Access time for read/write operations ............. 24
Alarm function block diagram ..........................27
General countdown timer behavior ................. 29
Bit transfer .......................................................31
Definition of START and STOP conditions ...... 31
System configuration .......................................32
PCA85063A
Product data sheet
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
Acknowledgement on the I2C-bus .................. 32
Master transmits to slave receiver (WRITE
mode) .............................................................. 33
Master reads after setting register address
(write register address; READ data) ................33
Device diode protection diagram of
PCA85063A .....................................................34
Typical IDD with respect to fSCL .....................37
Typical IDD as a function of temperature ........ 38
Typical IDD with respect to VDD ..................... 39
IDD with respect to quartz RS .........................40
Oscillator frequency variation with respect
to VDD ............................................................ 40
I2C-bus timing diagram; rise and fall times
refer to 30 % and 70 % .................................. 42
Application diagram for PCA85063A ............... 42
Package outline SOT505-1 (TSSOP8) of
PCA85063ATT .................................................44
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PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Fig. 31.
Temperature profiles for large and small
components ..................................................... 47
PCA85063A
Product data sheet
Fig. 32.
Footprint information for reflow soldering of
SOT505-1 (TSSOP8) of PCA85063ATT ..........47
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55 / 56
PCA85063A
NXP Semiconductors
2
Automotive tiny Real-Time Clock/calendar with alarm function and I C-bus
Contents
1
2
3
4
4.1
5
6
6.1
6.2
7
7.1
7.2
7.2.1
7.2.1.1
7.2.1.2
7.2.1.3
7.2.2
7.2.2.1
7.2.2.2
7.2.2.3
7.2.2.4
7.2.3
7.2.3.1
7.2.3.2
7.2.3.3
7.2.4
7.3
7.3.1
7.3.1.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.4
7.5
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.6
7.6.1
7.6.2
7.6.3
7.6.3.1
8
8.1
8.2
8.3
General description ............................................ 1
Features and benefits .........................................1
Applications .........................................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Block diagram ..................................................... 2
Pinning information ............................................ 3
Pinning ............................................................... 3
Pin description ................................................... 3
Functional description ........................................3
Registers organization ....................................... 5
Control registers ................................................ 7
Register Control_1 .............................................7
EXT_TEST: external clock test mode ................ 7
STOP: STOP bit function ...................................8
Software reset ................................................. 10
Register Control_2 ...........................................11
Alarm interrupt ................................................. 13
MI and HMI: minute and half minute
interrupt ............................................................14
TF: timer flag ................................................... 14
COF[2:0]: Clock output frequency ................... 15
Register Offset .................................................15
Correction when MODE = 0 ............................ 16
Correction when MODE = 1 ............................ 18
Offset calibration workflow ...............................19
Register RAM_byte ..........................................20
Time and date registers ...................................20
Register Seconds ............................................ 20
OS: Oscillator stop .......................................... 21
Register Minutes ..............................................22
Register Hours .................................................22
Register Days .................................................. 22
Register Weekdays ..........................................22
Register Months .............................................. 23
Register Years ................................................. 24
Setting and reading the time ........................... 24
Alarm registers ................................................ 25
Register Second_alarm ................................... 25
Register Minute_alarm .....................................25
Register Hour_alarm ........................................26
Register Day_alarm ......................................... 26
Register Weekday_alarm .................................26
Alarm function ..................................................27
Timer registers .................................................28
Register Timer_value .......................................28
Register Timer_mode ...................................... 28
Timer functions ................................................ 28
Countdown timer interrupts ..............................30
Characteristics of the I2C-bus interface ......... 31
Bit transfer ....................................................... 31
START and STOP conditions .......................... 31
System configuration ....................................... 31
8.4
8.5
8.5.1
8.5.2
8.5.3
9
10
11
12
13
14
14.1
15
16
17
17.1
18
18.1
18.2
18.3
18.4
19
20
20.1
21
22
23
24
Acknowledge ....................................................32
I2C-bus protocol .............................................. 32
Addressing ....................................................... 32
Clock and calendar READ or WRITE cycles ....33
I2C-bus error recovery technique .................... 34
Internal circuitry ................................................ 34
Safety notes .......................................................34
Limiting values .................................................. 35
Characteristics .................................................. 35
Application information .................................... 42
Test information ................................................ 43
Quality information ...........................................43
Package outline .................................................44
Handling information ........................................ 45
Packing information ..........................................45
Tape and reel information ................................45
Soldering of SMD packages .............................45
Introduction to soldering .............................
Wave and reflow soldering .........................
Wave soldering ...........................................
Reflow soldering .........................................
Footprint information ........................................47
Appendix ............................................................ 48
Real-time clock selection .................................48
Abbreviations .................................................... 50
References ......................................................... 50
Revision history ................................................ 50
Legal information .............................................. 52
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 16 September 2021
Document identifier: PCA85063A
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