PCA85276
Automotive 40 x 4 LCD driver
Rev. 4 — 29 September 2021
1
Product data sheet
General description
The PCA85276 is a peripheral device which interfaces to almost any Liquid Crystal
1
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be
easily cascaded for larger LCD applications. The PCA85276 is compatible with most
2
microcontrollers and communicates via the two-line bidirectional I C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing, and by display memory switching (static and duplex drive
modes).
For a selection of NXP LCD segment drivers, see Table 23.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AEC-Q100 grade 2 compliant for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
1
1
Selectable display bias configuration: static, ⁄2, or ⁄3
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
– Up to 20 7-segment numeric characters
– Up to 10 14-segment alphanumeric characters
– Any graphics of up to 160 segments/elements
40 × 4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
– From 2.5 V for low-threshold LCDs
– Up to 8.0 V for guest-host LCDs and high-threshold twisted nematic LCDs
Low power consumption
Extended temperature range up to 105 °C
2
400 kHz I C-bus interface
May be cascaded for large LCD applications (up to 1 280 segments/elements possible)
No external components required
1 The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21.
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
3
Ordering information
Table 1. Ordering information
Type number
PCA85276ATT/A
Topside
mark
Package
Name
PCA85276TT TSSOP56
Description
Version
plastic thin shrink small outline package, 56 leads;
body width 6.1 mm with 0.5 mm pitch
SOT364-1
3.1 Ordering options
Table 2. Ordering options
Type number
Orderable part
number
PCA85276ATT/A PCA85276ATT/AJ
[2]
PCA85276ATT/AY
[1]
[2]
Package
Packing method
TSSOP56
TSSOP56
[1]
Minimum
order
quantity
Temperature
reel 13 inch q1 non dry
pack
2000
Tamb = -40 °C to +105 °C
reel 13 inch q1 dry pack
2000
Tamb = -40 °C to +105 °C
Standard packing quantities and other packaging data are available at www.nxp.com/ packages/
Discontinuation notice 202107021DN - drop-in replacement is PCA85276ATT/AY - this is documented in PCN202102010F01.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
2 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
4
Block diagram
BP0 BP2 BP1 BP3
S0 to S39
40
VLCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD
VOLTAGE
SELECTOR
VSS
CLK
SYNC
OSC
DISPLAY
CONTROLLER
LCD BIAS
GENERATOR
CLOCK SELECT
AND TIMING
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
RAM
BLINKER
TIMEBASE
COMMAND
DECODER
OSCILLATOR
PCA85276
INPUT
FILTERS
I2C-BUS
CONTROLLER
WRITE DATA
CONTROL
DATA POINTER AND
AUTO INCREMENT
VDD
SCL
SDA
SA0
SUBADDRESS
COUNTER
T1
A0
A1
aaa-009319
Figure 1. Block diagram of PCA85276
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
3 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
5
Pinning information
5.1 Pinning
BP2 1
56 BP0
BP1 2
55 VLCD
BP3 3
54 VSS
S0 4
53 SA0
S1 5
52 T1
S2 6
51 A1
S3 7
50 A0
S4 8
49 OSC
S5 9
48 VDD
S6 10
47 CLK
S7 11
46 SYNC
S8 12
45 SCL
S9 13
44 SDA
S10 14
S11 15
PCA85276ATT
43 S39
42 S38
S12 16
41 S37
S13 17
40 S36
S14 18
39 S35
S15 19
38 S34
S16 20
37 S33
S17 21
36 S32
S18 22
35 S31
S19 23
34 S30
S20 24
33 S29
S21 25
32 S28
S22 26
31 S27
S23 27
30 S26
S24 28
29 S25
aaa-009320
Top view. For mechanical details, see Figure 28.
Figure 2. Pinning diagram for PCA85276ATT (TSSOP56)
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
4 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
5.2 Pin description
Table 3. Pin description of PCA85276ATT (TSSOP56)
Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise
specified.
Symbol
6
Pin
Description
PCA85276ATT
Type
SDA
44
input/output
I C-bus serial data line
SCL
45
input
I C-bus serial clock
CLK
47
input/output
clock line
VDD
48
supply
supply voltage
SYNC
46
input/output
cascade synchronization; if not
used it must be left open
OSC
49
input
internal oscillator enable
A0, A1
50, 51
input
subaddress inputs
T1
52
input
dedicated testing pin; to be tied to
VSS in application mode
SA0
53
input
I C-bus address input
VSS
54
supply
ground supply voltage
VLCD
55
supply
LCD supply voltage
BP0, BP2,
BP1, BP3
56, 1, 2, 3
output
LCD backplane outputs
S0 to S39
4 to 43
output
LCD segment outputs
2
2
2
Functional description
The PCA85276 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot-matrix displays. It can directly
drive any static or multiplexed LCD containing up to four backplanes and up to 40
segments.
6.1 Commands of PCA85276
The commands available to the PCA85276 are defined in Table 4.
Table 4. Definition of the PCA85276 commands
Bit position labeled as - is not used.
PCA85276
Product data sheet
Command
Operation Code
Bit
7
6
5
4
3
2
1
mode-set
C
1
0
-
E
B
M[1:0]
load-data-pointer
C
0
P[5:0]
device-select
C
1
1
0
0
0
A[1:0]
bank-select
C
1
1
1
1
0
I
blink-select
C
1
1
1
0
AB
BF[1:0]
Reference
0
Table 6
Table 7
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
Table 8
O
Table 9
Table 10
© NXP B.V. 2021. All rights reserved.
5 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
All available commands carry a continuation bit C in their most significant bit position
as shown in Figure 21. When this bit is set logic 1, it indicates that the next byte of the
transfer to arrive will also represent a command. If this bit is set logic 0, it indicates that
the command byte is the last in the transfer. Further bytes are regarded as display data
(see Table 5).
Table 5. C bit description
Bit
Symbol
7
C
Value
Description
continue bit
0
last control byte in the transfer; next byte will be
regarded as display data
1
control bytes continue; next byte will be a command too
6.1.1 Command: mode-set
The mode-set command allows configuring the multiplex mode, the bias levels and
enabling or disabling the display.
Table 6. Mode-set command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 5
6 to 5
-
10
fixed value
4
-
-
unused
3
E
2
[2]
0
disabled (blank)
1
enabled
[3]
LCD bias configuration
B
1 to 0
[1]
[2]
[3]
[1]
display status
0
1
⁄3 bias
1
1
⁄2 bias
LCD drive mode selection
M[1:0]
01
static; BP0
10
1:2 multiplex; BP0, BP1
11
1:3 multiplex; BP0, BP1, BP2
00
1:4 multiplex; BP0, BP1, BP2, BP3
The possibility to disable the display allows implementation of blinking under external control.
The display is disabled by setting all backplane and segment outputs to VLCD.
Not applicable for static drive mode.
6.1.2 Command: load-data-pointer
The load-data-pointer command defines the display RAM address where the following
display data are sent to.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
6 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 7. Load-data-pointer command bit description
See Section 6.3.1.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 5
6
-
0
fixed value
5 to 0
P[5:0]
00 0000 to
10 0111
6-bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
6.1.3 Command: device-select
The device-select command allows defining the subaddress counter value.
Table 8. Device-select command bit description
See Section 6.3.2.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 5
6 to 2
-
110 00
fixed value
1 to 0
A[1:0]
00 to 11
2-bit binary value, 0 to 3; transferred to the subaddress
counter to define one of four hardware subaddresses
6.1.4 Command: bank-select
The bank-select command controls where data is written to RAM and where it is
displayed from.
Table 9. Bank-select command bit description
See Section 6.3.5.
Bit
Symbol
Value
Description
Static
7
C
0, 1
see Table 5
6 to 2
-
111 10
fixed value
1
I
0
[1]
1:2 multiplex
[1]
input bank selection; storage of arriving display data
0
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
output bank selection; retrieval of LCD display data
O
0
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
6.1.5 Command: blink-select
The blink-select command allows configuring the blink mode and the blink frequency.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
7 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 10. Blink-select command bit description
See Section 6.1.5.1.
Bit
Symbol
Value
Description
7
C
0, 1
see Table 5
6 to 3
-
111 0
fixed value
2
AB
1 to 0
[1]
[2]
blink mode selection
[1]
0
normal blinking
1
alternate RAM bank blinking
[2]
blink frequency selection
BF[1:0]
00
off
01
1
10
2
11
3
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
6.1.5.1 Blinking
The display blinking capabilities of the PCA85276 are very versatile. The whole display
can blink at frequencies selected by the blink-select command (see Table 10). The blink
frequencies are derived from the clock frequency. The ratio between the clock and blink
frequencies depends on the blink mode selected (see Table 11).
An additional feature is for an arbitrary selection of LCD segments/elements to blink.
This applies to the static and 1:2 multiplex drive modes and can be implemented without
any communication overheads. With the output bank selector, the displayed RAM banks
are exchanged with alternate RAM banks at the blink frequency. This mode can also be
specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternative RAM bank is available, groups
of LCD segments/elements can blink by selectively changing the display RAM data at
fixed time intervals.
The entire display can blink at a frequency other than the nominal blink frequency. This
can be effectively performed by resetting and setting the display enable bit E at the
required rate using the mode-set command (see Table 6).
Table 11. Blink frequencies
Blink mode
Blink frequency
off
-
[1]
1
2
3
[1]
PCA85276
Product data sheet
The blink frequency is proportional to the clock frequency (fclk). For the range of the clock frequency, see Table 19.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
8 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
6.2 Clock and frame frequency
6.2.1 Internal clock
The internal logic of the PCA85276 and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used
as the clock signal for several PCA85276 in the system that are connected in cascade.
6.2.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD
frame frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
6.2.3 Timing
The PCA85276 timing controls the internal data flow of the device. This includes
the transfer of display data from the display RAM to the display segment outputs. In
cascaded applications, the correct timing relationship between each PCA85276 in
the system is maintained by the synchronization signal at pin SYNC. The timing also
generates the LCD frame frequency signal. The frame frequency signal is a fixed division
of the clock frequency from either the internal or an external clock:
6.3 Display RAM
The display RAM is a static 40 × 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD segments/elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bitmap, Figure 3, shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the
first, second, third, and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
9 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
35
36
37
38
39
0
display RAM bits
1
(rows)/
backplane outputs
2
(BP)
3
mbe525
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Figure 3. Display RAM bitmap
When display data is transmitted to the PCA85276, the display bytes received are
stored in the display RAM in accordance with the selected LCD drive mode. The data
is stored as it arrives and depending on the current multiplex drive mode the bits are
stored singularly, in pairs, triples, or quadruples. To illustrate the filling order, an example
of a 7-segment display showing all drive modes is given in Figure 4; the RAM filling
organization depicted applies equally to other LCD types.
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into row 0
and 1 as four successive 2-bit RAM words
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 6.3.3)
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
10 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
drive mode
LCD segments
Sn+2
static
Sn+3
a
multiplex
e
c
Sn
Sn+1
BP0
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
DP
b
f
e
Sn+2
BP1
c
DP
d
Sn+1
b
f
Sn
BP1
c
a
b
BP0
g
e
BP1
c
d
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
MSB
LSB
c b a
f
g e d DP
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
n
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
MSB
a b
LSB
f
g e c d DP
n
rows
display RAM 0 b
rows/backplane
1 DP
outputs (BP)
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
f
Sn+1
BP2
DP
d
multiplex
n+3
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
g
Sn
n+2
BP0
a
e
n+1
columns
display RAM address/segment outputs (s)
byte1
byte2
g
Sn+2
transmitted display byte
n
BP0
a
multiplex
1:4
Sn+1
Sn
Sn+7
d
Sn+3
1:3
b
g
Sn+6
1:2
display RAM filling order
columns
display RAM address/segment outputs (s)
byte1
f
Sn+4
Sn+5
LCD backplanes
DP
BP2
n
rows
display RAM 0 a
rows/backplane
1 c
BP3 outputs (BP) 2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged.
2
Figure 4. Relationship between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I C-bus
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
11 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
6.3.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 7). Following this command,
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in Figure 4.
After each byte is stored, the content of the data pointer is automatically incremented by
a value dependent on the selected LCD drive mode:
•
•
•
•
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
2
If an I C-bus data access terminates early, then the state of the data pointer is unknown.
So, the data pointer must be rewritten prior to further RAM accesses.
6.3.2 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0 and A1. The subaddress counter value is defined
by the device-select command (see Table 8). If the content of the subaddress counter
and the hardware subaddress do not match, then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is
also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCA85276 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on
2
the I C-bus interface.
6.3.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 12 (see Figure 4 as
well).
Table 12. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the
display.
PCA85276
Product data sheet
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
12 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 12. Standard RAM filling in 1:3 multiplex drive mode...continued
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any segments/elements on the
display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 13.
Table 13. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to segments/elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
c1/d7 d4
d1/e7 e4
:
1
a6
a3
a0/b6 b3
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
2
a5
a2
b5
b2
c5
c2
d5
d2
e5
e2
:
3
-
-
-
-
-
-
-
-
-
-
:
3
4
5
6
7
8
9
:
In the case described in Table 13 the RAM has to be written entirely and BP2/S2, BP2/
S5, BP2/S8 etc. have to be connected to segments/elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written
• The data-pointer (see Section 6.3.1) has to be set to the address of bit a1
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7 and
b6
• The data-pointer has to be set to the address of bit b1
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and c6
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some segments/elements remain unused or can be used, but it has to be considered in
the module layout process as well as in the driver software design.
6.3.4 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible
to fill the RAM over the RAM address boundary. If the PCA85276 is part of a cascade
the additional bits fall into the next device that also generates the acknowledge signal. If
the PCA85276 is a single device or the last device in a cascade, the additional bits are
discarded and no acknowledge signal is generated.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
13 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
6.3.5 Bank selection
6.3.5.1 Output bank selector
The output bank selector (see Table 9) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, followed by the
contents of row 1, row 2, and then row 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
6.3.5.2 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded by using the bank-select
command (see Table 9). The input bank selector functions independently to the output
bank selector.
6.3.5.3 RAM bank switching
The PCA85276 includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. A bank can be thought of as one RAM row or a collection of RAM rows (see
Figure 5). The RAM bank switching gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it is complete.
display RAM addresses (columns)/segment outputs (S)
Static drive mode
display RAM bits (rows)/backplane outputs (BP)
0
1
2
3
4
35
36
37
38
39
bank 0
0
1
bank 1
2
3
Multiplex drive mode 1:2
0
1
2
3
4
35
0
36
37
38
39
bank 0
1
2
bank 1
3
aaa-004787
Figure 5. RAM banks in static and multiplex driving mode 1:2
There are two banks; bank 0 and bank 1. Figure 5 shows the location of these banks
relative to the RAM map. Input and output banks can be set independently from one
another with the Bank-select command (see Table 9). Figure 6 shows the concept.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
14 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
input bank selection
controls the input
data path
output bank selection
controls the output
data path
BANK 0
MICROCONTROLLER
DISPLAY
RAM
BANK 1
aaa-004656
Figure 6. Bank selection
In the static drive mode, the bank-select command may request the contents of row 2
to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode,
the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
In Figure 7 an example is shown for 1:2 multiplex drive mode where the displayed data is
read from the first two rows of the memory (bank 0), while the transmitted data is stored
in the second two rows of the memory (bank 1).
columns
display RAM columns/segment outputs (S)
0
1
2
3
4
5
6
7
35 36 37 38 39
0
1
rows
output RAM bank
to the LCD
display RAM rows/
backplane outputs 2
(BP)
3
to the RAM
input RAM bank
aaa-004788
Figure 7. Example of the Bank-select command with multiplex drive mode 1:2
6.4 Initialization
2
At power-on the status of the I C-bus and the registers of the PCA85276 is undefined.
Therefore the PCA85276 should be initialized as quickly as possible after power-on
to ensure a proper bus communication and to avoid display artifacts. The following
instructions should be accomplished for initialization:
6.4.1 Device initialization
2
At power-on the status of the I C-bus communication interface is undefined since this
device doesn’t have POR which was removed to improve the ESD performance. A
START and STOP condition with dummy byte in-between must be sent after every power
2
reset to set up the I C-bus communication interface.
2
• I C-bus (see Section 7) initialization
– generating a START condition
– sending 0h (1 byte) and ignoring the acknowledge – Note, this is not the device
address but just a dummy byte of all zeros
– generating a STOP condition
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
15 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
6.4.2 Device setup
At power-on the status of the display and configuration registers are undefined and
2
need to be set up to properly display information on the LCD display. After the I C-bus
interface is initialized as discussed in Section 6.4.1 set up the device using these register
settings
• Mode-set command (see Table 6), setting
– bit E = 0
– bit B to the required LCD bias configuration
– bits M[1:0] to the required LCD drive mode
• Load-data-pointer command (see Table 7), setting
– bits P[4:0] to 0h (or any other required address)
• Device-select command (see Table 8), setting
– bits A[1:0] to the required hardware subaddress (for example, 0h)
• Bank-select command (see Table 9), setting
– bit I to 0
– bit O to 0
• Blink-select command (see Table 10), setting
– bit AB to 0 or 1
– bits BF[1:0] to 00 (or to a desired blinking mode)
• writing meaningful information (for example, a logo) into the display RAM
• After the initialization, the display can be switched on by setting bit E = 1 with the
mode-set command or left off (blank) with bit E = 0.
6.5 Possible display configurations
The possible display configurations of the PCA85276 depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 14. All
of these configurations can be implemented in the typical system shown in Figure 9.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Figure 8. Example of displays suitable for PCA85276
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
16 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 14. Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment
[1]
[2]
14-segment
Dot matrix:
segments/
elements
4
160
20
10
160 (4 × 40)
3
120
15
7
120 (3 × 40)
2
80
10
5
80 (2 × 40)
1
40
5
2
40 (1 × 40)
[1]
[2]
7 segment display has 8 segments/elements including the decimal point.
14 segment display has 16 segments/elements including decimal point and accent dot.
VDD
R≤
tr
2CB
VDD
VLCD
40 segment drives
SDA
HOST
MICROCONTROLLER
LCD PANEL
SCL
PCA85276
OSC
A0
A1
T1
4 backplanes
(up to 160
elements)
SA0 VSS
VSS
aaa-009321
The resistance of the power lines must be kept to a minimum.
Figure 9. Typical system configuration
2
The host microcontroller maintains the 2-line I C-bus communication channel with the
PCA85276. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are the power supplies (VDD,
VSS, and VLCD) and the LCD panel chosen for the application.
6.5.1 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between VLCD and VSS. The center impedance is bypassed
1
by switch if the ⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected.
6.5.2 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
6.5.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with
the selected LCD drive configuration. The operation of the voltage selector is controlled
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
17 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
by the mode-set command from the command decoder. The biasing configurations that
apply to the preferred modes of operation, together with the biasing characteristics as
functions of VLCD and the resulting discrimination ratios (D) are given in Table 15.
Discrimination is a term which is defined as the ratio of the on and off RMS voltage
across a segment. It can be thought of as a measurement of contrast.
Table 15. Biasing characteristics
LCD drive
mode
Number of:
static
1
Backplanes Levels
1:2 multiplex 2
1:2 multiplex 2
1:3 multiplex 3
1:4 multiplex 4
LCD bias
configuration
2
static
0
1
∞
3
1
0.354
0.791
2.236
4
1
0.333
0.745
2.236
4
1
0.333
0.638
1.915
4
1
0.333
0.577
1.732
⁄2
⁄3
⁄3
⁄3
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast.
In the static drive mode a suitable choice is VLCD > 3Vth(off).
1
Multiplex drive modes of 1:3 and 1:4 with ⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
Bias is calculated by
, where the values for a are
1
a = 1 for ⁄2 bias
1
a = 2 for ⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
(3)
1
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with ⁄2 bias
PCA85276
Product data sheet
1
is
and the discrimination for an LCD drive mode of 1:4 multiplex with ⁄2 bias
is
.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
18 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage
VLCD as follows:
•
•
1
1:3 multiplex ( ⁄2 bias):
1
1:4 multiplex ( ⁄2 bias):
1
These compare with
when ⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
6.5.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 10. For a good contrast performance, the following rules should be followed:
(4)
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the
selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
100 %
Relative Transmission
90 %
10 %
Vth(off)
OFF
SEGMENT
Vth(on)
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
013aaa494
Figure 10. Electro-optical characteristic: relative transmission curve of the liquid
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
19 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
6.5.4 LCD drive mode waveforms
6.5.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
The backplane (BPn) and segment (Sn) drive waveforms for this mode are shown in
Figure 11.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
- VLCD
VLCD
state 2
0V
- VLCD
(b) Resultant waveforms
at LCD segment.
013aaa207
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn + 1)(t) - VBP0(t).
Voff(RMS) = 0 V.
Figure 11. Static drive mode waveforms
6.5.4.2 1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
1
1
PCA85276 allows the use of ⁄2 bias or ⁄3 bias in this mode as shown in Figure 12 and
Figure 13.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
20 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Tfr
VLCD
BP0
LCD segments
VLCD/2
VSS
state 1
VLCD
BP1
state 2
VLCD/2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD/2
state 1
0V
- VLCD/2
- VLCD
VLCD
VLCD/2
state 2
0V
- VLCD/2
- VLCD
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) - VBP1(t).
Voff(RMS) = 0.354VLCD.
013aaa208
1
Figure 12. Waveforms for the 1:2 multiplex drive mode with ⁄2 bias
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
21 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Tfr
VLCD
BP0
BP1
LCD segments
2VLCD/3
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
Sn
2VLCD/3
VLCD/3
VSS
VLCD
Sn+1
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
state 1
VLCD/3
0V
- VLCD/3
- 2VLCD/3
- VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
- VLCD/3
- 2VLCD/3
- VLCD
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t) - VBP1(t).
Voff(RMS) = 0.333VLCD.
013aaa209
1
Figure 13. Waveforms for the 1:2 multiplex drive mode with ⁄3 bias
6.5.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as
shown in Figure 14.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
22 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
BP0
VLCD
2VLCD/3
Tfr
LCD segments
VLCD/3
VSS
state 1
VLCD
BP1
BP2
Sn
Sn+1
Sn+2
state 2
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
state 1
2VLCD/3
VLCD/3
0V
- VLCD/3
- 2VLCD/3
- VLCD
VLCD
2VLCD/3
state 2
VLCD/3
0V
- VLCD/3
- 2VLCD/3
- VLCD
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) - VBP1(t).
Voff(RMS) = 0.333VLCD.
013aaa210
1
Figure 14. Waveforms for the 1:3 multiplex drive mode with ⁄3 bias
6.5.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies as
shown in Figure 15.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
23 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
BP0
VLCD
2VLCD/3
VLCD/3
VSS
BP1
VLCD
2VLCD/3
VLCD/3
VSS
BP2
VLCD
2VLCD/3
VLCD/3
VSS
BP3
VLCD
2VLCD/3
VLCD/3
VSS
Sn
VLCD
2VLCD/3
VLCD/3
VSS
Sn+1
VLCD
2VLCD/3
VLCD/3
VSS
Sn+2
VLCD
2VLCD/3
VLCD/3
VSS
Sn+3
VLCD
2VLCD/3
VLCD/3
VSS
state 1
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
state 2
VLCD
2VLCD/3
VLCD/3
0V
-VLCD/3
-2VLCD/3
-VLCD
Tfr
LCD segments
state 1
state 2
(a) Waveforms at driver.
(b) Resultant waveforms
at LCD segment.
Vstate1(t) = VSn(t) - VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) - VBP1(t).
Voff(RMS) = 0.333VLCD.
013aaa211
1
Figure 15. Waveforms for the 1:4 multiplex drive mode with ⁄3 bias
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
24 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
6.6 Backplane and segment outputs
6.6.1 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must
be connected directly to the LCD. The backplane output signals are generated in
accordance with the selected LCD drive mode. If less than four backplane outputs are
required, the unused outputs can be left open-circuit.
• In 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities
• In 1:2 multiplex drive mode, BP0 and BP2, respectively, BP1 and BP3 all carry the
same signals and may also be paired to increase the drive capabilities
• In static drive mode, the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements
6.6.2 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display register.
When less than 40 segment outputs are required, the unused segment outputs should be
left open-circuit.
7
2
Characteristics of the I C-bus
2
The I C-bus is for bidirectional, two-line communication between different ICs or
modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both
lines must be connected to a positive supply via a pull-up resistor when connected to the
output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time is interpreted as a control signal (see Figure 16).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Figure 16. Bit transfer
7.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the
START condition - S.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
25 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P.
The START and STOP conditions are illustrated in Figure 17.
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc 622
Figure 17. Definition of START and STOP conditions
7.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the controller and the devices which
are controlled by the controller are the targets. The system configuration is shown in
Figure 18.
CONTROLLER
TRANSMITTER/
RECEIVER
TARGET
RECEIVER
TARGET
TRANSMITTER/
RECEIVER
CONTROLLER
TRANSMITTER
CONTROLLER
TRANSMITTER/
RECEIVER
SDA
SCL
mga807
Figure 18. System configuration
7.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A target receiver, which is addressed, must generate an acknowledge after the
reception of each byte
• A controller receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the target transmitter
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered)
• A controller receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the target. In this event, the
transmitter must leave the data line HIGH to enable the controller to generate a STOP
condition
2
Acknowledgement on the I C-bus is illustrated in Figure 19.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
26 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL
from controller
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
2
Figure 19. Acknowledgement of the I C-bus
2
7.5 I C-bus controller
2
2
The PCA85276 acts as an I C-bus target receiver. It does not initiate I C-bus transfers or
2
transmit data to an I C-bus controller receiver. The only data output from the PCA85276
are the acknowledge signals of the selected devices. Device selection depends on
2
the I C-bus target address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0 and A1 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device applications A0
and A1 are tied to VSS or VDD using a binary coding scheme, so that no two devices with
2
a common I C-bus target address have the same hardware subaddress.
7.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
2
7.7 I C-bus protocol
2
Two I C-bus target addresses (0111 000 and 0111 001) are used to address the
2
PCA85276. The entire I C-bus target address byte is shown in Table 16.
2
Table 16. I C target address byte
target address
Bit
7
6
5
4
3
2
0
1
MSB
0
LSB
1
1
1
0
0
SA0
R/W
The PCA85276 is a write-only device and will not respond to a read access, therefore bit
0 should always be logic 0. Bit 1 of the target address byte that a PCA85276 will respond
to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1).
2
Having two reserved target addresses allows the following on the same I C-bus:
• Up to 8 PCA85276 for very large LCD applications
• The use of two types of LCD multiplex drive modes
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
27 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
2
The I C-bus protocol is shown in Figure 20. The sequence is initiated with a START
2
condition (S) from the I C-bus controller which is followed by one of the two possible
PCA85276 target addresses available. All PCA85276 whose SA0 inputs correspond to
2
bit 0 of the target address respond by asserting an acknowledge in parallel. This I C-bus
transfer is ignored by all PCA85276 whose SA0 inputs are set to the alternative level.
acknowledge
by A0 and A1
selected
PCA85276 only
acknowledge by
all addressed
PCA85276
R/W
target address
S
S
0 1 1 1 0 0 A 0 A C
0
1 byte
COMMAND
A
n ≥ 1 byte(s)
DISPLAY DATA
A
P
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
aaa-009328
2
Figure 20. I C-bus protocol
After an acknowledgement, one or more command bytes follow that define the status of
each addressed PCA85276.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C (see Figure 21). The command bytes are also acknowledged by all addressed
PCA85276 on the bus.
MSB
C
LSB
REST OF OPCODE
msa833
Figure 21. Format of command byte
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and
the subaddress counter. Both data pointer and subaddress counter are automatically
updated and the data directed to the intended PCA85276 device.
An acknowledgement after each byte is asserted only by the PCA85276 that are
2
addressed via address lines A0 and A1. After the last display byte, the I C-bus controller
2
asserts a STOP condition (P). Alternately a START may be asserted to restart an I C-bus
access.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
28 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
8
Internal circuitry
VDD
VDD
VSS
VSS
SA0
VDD
CLK
SCL
VSS
VDD
VSS
OSC
VSS
VDD
SDA
SYNC
VSS
VSS
VDD
A0, A1, T1
VSS
VLCD
BP0, BP1,
BP2, BP3
VSS
VLCD
VLCD
S0 to S39
VSS
VSS
mdb076
Figure 22. Device protection circuits
9
Safety notes
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe
precautions for handling electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5,
JESD625-A or equivalent standards.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
29 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
CAUTION
Static voltages across the liquid crystal display can build up when the LCD
supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice
versa. This may cause unwanted display artifacts. To avoid such artifacts,
VLCD and VDD must be applied or removed together.
10 Limiting values
Table 17. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
Min
Max
Unit
supply voltage
-0.5
+6.5
V
VLCD
LCD supply voltage
-0.5
+9.0
V
VI
input voltage
on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0, A1, T1
-0.5
+6.5
V
VO
output voltage
on each of the pins S0 to
S39, BP0 to BP3
-0.5
+9.0
V
II
input current
-10
+10
mA
IO
output current
-10
+10
mA
IDD
supply current
-50
+50
mA
IDD(LCD)
LCD supply current
-50
+50
mA
ISS
ground supply current
-50
+50
mA
Ptot
total power dissipation
-
400
mW
Po
output power
VESD
Ilu
electrostatic discharge
voltage
latch-up current
Tstg
storage temperature
Tamb
ambient temperature
[1]
[2]
[3]
[4]
Conditions
-
100
mW
HBM
[1]
-
±5 000
V
CDM
[2]
-
±2 000
V
VLU = 11.5 V
[3]
-
200
mA
[4]
-55
+150
°C
-40
+105
°C
operating device
Pass level; Human Body Model (HBM), according to [1]
Pass level; Charged-Device Model (CDM), according to [2]
Pass level; latch-up testing according to [3] at maximum ambient temperature (Tamb(max)).
According to the store and transport requirements (see [5]) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to
75 %.
11 Static characteristics
Table 18. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = -40 °C to +105 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
supply voltage
VLCD ≤ 6.5 V
1.8
-
5.5
V
VLCD > 6.5 V
2.5
-
5.5
V
Supplies
VDD
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
30 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 18. Static characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = -40 °C to +105 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VLCD
LCD supply voltage
VDD < 2.5 V
2.5
-
6.5
V
2.5
-
8.0
V
-
3.5
7
μA
-
2.7
-
μA
-
23
32
μA
-
13
-
μA
VSS
-
0.3VDD
V
0.7VDD
-
VDD
V
on pins CLK and SYNC
1
-
-
mA
on pin SDA
3
-
-
mA
VDD ≥ 2.5 V
IDD
supply current
fclk(ext) = 1536 Hz
[1][2]
VDD = 3.0 V; Tamb = 25
°C
IDD(LCD)
LCD supply current
[1]
fclk(ext) = 1536 Hz
VLCD = 3.0 V; Tamb = 25
°C
[3]
Logic
VIL
LOW-level input voltage
on pins CLK, SYNC, OSC,
A0, A1, T1, SA0, SCL, SDA
VIH
HIGH-level input voltage
on pins CLK, SYNC, OSC,
A0, A1, T1, SA0, SCL, SDA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V; VDD = 5 V
[4][5]
IOH(CLK)
HIGH-level output current
on pin CLK
output source current;
VOH = 4.6 V; VDD = 5 V
1
-
-
mA
IL
leakage current
VI = VDD or VSS;
on pins CLK, SCL, SDA, A0,
A1, T1, SA0
-1
-
+1
μA
IL(OSC)
leakage current on pin
OSC
VI = VDD
-1
-
+1
μA
CI
input capacitance
-
-
7
pF
-100
-
+100
mV
on pins BP0 to BP3
-
1.5
-
kΩ
on pins S0 to S39
-
6.0
-
kΩ
[6]
LCD outputs
ΔVO
output voltage variation
on pins BP0 to BP3 and
S0 to S39
RO
output resistance
VLCD = 5 V
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[7]
2
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I C-bus inactive.
For typical values, see Figure 23.
2
The I C-bus interface of the PCA85276 is 5 V tolerant.
2
When tested, I C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 17 (see Figure 22 as well).
Propagation delay of driver between clock (CLK) and LCD driving signals.
Periodically sampled, not 100 % tested.
Outputs measured one at a time.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
31 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
001aal523
5
IDD
(µA)
4
3
2
1
0
2
3
4
5
VDD (V)
6
Tamb = 30 °C; 1:4 multiplex drive mode; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with
2
logic 1; no display connected; I C-bus inactive.
Figure 23. Typical IDD with respect to VDD
12 Dynamic characteristics
Table 19. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = -40 °C to +105 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3 505
4 800
6 240
Hz
960
-
6 720
Hz
internal clock
146
200
260
Hz
external clock
40
-
280
Hz
Clock
fclk(int)
internal clock frequency
fclk(ext)
external clock frequency
ffr
frame frequency
[1]
tclk(H)
HIGH-level clock time
60
-
-
μs
tclk(L)
LOW-level clock time
60
-
-
μs
-
30
-
ns
1
-
-
μs
-
-
30
μs
Synchronization
tPD(SYNC_N) SYNC propagation delay
tSYNC_NL
tPD(drv)
2
SYNC LOW time
driver propagation delay
VLCD = 5 V
[2]
[3]
I C-bus
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL
clock
1.3
-
-
μs
tHIGH
HIGH period of the SCL
clock
0.6
-
-
μs
Pin SDA
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
32 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 19. Dynamic characteristics...continued
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = -40 °C to +105 °C; unless otherwise specified.
Symbol
Parameter
tSU;DAT
tHD;DAT
Conditions
Min
Typ
Max
Unit
data set-up time
100
-
-
ns
data hold time
0
-
-
ns
Pins SCL and SDA
tBUF
bus free time between
a STOP and START
condition
1.3
-
-
μs
tSU;STO
set-up time for STOP
condition
0.6
-
-
μs
tHD;STA
hold time (repeated)
START condition
0.6
-
-
μs
tSU;STA
set-up time for a repeated
START condition
0.6
-
-
μs
tr
rise time of both SDA and
SCL signals
fSCL = 400 kHz
-
-
0.3
μs
fSCL < 125 kHz
-
-
1.0
μs
tf
fall time of both SDA and
SCL signals
-
-
0.3
μs
Cb
capacitive load for each
bus line
-
-
400
pF
tw(spike)
spike pulse width
-
-
50
ns
[1]
[2]
[3]
2
on the I C-bus
Typical output duty factor: 50 % measured at the CLK output pin.
Not tested in production.
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage
swing of VSS to VDD.
tclk(H)
1 / fclk
tclk(L)
0.7 VDD
CLK
0.3 VDD
0.7 VDD
SYNC
0.3 VDD
tPD(SYNC_N)
tSYNC_NL
10 %
80 %
BPn, Sn
10 %
tPD(drv)
013aaa298
Figure 24. Driver timing waveforms
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
33 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
(1) Configured as Controller when OSC is connected to VSS
(2) Configured as Target when OSC is connected to VDD
mga728
2
Figure 25. I C-bus timing waveforms
13 Application information
13.1 Cascaded operation
2
Large display configurations of up to 8 PCA85276 can be recognized on the same I C2
bus by using the 2-bit hardware subaddress (A0 and A1) and the programmable I C-bus
target address (SA0).
Table 20. Addressing cascaded PCA85276
Cluster
Bit SA0
Pin A1
Pin A0
Device
1
0
0
0
0
0
1
1
1
0
2
1
1
3
0
0
4
0
1
5
1
0
6
1
1
7
2
1
When cascaded PCA85276 are synchronized, they can share the backplane signals
from one of the devices in the cascade. The other PCA85276 of the cascade contribute
additional segment outputs. The backplanes can either be connected together to
enhance the drive capability or some can be left open-circuit (such as the ones from the
target in Figure 26) or just some of the controller and some of the target will be taken to
facilitate the layout of the PCB.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
34 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
VDD
VLCD
SDA
40 segment drives
SCL
SYNC
PCA85276
CLK
(2)
BP0 to BP3
(open-circuit)
OSC
A0
A1
T1
SA0 VSS
LCD PANEL
VLCD
VDD
R≤
tr
2Cb
VDD
VLCD
40 segment drives
SDA
SCL
HOST
MICROCONTROLLER
SYNC
PCA85276
CLK
(1)
OSC
A0
VSS
A1
T1
1. Is controller (OSC connected to VSS).
2. Is target (OSC connected to VDD).
4 backplanes
BP0 to BP3
SA0 VSS
aaa-009329
Figure 26. Cascaded PCA85276 configuration
The SYNC line is provided to maintain the correct synchronization between all cascaded
PCA85276. Synchronization is guaranteed after a power-on and initialization. The only
time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by
noise in adverse electrical environments or by defining a multiplex drive mode when
PCA85276 with different SA0 levels are cascaded).
SYNC is organized as an input/output pin. The output selection is realized as an opendrain driver with an internal pull-up resistor. A PCA85276 asserts the SYNC line at the
onset of its last active backplane signal and monitors the SYNC line at all other times.
If synchronization in the cascade is lost, it is restored by the first PCA85276 to assert
SYNC. The timing relationship between the backplane waveforms and the SYNC signal
for the various drive modes of the PCA85276 are shown in Figure 27.
The PCA85276 can always be cascaded with other devices of the same type or
conditionally with other devices of the same family. This allows optimal drive selection for
a given number of pixels to display. Figure 27 shows the timing of the synchronization
signals.
Only one controller but multiple targets are allowed in a cascade. All devices in the
cascade have to use the same clock whether it is supplied externally or provided by the
controller.
If an external clock source is used, all PCA85276 in the cascade must be configured
such as to receive the clock from that external source (pin OSC connected to VDD).
Thereby it must be ensured that the clock tree is designed such that on all PCA85276
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
35 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
the clock propagation delay from the clock source to all PCA85276 in the cascade is as
equal as possible since otherwise synchronization artifacts may occur.
In mixed cascading configurations, care has to be taken that the specifications of the
individual cascaded devices are always met.
Tfr =
1
ffr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Figure 27. Synchronization of the cascade for the various PCA85276 drive modes
14 Test information
14.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
36 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
15 Package outline
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
E
D
A
X
c
HE
y
v M A
Z
56
29
Q
A2
(A 3 )
A1
pin 1 index
A
θ
Lp
L
1
28
w M
bp
e
detail X
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
14.1
13.9
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.5
0.1
8
o
0
o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT364-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Figure 28. Package outline SOT364-1 (TSSOP56) of PCA85276ATT
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
37 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
16 Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
17 Packing information
17.1 Tape and reel information
For tape and reel packing information, please see [4].
18 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
18.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
18.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
38 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
18.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
18.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 29) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 21 and Table 22
Table 21. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 22. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
39 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 29.
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 29. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
40 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
19 Footprint information
Footprint information for reflow soldering of TSSOP56 package
SOT364-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
0.500
0.560
8.900
6.100
1.400
0.280
D2
Gx
0.400 14.270
Gy
Hx
Hy
7.000 16.600 9.150
sot364-1_fr
Figure 30. Footprint information for reflow soldering of SOT364-1 (TSSOP56) of PCA85276ATT
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
41 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
20 Appendix
20.1 LCD segment driver selection
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
42 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 23. Selection of LCD segment drivers
Type name
PCA8553DTT
PCA8546ATT
PCA8546BTT
PCA8547AHT
PCA8547BHT
PCF85134HL
PCA85134H
PCA8543AHL
PCF8545ATT
PCF8545BTT
PCF8536AT
PCF8536BT
PCA8536AT
PCA8536BT
PCF8537AH
PCF8537BH
PCA8537AH
PCA8537BH
PCA9620H
PCA9620U
PCF8576DU
PCF8576EUG
PCA8576FUG
PCF85133U
PCA85276
Product data sheet
Number of elements at MUX
1:1
1:2
1:3
1:4
1:6
1:8
1:9
40
80
120
160
-
-
-
44
44
60
60
60
44
44
44
44
60
60
40
40
40
80
88
88
120
120
120
88
88
88
88
120
120
80
80
80
160
180
180
120
120
120
240
176
176
176
176
240
240
240
176
176
176
176
176
176
176
176
176
176
240
240
160
160
160
320
252
252
252
252
252
252
276
276
276
276
320
320
-
320
320
320
320
320
320
352
352
352
352
480
480
-
-
VDD (V)
VLCD (V)
ffr (Hz)
1.8 to 5.5
1.8 to 5.5
32 to 256
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 6.5
2.5 to 8
2.5 to 9
2.5 to 5.5
2.5 to 5.5
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 9
2.5 to 6.5
2.5 to 6.5
2.5 to 8
2.5 to 6.5
[1]
VLCD (V)
temperature
compensat.
Tamb (°C)
Interface
Package
AECQ100
N
N
-40 to 105
I C / SPI
2
TSSOP56
Y
2
[1]
N
N
-40 to 95
I C
TSSOP56
Y
[1]
N
N
-40 to 95
SPI
TSSOP56
Y
60 to 300
60 to 300
[1]
Y
Y
-40 to 95
I C
TQFP64
Y
[1]
Y
Y
-40 to 95
SPI
60 to 300
60 to 300
82
N
82
N
[1]
60 to 300
Y
N
N
Y
2
TQFP64
Y
-40 to 85
2
I C
LQFP80
N
-40 to 95
2
I C
LQFP80
Y
2
LQFP80
Y
2
-40 to 105
I C
[1]
N
N
-40 to 85
I C
TSSOP56
N
[1]
N
N
-40 to 85
SPI
TSSOP56
N
60 to 300
60 to 300
[1]
N
N
-40 to 85
I C
TSSOP56
N
[1]
N
N
-40 to 85
SPI
TSSOP56
N
60 to 300
60 to 300
2
[1]
N
N
-40 to 95
I C
TSSOP56
Y
[1]
N
N
-40 to 95
SPI
TSSOP56
Y
60 to 300
60 to 300
2
[1]
Y
Y
-40 to 85
I C
TQFP64
N
[1]
Y
Y
-40 to 85
SPI
TQFP64
N
60 to 300
60 to 300
2
[1]
Y
Y
-40 to 95
I C
TQFP64
Y
[1]
Y
Y
-40 to 95
SPI
60 to 300
60 to 300
[1]
60 to 300
[1]
60 to 300
77
Y
Y
N
77
N
200
82, 110
VLCD (V)
charge
pump
N
[2]
N
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
Y
Y
N
N
N
N
2
TQFP64
Y
-40 to 105
2
I C
LQFP80
Y
-40 to 105
2
I C
Bare die
Y
-40 to 85
2
I C
Bare die
N
-40 to 85
2
I C
Bare die
N
2
I C
Bare die
Y
2
Bare die
N
-40 to 105
-40 to 85
I C
© NXP B.V. 2021. All rights reserved.
43 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Table 23. Selection of LCD segment drivers...continued
Type name
PCA85133U
PCA85233UG
PCF85132U
PCA8530DUG
PCA85132U
PCA85232U
PCF8538UG
PCA8538UG
[1]
[2]
Number of elements at MUX
1:1
1:2
1:3
1:4
1:6
1:8
1:9
80
160
240
320
-
-
-
80
160
102
160
160
102
102
160
320
204
320
320
204
204
240
480
480
480
-
320
640
408
640
640
408
408
612
612
816
816
918
918
VDD (V)
VLCD (V)
ffr (Hz)
1.8 to 5.5
2.5 to 8
82, 110
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
1.8 to 5.5
1.8 to 5.5
2.5 to 5.5
2.5 to 5.5
2.5 to 8
1.8 to 8
4 to 12
1.8 to 8
1.8 to 8
4 to 12
4 to 12
[2]
[2]
150, 220
60 to 90
[1]
VLCD (V)
temperature
compensat.
Tamb (°C)
Interface
N
N
-40 to 95
N
N
[1]
45 to 300
60 to 90
VLCD (V)
charge
pump
[1]
Y
N
[1]
117 to 176
[1]
45 to 300
[1]
45 to 300
N
Y
Y
N
N
Y
N
N
Y
Y
Package
AECQ100
I C
2
Bare die
Y
2
I C
Bare die
Y
2
I C
Bare die
N
2
Bare die
Y
-40 to 95
2
I C
Bare die
Y
-40 to 95
2
I C
Bare die
Y
-40 to 85
2
Bare die
N
2
Bare die
Y
-40 to 105
-40 to 85
-40 to 105
-40 to 105
I C / SPI
I C / SPI
I C / SPI
Software programmable.
Hardware selectable.
PCA85276
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
44 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
21 Abbreviations
Table 24. Abbreviations
Acronym
Description
AEC
Automotive Electronics Council
CMOS
Complementary Metal-Oxide Semiconductor
CDM
Charged Device Model
DC
Direct Current
HBM
Human Body Model
2
I C
Inter-Integrated Circuit
IC
Integrated Circuit
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MSB
Most Significant Bit
MSL
Moisture Sensitivity Level
PCB
Printed-Circuit Board
RAM
Random Access Memory
RC
Resistance and Capacitance
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta Line
SMD
Surface-Mount Device
22 References
[1]
[2]
[3]
[4]
[5]
PCA85276
Product data sheet
JESD22-A114 Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model
(HBM)
JESD22-C101 Field-Induced Charged-Device Model Test Method for ElectrostaticDischarge-Withstand Thresholds of Microelectronic Components
JESD78 IC Latch-Up Test
SOT364-1_118 TSSOP56; Reel pack; SMD, 13", packing information
UM10569 Store and transport requirements
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
45 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
23 Revision history
Table 25. Revision history
Document ID
Release date
Data sheet status
Change notice
PCA85276 v.4
Modifications:
20210929
Product data sheet
PCN202102010F01 PCA85276 v.3
PCA85276 v.3
20181112
Modifications:
• Updated Section 6.4
• Updated layout of Section 3
PCA85276 v.2
20150409
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Changed pin configuration due to redesign
• Enhanced SYNC pin description in Table 3
• Changed typical value of IDD and IDD(LCD) in Table 18
• Adjusted description of initialization (Section 6.4)
PCA85276 v.1
20140211
PCA85276
Product data sheet
Supersedes
• Updated Section 3. See Change notice column.
• Global: The terms "master" and "slave" changed to "controller" and "target" to comply with
NXP inclusive language policy.
Product data sheet
Product data sheet
Product data sheet
201811010I
PCA85276 v.2
-
PCA85276 v.1
-
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
-
© NXP B.V. 2021. All rights reserved.
46 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
24 Legal information
24.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
24.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
24.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not
give any representations or warranties, expressed or implied, as to the
accuracy or completeness of such information and shall have no liability
for the consequences of use of such information. NXP Semiconductors
takes no responsibility for the content in this document if provided by an
information source outside of NXP Semiconductors. In no event shall NXP
Semiconductors be liable for any indirect, incidental, punitive, special or
consequential damages (including - without limitation - lost profits, lost
savings, business interruption, costs related to the removal or replacement
of any products or rework charges) whether or not such damages are based
on tort (including negligence), warranty, breach of contract or any other
legal theory. Notwithstanding any damages that customer might incur for
any reason whatsoever, NXP Semiconductors’ aggregate and cumulative
liability towards customer for the products described herein shall be limited
in accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
PCA85276
Product data sheet
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes
no representation or warranty that such applications will be suitable
for the specified use without further testing or modification. Customers
are responsible for the design and operation of their applications and
products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications
and products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with
their applications and products. NXP Semiconductors does not accept any
liability related to any default, damage, costs or problem which is based
on any weakness or default in the customer’s applications or products, or
the application or use by customer’s third party customer(s). Customer is
responsible for doing all necessary testing for the customer’s applications
and products using NXP Semiconductors products in order to avoid a
default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this
respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
Suitability for use in automotive applications — This NXP product has
been qualified for use in automotive applications. If this product is used
by customer in the development of, or for incorporation into, products or
services (a) used in safety critical applications or (b) in which failure could
lead to death, personal injury, or severe physical or environmental damage
(such products and services hereinafter referred to as “Critical Applications”),
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
47 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
then customer makes the ultimate design decisions regarding its products
and is solely responsible for compliance with all legal, regulatory, safety,
and security related requirements concerning its products, regardless of
any information or support that may be provided by NXP. As such, customer
assumes all risk related to use of any products in Critical Applications and
NXP and its suppliers shall not be liable for any such use by customer.
Accordingly, customer will indemnify and hold NXP harmless from any
claims, liabilities, damages and associated costs and expenses (including
attorneys’ fees) that NXP may incur related to customer’s incorporation of
any product in a Critical Application.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
PCA85276
Product data sheet
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
24.4 Trademarks
Notice: All referenced brands, product names, service names and
trademarks are the property of their respective owners.
2
I C-bus — logo is a trademark of NXP B.V.
NXP — wordmark and logo are trademarks of NXP B.V.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
48 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Ordering information ..........................................2
Ordering options ................................................2
Pin description of PCA85276ATT
(TSSOP56) ........................................................ 5
Definition of the PCA85276 commands .............5
C bit description ................................................ 6
Mode-set command bit description ................... 6
Load-data-pointer command bit description ...... 7
Device-select command bit description ............. 7
Bank-select command bit description ................7
Blink-select command bit description ................ 8
Blink frequencies ...............................................8
Standard RAM filling in 1:3 multiplex drive
mode ............................................................... 12
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Entire RAM filling by rewriting in 1:3
multiplex drive mode ....................................... 13
Selection of possible display configurations .... 17
Biasing characteristics .....................................18
I2C target address byte ...................................27
Limiting values ................................................ 30
Static characteristics ....................................... 30
Dynamic characteristics .................................. 32
Addressing cascaded PCA85276 ....................34
SnPb eutectic process (from J-STD-020D) ..... 39
Lead-free process (from J-STD-020D) ............ 39
Selection of LCD segment drivers ...................43
Abbreviations ...................................................45
Revision history ...............................................46
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Fig. 14.
Block diagram of PCA85276 ............................. 3
Pinning diagram for PCA85276ATT
(TSSOP56) ........................................................ 4
Display RAM bitmap ....................................... 10
Relationship between LCD layout, drive
mode, display RAM filling order, and
display data transmitted over the I2C-bus ....... 11
RAM banks in static and multiplex driving
mode 1:2 ......................................................... 14
Bank selection .................................................15
Example of the Bank-select command with
multiplex drive mode 1:2 ................................. 15
Example of displays suitable for PCA85276 ....16
Typical system configuration ........................... 17
Electro-optical characteristic: relative
transmission curve of the liquid .......................19
Static drive mode waveforms .......................... 20
Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias .................................................... 21
Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias .................................................... 22
Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias .................................................... 23
PCA85276
Product data sheet
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
Fig. 24.
Fig. 25.
Fig. 26.
Fig. 27.
Fig. 28.
Fig. 29.
Fig. 30.
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias .................................................... 24
Bit transfer .......................................................25
Definition of START and STOP conditions ...... 26
System configuration .......................................26
Acknowledgement of the I2C-bus ................... 27
I2C-bus protocol .............................................. 28
Format of command byte ................................ 28
Device protection circuits ................................ 29
Typical IDD with respect to VDD ..................... 32
Driver timing waveforms ..................................33
I2C-bus timing waveforms ...............................34
Cascaded PCA85276 configuration ................ 35
Synchronization of the cascade for the
various PCA85276 drive modes ......................36
Package outline SOT364-1 (TSSOP56) of
PCA85276ATT .................................................37
Temperature profiles for large and small
components ..................................................... 40
Footprint information for reflow soldering of
SOT364-1 (TSSOP56) of PCA85276ATT ........41
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 29 September 2021
© NXP B.V. 2021. All rights reserved.
49 / 50
PCA85276
NXP Semiconductors
Automotive 40 x 4 LCD driver
Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
6.1.5.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.5.1
6.3.5.2
6.3.5.3
6.4
6.4.1
6.4.2
6.5
6.5.1
6.5.2
6.5.3
6.5.3.1
6.5.4
6.5.4.1
6.5.4.2
6.5.4.3
6.5.4.4
6.6
6.6.1
6.6.2
7
7.1
7.2
7.3
7.4
7.5
7.6
7.7
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 5
Functional description ........................................5
Commands of PCA85276 ..................................5
Command: mode-set ......................................... 6
Command: load-data-pointer ............................. 6
Command: device-select ................................... 7
Command: bank-select ......................................7
Command: blink-select ...................................... 7
Blinking .............................................................. 8
Clock and frame frequency ............................... 9
Internal clock ..................................................... 9
External clock .................................................... 9
Timing ................................................................ 9
Display RAM ......................................................9
Data pointer ..................................................... 12
Subaddress counter .........................................12
RAM writing in 1:3 multiplex drive mode ..........12
Writing over the RAM address boundary ......... 13
Bank selection ................................................. 14
Output bank selector ....................................... 14
Input bank selector .......................................... 14
RAM bank switching ........................................ 14
Initialization ...................................................... 15
Device initialization .......................................... 15
Device setup ....................................................16
Possible display configurations ........................16
LCD bias generator ......................................... 17
Display register ................................................ 17
LCD voltage selector ....................................... 17
Electro-optical performance ............................. 19
LCD drive mode waveforms ............................ 20
Static drive mode .............................................20
1:2 Multiplex drive mode ................................. 20
1:3 Multiplex drive mode ................................. 22
1:4 Multiplex drive mode ................................. 23
Backplane and segment outputs ..................... 25
Backplane outputs ........................................... 25
Segment outputs ............................................. 25
Characteristics of the I2C-bus ......................... 25
Bit transfer ....................................................... 25
START and STOP conditions .......................... 25
System configuration ....................................... 26
Acknowledge ....................................................26
I2C-bus controller ............................................ 27
Input filters ....................................................... 27
I2C-bus protocol .............................................. 27
8
9
10
11
12
13
13.1
14
14.1
15
16
17
17.1
18
18.1
18.2
18.3
18.4
19
20
20.1
21
22
23
24
Internal circuitry ................................................ 29
Safety notes .......................................................29
Limiting values .................................................. 30
Static characteristics ........................................ 30
Dynamic characteristics ...................................32
Application information .................................... 34
Cascaded operation .........................................34
Test information ................................................ 36
Quality information ...........................................36
Package outline .................................................37
Handling information ........................................ 38
Packing information ..........................................38
Tape and reel information ................................38
Soldering of SMD packages .............................38
Introduction to soldering .................................. 38
Wave and reflow soldering .............................. 38
Wave soldering ................................................ 39
Reflow soldering .............................................. 39
Footprint information ........................................41
Appendix ............................................................ 42
LCD segment driver selection ......................... 42
Abbreviations .................................................... 45
References ......................................................... 45
Revision history ................................................ 46
Legal information .............................................. 47
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 29 September 2021
Document identifier: PCA85276
