PCA8530
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Rev. 2 — 25 September 2014
Product data sheet
1. General description
The PCA8530 is a fully featured Chip-On-Glass (COG)1 Liquid Crystal Display (LCD)
driver, designed for high-contrast Vertical Alignment (VA) LCD with multiplex rates up to
1:4. It generates the drive signals for a static or multiplexed LCD containing up to
4 backplane, 102 segment outputs, and up to 408 segments/elements. The PCA8530
features an internal charge pump with internal capacitors for on-chip generation of the
LCD driving voltage. To ensure an optimal and stable contrast over the full temperature
range, the PCA8530 offers a programmable temperature compensation of the LCD supply
voltage. The PCA8530 can be easily controlled by a microcontroller through either the
two-line I2C-bus or a four-line bidirectional SPI-bus.
For a selection of NXP LCD segment drivers, see Table 58 on page 93.
2. Features and benefits
1.
AEC Q100 grade 2 compliant for automotive applications
Low power consumption
Extended operating temperature range from 40 C to +105 C
102 segments and 4 backplanes allowing to drive:
up to 51 7-segment numeric characters
up to 25 14-segment alphanumeric characters
any graphics of up to 408 segments/elements
408-bit RAM for display data storage
Two sets of backplane outputs providing higher flexibility for optimal COG layout
configurations
Up to 4 chips can be cascaded to drive larger displays with an internally generated or
externally supplied VLCD
Selectable backplane drive configuration: static, 2, or 4 backplane multiplexing
LCD supply voltage
Programmable internal charge pump for on-chip LCD voltage generation up to
5 VDD2
External LCD voltage supply possible as well
Selectable 400 kHz I2C-bus or 3 MHz SPI-bus interface
Selectable linear temperature compensation of VLCD
Selectable display bias configuration
Wide range for digital and analog power supply: from 2.5 V to 5.5 V
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21 on page 95.
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Wide LCD voltage range from 4.0 V for low threshold LCDs up to 12.0 V for high
threshold twisted nematic and Vertical Alignment (VA) displays
Display memory bank switching in static and 1:2 multiplex drive modes
Programmable frame frequency in the range of 45 Hz to 300 Hz; factory calibrated
with a tolerance of 3 Hz (at 80 Hz)
Selectable inversion scheme for LCD driving waveforms: frame or n-line inversion
Diagnostic features for status monitoring
Integrated temperature sensor with temperature readout
On chip calibration of internal oscillator frequency and VLCD
Laser marking at the back-side of the die for traceability of the lot number, wafer
number, and die position on the wafer
3. Applications
Automotive
Instrument clusters
Climate control
Car entertainment
Car radio
Industrial
Consumer
Medical and health care
Measuring equipment
Machine control systems
Information boards
White goods
General-purpose display modules
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
4. Ordering information
Table 1.
Ordering information
Type number
Package
PCA8530DUG
Name
Description
Version
bare die
247 bumps
PCA8530DUG
4.1 Ordering options
Table 2.
Ordering options
Product type number
Orderable part number Sales item
(12NC)
Delivery form
IC
revision
PCA8530DUG/DA
PCA8530DUG/DAZ
chips with bumps[1] in tray
1
[1]
935304675033
Bump hardness, see Table 56 on page 90.
5. Marking
Table 3.
Marking codes
Product type number
Marking code
PCA8530DUG/DA
on the active side of the die
PC8530-1
on the rear side of the die[1]
LLLLLLL WW XXXXXX
[1]
The rear side marking has the following meaning:
LLLLLLL — wafer lot number
WW — wafer number
XXXXXX — die identification number
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
6. Block diagram
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Fig 14. VLCD generation including temperature compensation
In Equation 2 the main parameters are the programmed digital value term and the
compensated temperature term.
V LCD = V 8:0 + VT 8:0 n + m
(2)
1. V[8:0] is the binary value of the programmed voltage.
2. VT[8:0] is the binary value of the temperature compensated voltage. Its value comes
from the temperature compensation block and is a two’s complement which has the
value 0h at 20 C.
3. m and n are fixed values (see Table 30 and Figure 15).
Table 30.
Parameters of VLCD generation
Symbol
Value
Unit
m
3.99
V
n
0.03
V
Figure 15 shows how VLCD changes with the programmed value of V[8:0].
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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35 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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(1) V[8:0] must be set so that VLCD > VDD2.
(2) Automatic limitation for VLCD > 12 V.
Fig 15. VLCD programming of PCA8530 (assuming VT[8:0] = 0h)
Remarks:
1. It is important that V[8:0] is set to such a value that the resultant VLCD, including the
temperature compensation VT[8:0], is higher than VDD2.
2. Programmable range of V[8:0] is from 0h to 1FFh. This would allow achieving a VLCD
above 12 V but 12 V is the built-in automatic limit.
8.10.3.2
VLCD driving capability
Figure 16 illustrates the main factor determining how much current the charge pump can
deliver.
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Fig 16. Charge pump model (used to characterize the driving strength)
The output resistance of the charge pump is specified in Table 31.
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 31. Output resistance of the charge pump
RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
Charge pump configuration
Ro(VLCDOUT) (typical)
Unit
VLCD = 2 VDD2
2.5
k
VLCD = 3 VDD2
6
k
VLCD = 4 VDD2
10.5
k
VLCD = 5 VDD2
18
k
Remark: The PCA8530 has a built-in automatic limitation of VLCD, set to 12 V. The
maximum VLCD that can be programmed is expressed by the following equation:
V LCD max = min 12 V, n V DD2 – R o VLCDOUT I load , where n is the multiplication factor of
the charge pump. Iload is the overall current sink by the segments and backplanes outputs
depending on the display, plus the on-chip VLCD current consumption.
With these values, it can be calculated how much current the charge pump can drive
under certain conditions, as shown in Figure 17 and Figure 18.
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Conditions: VDD2 = 3.0 V, RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 , Tamb = 27 C.
Charge pump configuration:
(1) VLCD = 2 VDD2.
(2) VLCD = 3 VDD2.
(3) VLCD = 4 VDD2.
(4) VLCD = 5 VDD2.
Iload is the overall current sink by the segments and backplanes outputs depending on the display,
plus the on-chip VLCD current consumption.
Reading example: VLCD can be programmed to 10 V by using the charge pump configuration (3)
or (4). With configuration (3), VLCD can be programmed to 10 V for a current load up to about
120 A. With configuration (4), VLCD can be programmed to 10 V for a current load up to about
260 A.
Remark: Only the charge pump configuration (4) allows programming VLCD = 12 V when
VDD2 = 3.0 V.
Fig 17. Charge pump driving capability with VDD2 = 3.0 V
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Conditions: VDD2 = 5.0 V, RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 , Tamb = 27 C.
Charge pump configuration:
(1) VLCD = 2 VDD2.
(2) VLCD = 3 VDD2.
(3) VLCD = 4 VDD2.
(4) VLCD = 5 VDD2.
Iload is the overall current sink by the segment and backplane outputs depending on the display,
plus the on-chip VLCD current consumption.
Reading example: VLCD can be programmed to 10 V by using the charge pump configuration (2)
or (3). With configuration (2), VLCD can be programmed to 10 V for a current load up to about
780 A. With configuration (3), VLCD can be programmed to 10 V for a current load up to about
940 A.
Remark: The charge pump configuration (4) has no benefit compared to configuration (3) and is
therefore not recommended when VDD2 = 5.0 V.
Fig 18. Charge pump driving capability with VDD2 = 5.0 V
It has to be considered that the driving capability of the charge pump is depending on the
resistance of the Indium Tin Oxide (ITO) tracks, see Figure 20 and Figure 19.
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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38 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
DDD
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Conditions: VDD2 = 3 V; charge pump configuration: VLCD = 4 VDD2; VLCD = 8 V; Tamb = 27 C.
(1) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
(2) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 100 .
Iload is the overall current sink of the segment and backplane outputs depending on the display,
plus the on-chip VLCD current consumption.
Fig 19. VLCD with respect to Iload at VDD2 = 3 V
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Conditions: VDD2 = 5 V; charge pump configuration: VLCD = 2 VDD2; VLCD = 8 V; Tamb = 27 C.
(1) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 50 .
(2) RITO(VSS2), RITO(VDD2), RITO(VLCDOUT) = 100 .
Iload is the overall current sink of the segment and backplane outputs depending on the display,
plus the on-chip VLCD current consumption.
Fig 20. VLCD with respect to Iload at VDD2 = 5 V
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
8.10.4 Temperature measurement and temperature compensation of VLCD
8.10.4.1
Temperature readout
The PCA8530 has a built-in temperature sensor which provides an 8-bit digital value
(TD[7:0]) of the ambient temperature. This value can be read by command (see
Section 8.2.6 on page 12 and Section 8.2.7 on page 13). The actual temperature is
determined from TD[7:0] using Equation 3.
T C = 0.6275 TD 7:0 – 40
(3)
TD[7:0] = FFh means that no temperature readout is available or was performed. The
measurement needs about 8 ms to complete. It is repeated periodically every second as
long as bit TME is set logic 1 (see Table 17 on page 17).
Due to the nature of a temperature sensor, oscillations may occur. To avoid this, a filter
has been implemented in PCA8530. A control bit, TMF, is implemented to enable or
disable the digital temperature filter (see Table 17 on page 17). The system is exemplified
in Figure 21.
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Fig 21. Temperature measurement block with digital temperature filter
The digital temperature filter introduces a certain delay in the measurement of the
temperature. This behavior is illustrated in Figure 22.
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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(1) Environment temperature, T1 (C).
(2) Measured temperature, T2 (C).
(3) Temperature deviation, T = T2 T1.
Fig 22. Temperature measurement delay
8.10.4.2
Temperature adjustment of the VLCD
Due to the temperature dependency of the liquid crystal viscosity, the LCD supply voltage
may have to be adjusted at different temperatures to maintain optimal contrast. The
temperature characteristics of the liquid is provided by the LCD manufacturer. The slope
has to be set to compensate for the liquid behavior. Internal temperature compensation
can be enabled via bit TCE (see Table 17 on page 17).
The ambient temperature range is split up to six programmable regions and to each a
different temperature coefficient can be applied (see Figure 23).
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 23. Example of segmented temperature coefficients
The temperature regions are determined by programming the temperature limits T1 to T4
via the TC-set-1 to TC-set-4 commands (see Section 8.4.2 on page 18). The temperature
coefficients can be selected from a choice of eight different slopes. Each one of theses
coefficients is independently selected via the TC-slope command (see Section 8.4.3 on
page 19).
Table 32.
Temperature regions
T1T[2:0] to
T4T[2:0]
Temperature region 1 and 2
Temperature region 3 and 4
T1, T2 (C)
Corresponding
TD value[1]
T3, T4 (C)
Corresponding
TD value[1]
000
34
10
+29
110
001
27
20
+38
124
010
21
30
+47
138
011
15
40
+55
152
100
9
50
+64
166
101
2
60
+73
180
110
+4
70
+82
194
111
+10
80
+91
208
[1]
The relation between the actual temperature and TD[7:0] is derived from Equation 3 on page 40.
Remark: The programming has to be made such that T1 < T2 and T3 < T4 otherwise the
VLCD temperature compensation will not be executed.
PCA8530
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
Table 33.
Temperature coefficients
TSA[2:0] to TSF[2:0] value
Slope factor (mV/C)
Temperature coefficients
SA to SF[1]
000
0
0.000
001
6
0.125
010
12
0.250
011
24
0.500
100
60
1.250
101
+6
+0.125
110
+12
+0.250
111
+24
+0.500
[1]
The relationship between the temperature coefficients SA to SF and the slope factor is derived from the
0.6275 C
LSB of V[8:0] mV
following equation: Sn = ----------------------------------------------- slope factor (mV/C , where LSB of V[8:0] 30 mV.
The binary value of the temperature compensated voltage VT[8:0] is calculated according
to Table 34.
Table 34.
PCA8530
Product data sheet
Calculation of the temperature compensated value VT
Temperature
(C)
Digital temperature:
TD[7:0]
Binary value of the temperature compensated
voltage: VT[8:0]
T –40 C
TD 7:0 = 0
– 96 – T2 SC – T2 – T1 SB – T1 SA
– 40 C T T1
0 TD 7:0 T1
– 96 – T2 SC – T2 – T1 SB – T1 – TD 7:0 SA
T1 T T2
T1 TD 7:0 T2
– 96 – T2 SC – T2 – TD 7:0 SB
T2 T 20 C
T2 TD 7:0 96
– 96 – TD 7:0 SC
20 C T T3
96 TD 7:0 T3
TD 7:0 – 96 SD
T3 T T4
T3 TD 7:0 T4
T3 – 96 SD + TD 7:0 – T3 SE
T4 T 105 C
T4 TD 7:0 231
T3 – 96 SD + T4 – T3 SE + TD 7:0 – T4 SF
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
8.10.5 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
Set-bias-mode command (see Table 16 on page 16) and the Set-MUX-mode command
(see Table 20 on page 20).
Table 35.
LCD drive modes: summary of characteristics
LCD bias
configuration
V off RMS
----------------------V LCD
V on RMS
---------------------V LCD
V on RMS [1] VLCD[2]
D = ---------------------V off RMS
2
static
0
1
Von(RMS)
3
1⁄
2
0.354
0.791
2.236
2.828 Voff(RMS)
4
1⁄
3
0.333
0.745
2.236
3.0 Voff(RMS)
4
3
1⁄
2
0.433
0.661
1.527
2.309 Voff(RMS)
4
4
1⁄
3
0.333
0.577
1.732
3.0 Voff(RMS)
LCD drive
mode
Number of:
static
1
1:2 multiplex
1:2 multiplex
1:4
multiplex[3]
1:4 multiplex
Backplanes Levels
2
2
[1]
Determined from Equation 6.
[2]
Determined from Equation 5.
[3]
In this example, the discrimination factor and hence the contrast ratio is smaller. The advantage of this LCD drive mode is a power
saving from a reduction of VLCD.
Intermediate LCD biasing voltages are obtained from an internal voltage divider. The
biasing configurations that apply to the preferred modes of operation, together with the
biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are
given in Table 35. Discrimination is a term which is defined as the ratio of the on and off
RMS voltage across a segment. It can be thought of as a measurement of contrast.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off).
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 4:
V on RMS =
V LCD
a 2 + 2a + n
-----------------------------2
n 1 + a
(4)
where VLCD is the resultant voltage at the LCD segment and where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 5:
V off RMS =
PCA8530
Product data sheet
V LCD
a 2 – 2a + n
-----------------------------2
n 1 + a
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 6:
V on RMS
D = ---------------------- =
V off RMS
2
a + 2a + n
--------------------------2
a – 2a + n
(6)
VLCD is sometimes referred as the LCD operating voltage.
8.10.5.1
Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel is switched on or off, determine the transmissibility of the
pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 24.
For a good contrast performance, the following rules should be followed:
V on RMS V th on
(7)
V off RMS V th off
(8)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 4 to Equation 6) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
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Fig 24. Electro-optical characteristic: relative transmission curve of the liquid
PCA8530
Product data sheet
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Rev. 2 — 25 September 2014
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
8.10.6 LCD drive mode waveforms
8.10.6.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD.
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = V(Sn + 1)(t) VBP0(t).
Von(RMS)(t) = VLCD.
Voff(RMS)(t) = 0 V.
Fig 25. Static drive mode waveforms, line inversion mode (n = 1)
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8.10.6.2
1:2 Multiplex drive mode
When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The
PCA8530 allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 26 and
Figure 27.
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.791VLCD.
Voff(RMS)(t) = 0.354VLCD.
Fig 26. Waveforms for the 1:2 multiplex drive mode, 1⁄2 bias, line inversion mode (n = 1)
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.745VLCD.
Voff(RMS)(t) = 0.333VLCD.
Fig 27. Waveforms for the 1:2 multiplex drive mode, 1⁄3 bias, line inversion mode (n = 1)
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8.10.6.3
1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as
shown in Figure 28.
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Vstate1(t) = VSn(t) VBP0(t).
Vstate2(t) = VSn(t) VBP1(t).
Von(RMS)(t) = 0.577VLCD.
Voff(RMS)(t) = 0.333VLCD.
Fig 28. Waveforms for the 1:4 multiplex drive mode, 1⁄3 bias, line inversion mode (n = 1)
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
8.11 Backplane outputs
The LCD drive section includes 4 backplane outputs: COM0 to COM3. The backplanes
are double implemented to offer a higher flexibility for the glass layout.
The backplane output signals are generated based on the selected LCD multiplex drive
mode. Table 36 describes which outputs are active for each of the multiplex drive modes
and what signal is generated.
Table 36.
Mapping of output pins and corresponding output signals with respect to the
multiplex driving mode
Multiplex
drive mode
Output pin
COM0
COM1
COM2
COM3
Signal
static
BP0
BP0
BP0
BP0
1:2
BP0
BP1
BP0
BP1
1:4
BP0
BP1
BP2
BP3
Table 37 describes the corresponding layout topology.
Table 37.
Layout topology of output pins and corresponding output signals with respect to
the multiplex driving mode
Multiplex drive mode
Static
1:2
1:4
Signal
On pin
Signal
On pin
Signal
On pin
BP0
COM0
BP0
COM0
BP0
COM0
COM2
BP1
COM1
BP1
COM1
BP2
COM2
COM3
BP3
COM3
COM1
COM2
COM3
8.11.1 Driving strength on the backplanes
Corresponding output pins (COMx), which are carrying the same signal (BPx), may
optionally be connected to the display. This allows gaining a higher driving strength. If not
required, the unused pins can be left open-circuit.
8.12 Segment outputs
The LCD drive section includes 102 segment outputs (S0 to S101) which must be
connected directly to the LCD. The segment output signals are generated based on the
multiplexed backplane signals and with data resident in the display register. When less
than 102 segment outputs are required, the unused segment outputs must be left
open-circuit.
8.13 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
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8.14 Display RAM
The display RAM is a static 102 4-bit RAM which stores LCD data. Logic 1 in the RAM
bit map indicates the on-state, logic 0 the off-state of the corresponding LCD element.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD segments/elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
The display RAM bit map, Figure 29 on page 53, shows row 0 to row 3 which correspond
with the backplane outputs COM0 to COM3, and column 0 to column 101 which
correspond with the segment outputs S0 to S101. In multiplexed LCD applications, the
data of each row of the display RAM is time-multiplexed with the corresponding backplane
(row 0 with COM0, row 1 with COM1, and so on).
When display data is transmitted to the PCA8530, the display bytes received are stored in
the display RAM in accordance with the selected LCD multiplex drive mode. The data is
stored as it arrives and does not wait for the acknowledge cycle as with the commands.
Depending on the current multiplex drive mode, data is stored singularly, in pairs, or
quadruples.
8.14.1 Data pointer
The addressing mechanism for the display RAM is realized using a data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the Data-pointer-init command followed by setting the data pointer with the
Data-pointer-MSB and Data-pointer-LSB commands. Then the display RAM content can
be written. An arriving data byte is stored starting at the display RAM address indicated by
the data pointer.
The data pointer is automatically incremented in accordance with the chosen LCD
multiplex drive mode configuration. After each byte is stored, the content of the data
pointer is incremented
• by eight (static drive mode)
• by four (1:2 multiplex drive mode)
• by two (1:4 multiplex drive mode)
When the address counter reaches the end of the RAM, it stops incrementing after the last
byte is transmitted. Redundant bits of the last byte and subsequent bytes transmitted are
discarded. To send new RAM data, the data pointer must be reset.
If a data access with the I2C- or SPI-bus is terminated early, then the state of the data
pointer is unknown. The data pointer must then be rewritten before further RAM accesses.
8.14.1.1
Data pointer in cascade configuration
In cascaded applications each PCA8530 in the cascade must be addressed separately.
Initially, the first PCA8530 is selected by sending the Device-address command matching
the first hardware address. Then the data pointer is set to the preferred display RAM
address with the Data-pointer commands.
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Storage is allowed only when the content of the device address register matches with the
hardware device address applied to A0 and A1 (see Section 8.2.3). If the content of the
device address register and the hardware device address do not match, then data storage
is inhibited but the data pointer is incremented as if data storage had taken place.
8.14.2 RAM filling
For the following examples showing the RAM filling patterns, it is assumed that the bits
shown in Table 38 are transferred to the RAM.
Table 38.
8.14.2.1
Bit scheme used to illustrate the RAM filling patterns
Bit 7
MSB
Byte
6
5
4
3
2
1
0
LSB
1
aa7
aa6
aa5
aa4
aa3
aa2
aa1
aa0
2
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ab6
ab5
ab4
ab3
ab2
ab1
ab0
:
:
:
:
:
:
:
:
:
51
by7
by6
by5
by4
by3
by2
by1
by0
RAM filling in static drive mode
In the static drive mode, the eight transmitted data bits are placed in eight successive
display RAM columns in row 0 (see Table 39).
Table 39.
RAM filling in static drive mode
RAM row/
backplane
output
(COM)
RAM column/Segment output (S)
0
aa7 aa6 aa5 aa4 aa3 aa2 aa1 aa0 ab7 ab6 ab5 ab4 ab3 ab2 ab1 ab0 :
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
:
99
100
101
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-
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-
-
-
-
-
:
-
-
-
In order to fill the whole RAM row, 13 bytes must be sent to the PCA8530. Any data bits
that spill over the RAM and additional data bytes sent are discarded.
8.14.2.2
RAM filling in 1:2 multiplex drive mode
In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four
successive display RAM columns of two rows (see Table 40).
Table 40.
RAM filling in 1:2 multiplex drive mode
RAM row/
backplane
output
(COM)
RAM column/Segment output (S)
0
1
2
3
4
5
6
7
:
99
100
101
0
aa7
aa5
aa3
aa1
ab7
ab5
ab3
ab1
:
ay1
az7
az5
1
aa6
aa4
aa2
aa0
ab6
ab4
ab2
ab0
:
ay0
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az4
2
-
-
-
-
-
-
-
-
:
-
-
-
3
-
-
-
-
-
-
-
-
:
-
-
-
In order to fill the whole two RAM rows 26 bytes need to be sent to the PCA8530. Any
data bits that spill over the RAM and additional data bytes sent are discarded.
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8.14.2.3
RAM filling in 1:4 multiplex drive mode
In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two
successive display RAM columns of four rows (see Table 41).
Table 41.
RAM filling in 1:4 multiplex drive mode
RAM row/
backplane
output
(COM)
RAM column/Segment output (S)
0
1
2
3
:
99
100
101
0
aa7
aa3
ab7
ab3
:
bx3
by7
by3
1
aa6
aa2
ab6
ab2
:
bx2
by6
by2
2
aa5
aa1
ab5
ab1
:
bx1
by5
by1
3
aa4
aa0
ab4
ab0
bx0
by4
by0
In order to fill the whole four RAM rows 51 bytes need to be sent to the PCA8530.
Depending on the start address of the data pointer, there is the possibility for a boundary
condition. This occurs when more data bits are sent than fit into the remaining RAM. The
additional data bits are discarded.
8.14.3 Bank selection
The PCA8530 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. A bank can be thought of as a RAM row or a collection of RAM rows. The RAM
bank switching gives the provision for preparing display information in an alternative bank
and to be able to switch to it once it is complete. Figure 29 shows the location of the banks
relative to the RAM map.
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The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs, between the bits in a RAM row and the backplane outputs, and between the
RAM rows and banks.
Fig 29. Display RAM bitmap and bank definition
Input and output banks can be set independently from one another with the bank-select
commands (see Section 8.7.2 on page 24). Figure 31 shows the concept.
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Fig 30. Bank selection in multiplex drive mode 1:2
In the 1:2 multiplex mode, the bank-select command may request the contents of bank 2
to be selected for display instead of the contents of bank 0. This gives the provision for
preparing display information in an alternative bank and to be able to switch to it once it is
assembled.
In Figure 31 an example is shown for 1:2 multiplex drive mode where the displayed data is
read from the first two rows of the memory (bank 0), while the transmitted data is stored in
the second two rows of the memory (bank 1).
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Fig 31. Example of the Bank-select command with multiplex drive mode 1:2
8.14.3.1
Input-bank-select
The Input-bank-select command (see Table 26 on page 24) loads display data into the
display RAM in accordance with the selected LCD drive configuration (see Figure 29 on
page 53).
• In static drive mode, an individual content can be stored in each RAM bank (bank 0 to
bank 3 which corresponds to row 0 and row 3).
• In 1:2 multiplex drive mode, individual content for RAM bank 0 (row 0 and row 1),
RAM bank 2 (row 2 and row 3) can be stored.
The Input-bank-select command works independently to the Output-bank-select
command.
8.14.3.2
Output-bank-select
The Output-bank-select command (see Table 27 on page 25) selects the display RAM
transferring it to the display register in accordance with the selected LCD drive
configuration (see Figure 29 on page 53).
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• In the static drive mode, it is possible to request the content of RAM bank 1 for display
instead of the default RAM bank 0.
• In 1:2 multiplex drive mode, the content of RAM bank 2 may be selected instead of
the default RAM bank 0.
The Output-bank-select command works independently to the Input-bank-select
command.
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9. Bus interfaces
9.1 Control byte and register selection
After initiating the communication over the bus and sending the slave address (I2C-bus,
see Section 9.2) or subaddress (SPI-bus, see Section 9.3 on page 61), a control byte
follows. The purpose of this byte is to indicate both, the content for the following data
bytes (RAM or command) and to indicate that more control bytes will follow.
Typical sequences could be:
• Slave address/subaddress - control byte - command byte - command byte - command
byte - end
• Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end
• Slave address/subaddress - control byte - command byte - control byte - RAM byte end
This allows sending a mixture of RAM and command data in one access or alternatively,
to send just one type of data in one access. In this way, it is possible to configure the
device and then fill the display RAM with little overhead. The display bytes are stored in
the display RAM at the address specified by the data pointer.
Table 42.
Control byte description
Bit
Symbol
7
CO
6 to 5
4 to 0
Value
Description
continue bit
0
last control byte
1
control bytes continue
RS[1:0]
register selection
-
00, 10
command register
01
RAM data
11
unused
-
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Fig 32. Control byte format
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9.2 I2C interface
The I2C-bus is selected by connecting pin IFS to VDD1.
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
In Chip-On-Glass (COG) applications, where the track resistance between the SDA
output pin to the system SDA input line can be significant, the bus pull-up resistor and the
Indium Tin Oxide (ITO) track resistance may generate a voltage divider. As a
consequence it may be possible that the acknowledge cycle, generated by the LCD driver,
cannot be interpreted as logic 0 by the master. Therefore it is an advantage for COG
applications to have the acknowledge output separated from the data line. For that
reason, the SDA line of the PCA8530 is split into SDI/SDAIN and SDAOUT.
In COG applications where the acknowledge cycle is required, it is necessary to minimize
the track resistance from the SDAOUT pin to the system SDI/SDAIN line to guarantee a
valid LOW level.
By splitting the SDA line into SDI/SDAIN and SDAOUT (having the SDAOUT open
circuit), the device could be used in a mode that ignores the acknowledge cycle.
Separating the acknowledge output from the serial data line can avoid design efforts to
generate a valid acknowledge level. However, in that case the I2C-bus master has to be
set up in such a way that it ignores the acknowledge cycle.2
By connecting pin SDAOUT to pin SDI/SDAIN, the SDI/SDAIN line becomes fully I2C-bus
compatible. The following definition assumes SDI/SDAIN and SDAOUT are connected
and refers to the pair as SDA.
9.2.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
are interpreted as a control signal (see Figure 33).
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Fig 33. I2C-bus - bit transfer
9.2.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START
condition (S).
2.
For further information, consider the NXP application note: Ref. 1 “AN10170”.
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A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP
condition (P).
The START and STOP conditions are shown in Figure 34.
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Fig 34. I2C-bus - definition of START and STOP conditions
9.2.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the
receiver. The device that controls the message is the master; and the devices which are
controlled by the master are the slaves. The system configuration is shown in Figure 35.
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Fig 35. I2C-bus - system configuration
9.2.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be considered).
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event, the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 36.
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Automotive 102 x 4 Chip-On-Glass LCD segment driver
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Fig 36. Acknowledgement on the I2C-bus
9.2.5 I2C-bus controller
The PCA8530 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers. The
only data output from PCA8530 is the acknowledge signals and the temperature readout
byte of the selected device.
9.2.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
9.2.7 I2C-bus slave address
Device selection depends on the I2C-bus slave address.
Table 43.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
slave address
0
0
LSB
1
1
1
0
SA1
SA0
R/W
The least significant bit of the slave address byte is bit R/W (see Table 44).
Table 44.
R/W-bit description
R/W
Description
0
write data
1
read data
Bit 1 and bit 2 of the slave address are defined by connecting the inputs SA0 and SA1 to
either VSS1 (logic 0) or VDD1 (logic 1). Therefore, four instances of PCA8530 can be
distinguished on the same I2C-bus.
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9.2.8 I2C-bus protocol
The I2C-bus protocol is shown in Figure 37. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the four PCA8530 slave
addresses available. All PCA8530 with the corresponding SA1 and SA0 level
acknowledge in parallel to the slave address, but all PCA8530 with the alternative SA1
and SA0 levels ignore the whole I2C-bus transfer.
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Fig 37. I2C-bus protocol - write mode
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information. The control byte (see Table 42 on page 56) also defines whether
the next byte is a control byte or further RAM or command data.
For a temperature readout (see Section 8.10.4.1 on page 40), the R/W bit must be logic 1.
The next data byte following is provided by the PCA8530 as shown in Figure 38.
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Fig 38. I2C-bus protocol - read mode
PCA8530
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60 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
9.3 SPI interface
The SPI interface is selected by connecting pin IFS to VSS1.
Data transfer to the device is made via a four-line SPI-bus (see Table 45). The SPI-bus is
initialized whenever the chip enable line pin CE is LOW.
Table 45.
Serial interface
Symbol
Function
Description
CE
chip enable input;
active LOW[1]
when HIGH, the interface is reset
SCL
serial clock input
input may be higher than VDD1
SDI/SDAIN serial data input
input may be higher than VDD1;
input data is sampled on the rising edge of SCL
SDO
[1]
serial data output
-
The chip enable must not be wired permanently LOW.
9.3.1 Data transmission
The chip enable signal (CE) is used to initialize data transmission. Each data transfer is a
byte, with the MSB sent first. The first byte transmitted is the subaddress byte.
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Fig 39. SPI-bus protocol - data transfer overview
The subaddress byte opens the communication with a read/write bit and a subaddress.
The subaddress is used to identify multiple devices on one SPI bus.
Table 46.
Subaddress byte definition
Bit
Symbol
7
R/W
6 to 5
SA
4 to 0
-
Value
Description
data read or write selection
0
write data
1
read data
01
subaddress; other codes cause the device to
ignore data transfer
unused
Figure 40 shows an example of an SPI data transfer.
PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
61 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
5:
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In this example, the bias system is set to 1⁄3. The transfer is terminated by CE returning to logic 1. After the last bit is
transmitted, the state of the SDI/SDAIN line is not important.
Fig 40. SPI-bus example
For a temperature readout (see Section 8.10.4.1 on page 40), the R/W bit must be logic 1.
The next data byte following is provided by the PCA8530 as shown in Figure 41.
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Fig 41. SPI-bus protocol - read example
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Data transfers are terminated by de-asserting CE (set CE to logic 1).
Fig 42. SPI-bus protocol - write example
PCA8530
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 25 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
62 of 103
PCA8530
NXP Semiconductors
Automotive 102 x 4 Chip-On-Glass LCD segment driver
10. Internal circuitry
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