PCA8533
Universal LCD driver for low multiplex rates
Rev. 3 — 1 October 2012
Product data sheet
1. General description
The PCA8533 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 80 segments and can easily be cascaded
for larger LCD applications. The PCA8533 is compatible with most microcontrollers and
communicates via the two-line bidirectional I2C-bus. Communication overheads are
minimized by a display RAM with auto-incremental addressing, by hardware
subaddressing and by display memory switching (static and duplex drive modes).
2. Features and benefits
1.
Single-chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2, or 1⁄3
Internal LCD bias generation with voltage follower buffers
80 segment outputs allowing to drive:
35 7-segment alphanumeric characters
20 14-segment alphanumeric characters
Any graphics of up to 320 elements
80 4 bit RAM for display data storage
Auto-incremental display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for high
threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
CMOS compatible
May be cascaded for large LCD applications (up to 5120 elements possible)
No external components required
Compatible with Chip-On-Glass (COG) technology
Manufactured using silicon gate CMOS process
The definition of the abbreviations and acronyms used in this data sheet can be found in Section 17.
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
PCA8533U
Name
Description
Version
bare die
99 bumps; 5.28 x 1.4 x 0.38 mm
PCA8533-2
3.1 Ordering options
Table 2.
Ordering options
Type number
IC
revision
Sales item (12NC)
Delivery form
PCA8533U/2DD/2
2
935295243026
chip with bumps in tray
4. Marking
Table 3.
PCA8533
Product data sheet
Marking codes
Type number
Marking code
PCA8533U/2DD/2
PC8533-2
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PCA8533
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Universal LCD driver for low multiplex rates
5. Block diagram
S0 to S79
BP0 BP1 BP2 BP3
80
VLCD
BACKPLANE
OUTPUTS
DISPLAY SEGMENT OUTPUTS
DISPLAY REGISTER
LCD
VOLTAGE
SELECTOR
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROL
LCD BIAS
GENERATOR
VSS
PCA8533
CLK
SYNC
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
OSC
OSCILLATOR
POWER-ON
RESET
SCL
INPUT
FILTERS
SDA
WRITE DATA
CONTROL
I2C-BUS
CONTROLLER
SA0
Fig 1.
COMMAND
DECODE
DISPLAY
RAM
DATA POINTER AND
AUTO INCREMENT
SUBADDRESS
COUNTER
SDAACK
VDD
A0
A1
A2
013aaa488
Block diagram of PCA8533
PCA8533
Product data sheet
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PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
6. Pinning information
PCA8533U
y
S11
D1
D2
BP2
BP0
S0
S1
S2
VLCD
VSS
SA0
A2
A1
A0
SYNC
VDD
CLK
SCL
SDA
SDAACK
S79
BP3
BP1
.
.
.
.
.
.
.
.
.
.
.
.
OSC
x
0, 0
D7
D8
S68
S12
D4
D3
.
.
.
.
.
.
D6
D5
S67
6.1 Pinning
013aaa489
Viewed from active side. For mechanical details, see Figure 28.
Fig 2.
Pin configuration for PCA8533U
6.2 Pin description
Table 4.
Pin description overview
Symbol
Pin
Type
Description
SDAACK
1
output
I2C-bus acknowledge
SDA
2 and 3
input/output
I2C-bus serial data
SCL
4 and 5
input
I2C-bus serial clock
CLK
6
input/output
clock input/output
VDD
7
supply
supply voltage
SYNC
8
input/output
cascade synchronization
OSC
9
input
oscillator select
A0, A1 and A2
10 to 12
input
subaddress
SA0
13
input
I2C-bus slave address
VSS[1]
14
supply
ground supply voltage
VLCD
15
supply
LCD supply voltage
BP0, BP1, BP2 and BP3 17, 99, 16 and
98
output
LCD backplane output
S0 to S79
output
LCD segment output
-
dummy pins
18 to 97
D1, D2, D3, D4, D5, D6,
D7, D8
[1]
PCA8533
Product data sheet
The substrate (rear side of the die) is at VSS potential and should be electrically isolated.
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PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
7. Functional description
The PCA8533 is a versatile peripheral device designed to interface between any
microcontroller to a wide variety of LCD segment or dot-matrix displays. It can directly
drive any static or multiplexed LCD containing up to four backplanes and up to
80 segments.
7.1 Commands of PCA8533
The five commands available to the PCA8533 are defined in Table 5.
Table 5.
Definition of commands
Command
Operation code
Reference
Bit
7
6
5
4
3
2
1
mode-set
1
1
0
0
E
B
M[1:0]
load-data-pointer
0
P[6:0]
device-select
1
1
1
0
0
A[2:0]
bank-select
1
1
1
1
1
0
I
blink-select
1
1
1
1
0
AB
BF[1:0]
0
Table 6
Table 7
Table 8
O
Table 9
Table 10
7.1.1 Command: mode-set
The mode-set command allows configuring the multiplex mode, the bias levels and
enabling or disabling the display.
Table 6.
Mode-set command bit description
Bit
Symbol
Value
Description
7 to 4
-
1100
fixed value
3
E
2
PCA8533
Product data sheet
0
disabled (blank)[2]
1
enabled
LCD bias configuration[3]
B
1 to 0
[1]
display status[1]
0
1⁄
3
bias
1
1⁄
2
bias
M[1:0]
LCD drive mode selection
01
static; 1 backplane
10
1:2 multiplex; 2 backplanes
11
1:3 multiplex; 3 backplanes
00
1:4 multiplex; 4 backplanes
The possibility to disable the display allows implementation of blinking under external control.
[2]
The display is disabled by setting all backplane and segment outputs to VLCD.
[3]
Not applicable for static drive mode.
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PCA8533
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Universal LCD driver for low multiplex rates
7.1.2 Command: load-data-pointer
The load-data-pointer command defines the display RAM address where the following
display data will be sent to.
Table 7.
Load-data-pointer command bit description
See Section 7.6.1.
Bit
Symbol
Value
Description
7
-
0
fixed value
6 to 0
P[6:0]
0000000 to
1001111
data pointer
7-bit binary value of 0 to 79, transferred to the data pointer to
define one of 80 display RAM addresses
7.1.3 Command: device-select
The device-select command allows defining the subaddress counter value.
Table 8.
Device-select command bit description
See Section 7.6.2.
Bit
Symbol
Value
Description
7 to 3
-
11100
fixed value
2 to 0
A[2:0]
000 to 111
device selection
3-bit binary value of 0 to 7, transferred to the subaddress
counter to define one of 8 hardware subaddresses
7.1.4 Command: bank-select
The bank-select command controls where data is written to RAM and where it is displayed
from.
Table 9.
Bank-select command bit description[1]
See Section 7.6.5.1 and Section 7.6.5.2.
Bit
Symbol
Value
Description
Static
7 to 2
-
1
I
0
[1]
PCA8533
Product data sheet
111110
1:2 multiplex
fixed value
Input bank selection: storage of arriving display data
0
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
O
Output bank selection: retrieval of LCD display data
0
RAM row 0
RAM rows 0 and 1
1
RAM row 2
RAM rows 2 and 3
The bank-select command has no effect in 1:3 or 1:4 multiplex drive modes.
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PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.1.5 Command: blink-select
The blink-select command allows configuring the blink mode and the blink frequency.
Table 10. Blink-select command bit description
See Section 7.1.5.1.
Bit
Symbol
Value
Description
7 to 3
-
11110
fixed value
2
AB
1 to 0
7.1.5.1
blink mode selection[1]
0
normal blinking
1
blinking by alternating display RAM banks
blink mode selection[2]
BF[1:0]
00
off
01
1
10
2
11
3
[1]
Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes.
[2]
For the blink frequency, see Table 11.
Blinking
The display blink capabilities of the PCA8533 are very versatile. The whole display can
blink at frequencies selected by the blink-select command (see Table 10). The blink
frequencies are fractions of the clock frequency. The ratios between the clock and blink
frequencies depend on the blink mode selected (see Table 11).
Table 11.
Blink frequencies
Blink mode
Normal operating
mode ratio
Nominal blink frequency of fclk Unit
(typical fclk = 1.536 kHz)
Off
-
blinking off
Hz
1
f clk
-------768
2
Hz
2
f clk
----------1536
1
Hz
3
f clk
----------3072
0.5
Hz
An additional feature is for an arbitrary selection of LCD segments to blink. This applies to
the static and 1:2 multiplex drive modes and can be implemented without any
communication overheads. With the output bank selector, the displayed RAM banks are
exchanged with alternate RAM banks at the blink frequency. This mode can also be
specified by the blink-select command.
In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of
LCD segments can blink by selectively changing the display RAM data at fixed time
intervals.
The entire display can blink at a frequency other than the typical blink frequency. This can
be effectively performed by resetting and setting the display enable bit E at the required
rate using the mode-set command (see Table 6).
PCA8533
Product data sheet
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PCA8533
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Universal LCD driver for low multiplex rates
7.2 Power-On Reset (POR)
At power-on, the PCA8533 resets to the following starting conditions:
1. All backplane outputs are set to VLCD.
2. All segment outputs are set to VLCD.
3. The selected drive mode is: 1:4 multiplex with 1⁄3 bias.
4. Blinking is switched off.
5. Input and output bank selectors are reset.
6. The I2C-bus interface is initialized.
7. The data pointer and the subaddress counter are cleared (set to logic 0).
8. The display is disabled (bit E = 0, see Table 6)
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.3 Possible display configurations
The display configurations possible with the PCA8533 depend on the required number of
active backplane outputs. A selection of display configurations is given in Table 12.
All of the display configurations given in Table 12 can be implemented in a typical system
as shown in Figure 4.
dot matrix
7-segment with dot
14-segment with dot and accent
013aaa312
Fig 3.
PCA8533
Product data sheet
Example of displays suitable for PCA8533
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PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
Table 12.
Selection of possible display configurations
Number of
Backplanes
Icons
Digits/Characters
7-segment[1]
14-segment[2]
Dot matrix/
Elements
4
320
40
20
320 (4 80)
3
240
30
15
240 (3 80)
2
160
20
10
160 (2 80)
1
80
10
5
80 (1 80)
[1]
7 segment display has 8 elements including the decimal point.
[2]
14 segment display has 16 elements including decimal point and accent dot.
VDD
R≤
tr
2Cb
SDAACK
VDD
VLCD
SDA
HOST
MICROPROCESSOR/
MICROCONTROLLER
80 segment drives
SCL
PCA8533
OSC
4 backplanes
A0
A1
A2
SA0 VSS
LCD PANEL
(up to 320
elements)
013aaa490
VSS
Fig 4.
Typical system configuration
The host microcontroller maintains the 2-line I2C-bus communication channel with the
PCA8533. The internal oscillator is enabled by connecting pin OSC to pin VSS. The
appropriate biasing voltages for the multiplexed LCD waveforms are generated internally.
The only other connections required to complete the system are the power supplies (VDD,
VSS, and VLCD) and the LCD panel chosen for the application.
7.3.1 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of three
impedances connected between pins VLCD and VSS. The center impedance is bypassed
by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is
selected.
7.3.2 Display register
The display register holds the display data while the corresponding multiplex signals are
generated.
7.3.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command from the command decoder. The biasing configurations that apply to
the preferred modes of operation, together with the biasing characteristics as functions of
VLCD and the resulting discrimination ratios (D) are given in Table 13.
PCA8533
Product data sheet
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PCA8533
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Universal LCD driver for low multiplex rates
Discrimination is a term which is defined as the ratio of the on and off RMS voltage across
a segment. It can be thought of as a measurement of contrast.
Table 13.
Biasing characteristics
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off RMS
------------------------V LCD
V on RMS
-----------------------V LCD
static
V on RMS
D = -----------------------V off RMS
1
2
static
0
1
1:2 multiplex 2
3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:3 multiplex 3
1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode, a suitable choice is VLCD > 3Vth(off).
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1:
V on RMS =
V LCD
a 2 + 2a + n
-----------------------------2
n 1 + a
(1)
where the values for n are
n = 1 for static drive mode
n = 2 for 1:2 multiplex drive mode
n = 3 for 1:3 multiplex drive mode
n = 4 for 1:4 multiplex drive mode
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
V off RMS =
V LCD
a 2 – 2a + n
-----------------------------2
n 1 + a
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
V on RMS
D = ---------------------- =
V off RMS
PCA8533
Product data sheet
2
a + 2a + n
--------------------------2
a – 2a + n
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PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2
bias is
1⁄
2
21
bias is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6 V off RMS = 2.449V off RMS
4 3
- = 2.309V off RMS
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off RMS when 1⁄3 bias is used.
VLCD is sometimes referred as the LCD operating voltage.
7.3.3.1
Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see
Figure 5. For a good contrast performance, the following rules should be followed:
V on RMS V th on
(4)
V off RMS V th off
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
PCA8533
Product data sheet
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PCA8533
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Universal LCD driver for low multiplex rates
100 %
Relative Transmission
90 %
10 %
Vth(off)
OFF
SEGMENT
Vth(on)
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
013aaa494
Fig 5.
PCA8533
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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PCA8533
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Universal LCD driver for low multiplex rates
7.3.4 LCD drive mode waveforms
7.3.4.1
Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 6.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
VLCD
state 2
0V
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl745
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = VLCD.
Vstate2(t) = V(Sn+1)(t) VBP0(t).
Voff(RMS) = 0 V.
Fig 6.
PCA8533
Product data sheet
Static drive mode waveforms
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PCA8533
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Universal LCD driver for low multiplex rates
7.3.4.2
1:2 multiplex drive mode
The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This
mode allows fractional LCD bias voltages of 1⁄2 bias or 1⁄3 bias as shown in Figure 7 and
Figure 8.
Tfr
VLCD
BP0
LCD segments
VLCD / 2
VSS
state 1
VLCD
BP1
state 2
VLCD / 2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD / 2
state 1
0V
−VLCD / 2
−VLCD
VLCD
VLCD / 2
state 2
0V
−VLCD / 2
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl746
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.791VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.354VLCD.
Fig 7.
PCA8533
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
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PCA8533
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Universal LCD driver for low multiplex rates
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
Sn+1
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl747
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.745VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 8.
PCA8533
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.3.4.3
1:3 multiplex drive mode
The 1:3 multiplex drive mode is used when three backplanes are provided in the LCD as
shown in Figure 9.
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+2
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl748
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.638VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 9.
PCA8533
Product data sheet
Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
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PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.3.4.4
1:4 multiplex drive mode
The 1:4 multiplex drive mode is used when four backplanes are provided in the LCD as
shown in Figure 10.
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP3
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+3
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl749
Vstate1(t) = VSn(t) VBP0(t).
Von(RMS) = 0.577VLCD.
Vstate2(t) = VSn(t) VBP1(t).
Voff(RMS) = 0.333VLCD.
Fig 10. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
PCA8533
Product data sheet
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Rev. 3 — 1 October 2012
© NXP B.V. 2012. All rights reserved.
17 of 54
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.4 Oscillator
The internal logic and the LCD drive signals of the PCA8533 are timed by a frequency fclk,
which either is derived from the built-in oscillator frequency fosc or equals an external clock
frequency fclk(ext).
f osc
f clk = ------64
The clock frequency fclk determines the LCD frame frequency ffr (see Table 14) and is
calculated as follows:
f clk
f fr = ------24
Table 14.
LCD frame frequency
Nominal clock frequency (Hz)
LCD frame frequency (Hz)
1536
64
7.4.1 Internal clock
The internal oscillator is enabled by connecting pin OSC to VSS. In this case, the output
from pin CLK provides the clock signal for cascaded PCA8533 in the system.
7.4.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.4.3 Timing
The PCA8533 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the synchronization signal (SYNC) maintains the correct timing relationship
between all PCA8533 in the system. The timing also generates the LCD frame signal (ffr)
whose frequency is derived as an integer division of the clock frequency fclk (see
Table 14), applied to pin CLK from either the internal or an external clock.
7.5 Backplane and segment outputs
7.5.1 Backplane outputs
The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane
output signals are generated based on the selected LCD drive mode.
• In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD.
If less than four backplane outputs are required, the unused outputs can be left
open-circuit.
• In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
• In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same
signals and can also be paired to increase the drive capabilities.
PCA8533
Product data sheet
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Rev. 3 — 1 October 2012
© NXP B.V. 2012. All rights reserved.
18 of 54
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
• In static drive mode: The same signal is carried by all four backplane outputs; and
they can be connected in parallel for very high drive requirements.
7.5.2 Segment outputs
The LCD drive section includes 80 segment outputs (S0 to S79) which must be connected
directly to the LCD. The segment output signals are generated in accordance with the
multiplexed backplane signals and with data residing in the display register. When less
than 80 segment outputs are required, the unused segment outputs must be left
open-circuit.
7.6 Display RAM
The display RAM is a static 80 4 bit RAM which stores LCD data.
There is a one-to-one correspondence between
• the bits in the RAM bitmap and the LCD elements
• the RAM columns and the segment outputs
• the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bit map, Figure 11, shows rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and columns 0 to 79 which correspond with the segment
outputs S0 to S79. In multiplexed LCD applications the segment data of the first, second,
third and fourth row of the display RAM are time-multiplexed with BP0,
BP1, BP2, and BP3 respectively.
columns
display RAM addresses/segment outputs (S)
0
rows
1
2
3
4
75
76
77
78
79
0
display RAM rows/
backplane outputs 1
(BP)
2
3
013aaa214
The display RAM bitmap shows the direct relationship between the display RAM addresses and
the segment outputs and between the bits in a RAM word and the backplane outputs.
Fig 11. Display RAM bitmap
When display data is transmitted to the PCA8533, the received display bytes are stored in
the display RAM in accordance with the selected LCD drive mode. The data is stored as it
arrives and depending on the current multiplex drive mode the bits are stored singularly, in
pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment
display showing all drive modes is given in Figure 12; the RAM filling organization
depicted applies equally to other LCD types.
PCA8533
Product data sheet
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Rev. 3 — 1 October 2012
© NXP B.V. 2012. All rights reserved.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
Sn+2
Sn+3
static
display RAM filling order
b
f
Sn+1
BP0
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
g
e
Sn+6
Sn
Sn+7
c
DP
d
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
Sn
a
b
f
g
multiplex
Sn+2
BP1
e
Sn+3
c
Sn+1
1:3
Sn+2
DP
d
a
b
Sn
multiplex
BP1
c
b
f
BP0
g
multiplex
e
BP1
c
d
g e d DP
n
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
MSB
a b
LSB
f
g e c d DP
n
rows
display RAM 0 b
rows/backplane
1 DP
outputs (BP)
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
DP
BP2
n
rows
display RAM 0 a
rows/backplane
1 c
BP3 outputs (BP) 2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged
Fig 12. Relationships between LCD layout, drive mode, display RAM filling order, and display data transmitted over the I2C-bus
PCA8533
20 of 54
© NXP B.V. 2012. All rights reserved.
Sn+1
f
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
a
Sn
1:4
BP2
DP
d
c b a
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
g
e
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
BP0
f
LSB
Universal LCD driver for low multiplex rates
Rev. 3 — 1 October 2012
All information provided in this document is subject to legal disclaimers.
Sn+1
MSB
columns
display RAM address/segment outputs (s)
byte1
byte2
BP0
1:2
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
a
Sn+4
Sn+5
LCD backplanes
NXP Semiconductors
PCA8533
Product data sheet
LCD segments
drive mode
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
• In static drive mode the eight transmitted data bits are placed into row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.6.3).
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
7.6.1 Data pointer
The addressing mechanism for the display RAM is realized using a data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see Table 7). Following this command, an
arriving data byte is stored at the display RAM address indicated by the data pointer. The
filling order is shown in Figure 12. After each byte is stored, the content of the data pointer
is automatically incremented by a value dependent on the selected LCD drive mode:
•
•
•
•
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early, then the state of the data pointer is
unknown. So, the data pointer must be rewritten before further RAM accesses.
7.6.2 Subaddress counter
The storage of display data is determined by the content of the subaddress counter.
Storage is allowed only when the content of the subaddress counter matches with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see Table 8). If the content of the subaddress counter and
the hardware subaddress do not match, then data storage is inhibited but the data pointer
is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCA8533 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
The hardware subaddress must not be changed while the device is being accessed on the
I2C-bus interface.
PCA8533
Product data sheet
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Rev. 3 — 1 October 2012
© NXP B.V. 2012. All rights reserved.
21 of 54
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.6.3 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 15 (see Figure 12 as
well).
Table 15. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 and so on, are not connected to any elements on the
display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 16.
Table 16. Entire RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 and so on, are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
c1/d7 d4
d1/e7 e4
:
1
a6
a3
a0/b6 b3
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
2
a5
a2
b5
b2
c5
c2
d5
d2
e5
e2
:
3
-
-
-
-
-
-
-
-
-
-
:
3
4
5
6
7
8
9
:
In the case described in Table 16 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8, and so on, have to be connected to elements on the display. This can be
achieved by a combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written
• The data-pointer (see Section 7.6.1 on page 21) has to be set to the address of bit a1
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6
• The data-pointer has to be set to the address of bit b1
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6
Depending on the method of writing to the RAM (standard or entire filling by rewriting),
some elements remain unused or can be used, but it has to be considered in the module
layout process as well as in the driver software design.
PCA8533
Product data sheet
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Rev. 3 — 1 October 2012
© NXP B.V. 2012. All rights reserved.
22 of 54
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
7.6.4 Writing over the RAM address boundary
In all multiplex drive modes, depending on the setting of the data pointer, it is possible to
fill the RAM over the RAM address boundary. If the PCA8533 is part of a cascade, the
additional bits fall into the next device that also generates the acknowledge signal. If the
PCA8533 is a single device or the last device in a cascade, the additional bits will be
discarded and no acknowledge signal will be generated.
7.6.5 Bank selection
7.6.5.1
Output bank selector
The output bank selector (see Table 9) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
selected LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The PCA8533 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. In the static drive mode, the bank-select command may request the contents of
row 2 to be selected for display instead of the contents of row 0. In the 1:2 multiplex mode,
the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
7.6.5.2
Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command (see
Table 9). The input bank selector functions independently to the output bank selector.
7.6.5.3
RAM bank switching
The PCA8533 includes a RAM bank switching feature in the static and 1:2 multiplex drive
modes. A bank can be thought of as one RAM row or a collection of RAM rows (see
Figure 13). The RAM bank switching gives the provision for preparing display information
in an alternative bank and to be able to switch to it once it is complete.
PCA8533
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 October 2012
© NXP B.V. 2012. All rights reserved.
23 of 54
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
GLVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6
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Fig 13. RAM banks in static and multiplex driving mode 1:2
There are two banks; bank 0 and bank 1. Figure 13 shows the location of these banks
relative to the RAM map. Input and output banks can be set independently from one
another with the Bank-select command (see Table 9 on page 6). Figure 14 shows the
concept.
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Fig 14. Bank selection
In the static drive mode, the bank-select command may request the contents of row 2 to
be selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the
contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it once it is assembled.
In Figure 15 an example is shown for 1:2 multiplex drive mode where the displayed data is
read from the first two rows of the memory (bank 0), while the transmitted data is stored in
the second two rows of the memory (bank 1).
PCA8533
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 1 October 2012
© NXP B.V. 2012. All rights reserved.
24 of 54
PCA8533
NXP Semiconductors
Universal LCD driver for low multiplex rates
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