PCA8534AH-Q900

PCA8534A Universal LCD driver for low multiplex rates Rev. 02 — 1 June 2010 Product data sheet 1. General description The PCA8534A is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 60 segments. It can be easily cascaded for larger LCD applications. The PCA8534A is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing, and by display memory switching (static and duplex drive modes). AEC-Q100 compliant for automotive applications. 2. Features and benefits Single-chip LCD controller and driver Selectable backplane drive configurations: static, 2, 3, or 4 backplane multiplexing 60 segment outputs allowing to drive: 30 7-segment alphanumeric characters 16 14-segment alphanumeric characters Any graphics of up to 240 elements Cascading supported for larger applications 60 × 4-bit display data storage RAM Wide LCD supply range: from 2.5 V for low threshold LCDs up to 6.5 V for guest-host LCDs and high threshold (automobile) twisted nematic LCDs Internal LCD bias generation with voltage follower buffers Selectable display bias configurations: static, 1⁄2, or 1⁄3 Wide logic power supply range: from 1.8 V to 5.5 V LCD and logic supplies may be separated Low power consumption 400 kHz I2C-bus interface Compatible with any microprocessors or microcontrollers No external components Display memory bank switching in static and duplex drive modes Auto-incremented display data loading Versatile blinking modes Silicon gate CMOS process 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 16. NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 3. Ordering information Table 1. Ordering information Package Name Description Delivery form Version tape and reel SOT315-1 Type number PCA8534AH/Q900 LQFP80 plastic low profile quad flat package; 80 leads; body 12 × 12 × 1.4 mm 4. Marking Table 2. Marking codes Marking code PCA8534A/Q900 Type number PCA8534AH/Q900 PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 2 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 5. Block diagram BP0 BP1 BP2 BP3 S0 to S59 60 VLCD BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS LCD VOLTAGE SELECTOR DISPLAY REGISTER DISPLAY CONTROL OUTPUT BANK SELECT AND BLINK CONTROL VSS LCD BIAS GENERATOR PCA8534A CLK SYNC CLOCK SELECT AND TIMING BLINKER TIMEBASE DISPLAY RAM OSC OSCILLATOR POWER-ON RESET COMMAND DECODE WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT SCL SDA INPUT FILTERS I2C-BUS CONTROLLER SUBADDRESS COUNTER SA0 VDD A0 A1 A2 013aaa268 Fig 1. Block diagram of PCA8534A PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 3 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 6. Pinning information 6.1 Pinning 80 S30 79 S29 78 S28 77 S27 76 S26 75 S25 74 S24 73 S23 72 S22 71 S21 70 S20 69 S19 68 S18 67 S17 66 S16 65 S15 64 S14 63 S13 62 S12 61 S11 S31 S32 S33 S34 S35 S36 S37 S38 S39 1 2 3 4 5 6 7 8 9 60 S10 59 S9 58 S8 57 S7 56 S6 55 S5 54 S4 53 S3 52 S2 51 S1 50 S0 49 VLCD 48 VSS 47 SA0 46 A2 45 A1 44 A0 43 OSC 42 SYNC 41 VDD S51 21 S52 22 S53 23 S54 24 S55 25 S56 26 S57 27 S58 28 S59 29 BP0 30 BP1 31 BP2 32 BP3 33 n.c. 34 n.c. 35 n.c. 36 n.c. 37 SDA 38 SCL 39 CLK 40 S40 10 S41 11 S42 12 S43 13 S44 14 S45 15 S46 16 S47 17 S48 18 S49 19 S50 20 PCA8534AH 013aaa269 Top view. For mechanical details, see Figure 24. Fig 2. Pin configuration for LQFP80 (PCA8534AH) PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 4 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 6.2 Pin description Table 3. Symbol S31 to S59 BP0 to BP3 n.c. SDA SCL CLK VDD SYNC OSC A0 to A2 SA0 VSS VLCD S0 to S30 Pin description Pin 1 to 29 Type output Description LCD segment output 31 to 59 LCD backplane output 0 to 3 not connected; do not connect and do not use as feed through I2C-bus serial data input and output I2C-bus serial clock input external clock input and internal clock output supply voltage cascade synchronization input and output (active LOW) enable input for internal oscillator subaddress counter input 0 to 2 I2C-bus slave address input 0 ground supply voltage LCD supply voltage LCD segment output 0 to 30 30 to 33 output 34 to 37 38 39 40 41 42 43 47 48 49 input/output input input/output supply input/output input input supply input 44 to 46 input 50 to 80 output PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 5 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 7. Functional description The PCA8534A is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 60 segments. The possible display configurations of the PCA8534A depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 4. All of these configurations can be implemented in the typical system shown in Figure 3. Table 4. Number of Backplanes 4 3 2 1 Elements 240 180 120 60 Selection of display configurations 7-segment alphanumeric Digits 30 22 15 7 Indicator symbols 30 26 15 11 14-segment alphanumeric Characters 16 12 8 4 Indicator symbols 16 12 8 4 240 (4 × 60) 180 (3 × 60) 120 (2 × 60) 60 (1 × 60) Dot matrix VDD R≤ tr 2Cb SDA SCL OSC VDD VLCD 60 segment drives LCD PANEL HOST MICROPROCESSOR/ MICROCONTROLLER PCA8534A 4 backplanes (up to 240 elements) A0 VSS A1 A2 SA0 VSS 013aaa270 Fig 3. Typical system configuration The host microprocessor or microcontroller maintains the 2-line I2C-bus communication channel with the PCA8534A. Biasing voltages for the multiplexed LCD waveforms are generated internally, removing the need for an external bias generator. The internal oscillator is selected by connecting pin OSC to VSS. The only other connections required to complete the system are the power supplies (VDD, VSS, and VLCD) and the LCD panel selected for the application. 7.1 Power-On Reset (POR) At power-on the PCA8534A resets to a default starting condition: • • • • • PCA8534A_2 All backplane and segment outputs are set to VLCD The selected drive mode is: 1:4 multiplex with 1⁄3 bias Blinking is switched off Input and output bank selectors are reset The I2C-bus interface is initialized All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 6 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates • The data pointer and the subaddress counter are cleared (set to logic 0) • The display is disabled Remark: Do not transfer data on the I2C-bus after a power-on for at least 1 ms to allow the reset action to complete. 7.2 LCD bias generator Fractional LCD biasing voltages are obtained from an internal voltage divider of three series resistors connected between pins VLCD and VSS. The center resistor is bypassed by switch if the 1⁄2 bias voltage level for the 1:2 multiplex drive mode configuration is selected. 7.3 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the mode-set command from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D) are given in Table 5. Table 5. LCD drive mode static Biasing characteristics Number of: LCD bias Backplanes Levels configuration 1 2 3 4 4 4 static 1⁄ 1⁄ 1⁄ 1⁄ 2 3 3 3 V off ( RMS ) -----------------------V LCD 0 0.354 0.333 0.333 0.333 V on ( RMS -----------------------) V LCD 1 0.791 0.745 0.638 0.577 V on ( RMS ) D = -----------------------V off ( RMS ) ∞ 2.236 2.236 1.915 1.732 1:2 multiplex 2 1:2 multiplex 2 1:3 multiplex 3 1:4 multiplex 4 A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are smaller. 1 Bias is calculated by ------------ , where the values for a are 1+a a = 1 for 1⁄2 bias a = 2 for 1⁄3 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) = a 2 + 2a + n ----------------------------2 n × (1 + a) (1) V LCD where the values for n are n = 1 for static drive mode n = 2 for 1:2 multiplex drive mode PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 7 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates n = 3 for 1:3 multiplex drive mode n = 4 for 1:4 multiplex drive mode The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2: V off ( RMS ) = a 2 – 2a + n ----------------------------2 n × (1 + a) (2) V LCD Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ) D = ---------------------- = V off ( RMS ) (a + 1) + (n – 1) ------------------------------------------2 (a – 1) + (n – 1) 2 (3) Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with 1⁄ 1⁄ 2 2 bias is 3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with 21 bias is ---------- = 1.528 . 3 The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD as follows: • 1:3 multiplex (1⁄2 bias): V LCD = 6 × V off ( RMS ) = 2.449V off ( RMS ) --------------------• 1:4 multiplex (1⁄2 bias): V LCD = ( 4 × 3 ) = 2.309V off ( RMS ) 3 These compare with V LCD = 3V off ( RMS ) when 1⁄3 bias is used. It should be noted that VLCD is sometimes referred as the LCD operating voltage. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 8 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 7.4 LCD drive mode waveforms 7.4.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD. Backplane and segment drive waveforms for this mode are shown in Figure 4. Tfr VLCD BP0 VSS VLCD Sn VSS VLCD state 1 (on) state 2 (off) LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 0V −VLCD (b) Resultant waveforms at LCD segment. mgl745 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = VLCD. Vstate2(t) = V(Sn + 1)(t) − VBP0(t). Voff(RMS) = 0 V. Fig 4. Static drive mode waveforms PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 9 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA8534A allows the use of 1⁄2 bias or 1⁄3 bias in this mode as shown in Figure 5 and Figure 6. Tfr VLCD BP0 VLCD / 2 VSS state 1 VLCD BP1 VLCD / 2 VSS VLCD Sn VSS VLCD state 2 LCD segments Sn+1 VSS (a) Waveforms at driver. VLCD VLCD / 2 state 1 0V −VLCD / 2 −VLCD VLCD VLCD / 2 state 2 0V −VLCD / 2 −VLCD (b) Resultant waveforms at LCD segment. mgl746 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.791VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.354VLCD. Fig 5. Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 10 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl747 LCD segments state 1 state 2 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.745VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 6. Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 11 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 7.4.3 1:3 Multiplex drive mode When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies, as shown in Figure 7. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD Sn 2VLCD / 3 VLCD / 3 VSS VLCD Sn+1 2VLCD / 3 VLCD / 3 VSS VLCD Sn+2 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD state 1 state 2 LCD segments (b) Resultant waveforms at LCD segment. mgl748 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.638VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 7. Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 12 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 7.4.4 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 8. Tfr VLCD BP0 2VLCD / 3 VLCD / 3 VSS VLCD BP1 2VLCD / 3 VLCD / 3 VSS VLCD BP2 2VLCD / 3 VLCD / 3 VSS VLCD BP3 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS VLCD state 1 state 2 LCD segments Sn Sn+1 Sn+2 2VLCD / 3 VLCD / 3 VSS VLCD 2VLCD / 3 VLCD / 3 VSS (a) Waveforms at driver. VLCD 2VLCD / 3 VLCD / 3 Sn+3 state 1 0V −VLCD / 3 −2VLCD / 3 −VLCD VLCD 2VLCD / 3 VLCD / 3 state 2 0V −VLCD / 3 −2VLCD / 3 −VLCD (b) Resultant waveforms at LCD segment. mgl749 Vstate1(t) = VSn(t) − VBP0(t). Von(RMS) = 0.577VLCD. Vstate2(t) = VSn(t) − VBP1(t). Voff(RMS) = 0.333VLCD. Fig 8. Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 13 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 7.5 Oscillator The internal logic and the LCD drive signals of the PCA8534A are timed by the frequency fclk, which equals either the built-in oscillator frequency fosc or the external clock frequency fclk(ext). The clock frequency fclk determines the LCD frame frequency (ffr). 7.5.1 Internal clock The internal oscillator is enabled by connecting pin OSC to pin VSS. In this case, the output from pin CLK is the clock signal for any cascaded PCA8534A in the system. 7.5.2 External clock Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fclk). A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. 7.6 Timing The PCA8534A timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCA8534A in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division of the clock frequency from either the internal or an external clock. Table 6. LCD frame frequencies Nominal frame frequency (Hz) 64 Frame frequency f clk f fr = ------24 7.7 Display register The display register holds the display data while the corresponding multiplex signals are generated. 7.8 Segment outputs The LCD drive section includes 60 segment outputs (S0 to S59) which should be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 60 segment outputs are required, the unused segment outputs must be left open-circuit. 7.9 Backplane outputs The LCD drive section includes four backplane outputs: BP0 to BP3. The backplane output signals are generated based on the selected LCD drive mode. • In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 14 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates If less than four backplane outputs are required the unused outputs can be left as an open-circuit. • In 1:3 multiplex drive mode: BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. • In 1:2 multiplex drive mode: BP0 and BP2, BP1 and BP3 respectively carry the same signals and can also be paired to increase the drive capabilities. • In static drive mode: the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. 7.10 Display RAM The display RAM is a static 60 × 4-bit RAM which stores LCD data. There is a one-to-one correspondence between • the bits in the RAM bitmap and the LCD elements • the RAM columns and the segment outputs • the RAM rows and the backplane outputs. Logic 1 in the RAM bit map indicates the on-state of the corresponding LCD segment, logic 0 indicates the off-state. The display RAM bit map, Figure 9, shows the rows 0 to 3 which correspond with the backplane outputs BP0 to BP3, and the columns 0 to 59 which correspond with the segment outputs S0 to S59. In multiplexed LCD applications the segment data of the first, second, third and fourth row of the display RAM are time-multiplexed with BP0, BP1, BP2, and BP3 respectively. display RAM addresses (columns)/segment outputs (S) 0 0 display RAM bits 1 (rows)/ backplane outputs 2 (BP) 3 001aah617 1 2 3 4 55 56 57 58 59 The display RAM bitmap shows the direct relationship between the display RAM column and the segment outputs; and between the bits in a RAM row and the backplane outputs. Fig 9. Display RAM bit map When display data is transmitted to the PCA8534A the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Figure 10; the RAM filling organization depicted applies equally to other LCD types. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 15 of 44 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Product data sheet Rev. 02 — 1 June 2010 16 of 44 PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. NXP Semiconductors drive mode LCD segments LCD backplanes display RAM filling order columns display RAM address/segment outputs (s) byte1 transmitted display byte Sn+2 Sn+3 static Sn+4 Sn+5 Sn+6 e d f a b g c Sn+1 Sn Sn+7 DP BP0 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n c x x x n+1 b x x x n+2 a x x x n+3 f x x x n+4 g x x x n+5 e x x x n+6 d x x x n+7 DP x x x MSB cba f LSB g e d DP BP0 Sn 1:2 Sn+1 f g a b columns display RAM address/segment outputs (s) byte1 byte2 rows display RAM 0 rows/backplane 1 outputs (BP) 2 3 n a b x x n+1 f g x x n+2 e c x x n+3 d DP x x MSB ab f LSB g e c d DP multiplex Sn+2 Sn+3 e d c BP1 DP Sn+1 1:3 Sn+2 f a b g BP0 Sn n rows display RAM 0 b rows/backplane 1 DP outputs (BP) 2c 3x columns display RAM address/segment outputs (s) byte1 byte2 byte3 n+1 a d g x n+2 f e x x MSB b DP c a d g f LSB Universal LCD driver for low multiplex rates multiplex e d c BP1 DP BP2 e Sn 1:4 f a b g columns display RAM address/segment outputs (s) byte1 byte2 byte3 byte4 byte5 BP0 BP2 n rows display RAM 0 a rows/backplane 1c BP3 outputs (BP) 2 b 3 DP n+1 f e g d MSB a c b DP f LSB egd multiplex e c d PCA8534A BP1 DP Sn+1 001aaj646 x = data bit unchanged. Fig 10. Relationship between LCD layout, drive mode, display RAM storage order, and display data transmitted over the I2C-bus NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates The following applies to Figure 10: • Static mode: the eight transmitted data bits are placed in row 0 to eight successive display RAM addresses. • 1:2 multiplex mode: the eight transmitted data bits are placed in row 0 and 1 to four successive display RAM addresses. • 1:3 multiplex mode: the eight transmitted data bits are placed in row 0, 1, and 2 to three successive addresses. However, bit 2 of the third address is left unchanged. This last bit can, if necessary, be controlled by an additional transfer to this address but avoid overriding adjacent data because full bytes are always transmitted. • 1:4 multiplex mode: the eight transmitted data bits are placed in row 0, 1, 2, and 3 to two successive display RAM addresses. 7.11 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 12). Following this command, an arriving data byte is stored at the display RAM address indicated by the data pointer. The filling order is shown in Figure 10. After each byte is stored, the content of the data pointer is automatically incremented by a value dependent on the selected LCD drive mode: • • • • In static drive mode by eight In 1:2 multiplex drive mode by four In 1:3 multiplex drive mode by three In 1:4 multiplex drive mode by two If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer should be re-written prior to further RAM accesses. 7.12 Subaddress counter The storage of display data is conditioned by the contents of the subaddress counter. Storage is allowed only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined by the device-select command (see Table 13). If the content of the subaddress counter and the hardware subaddress do not match then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. In cascaded applications each PCA8534A in the cascade must be addressed separately. Initially, the first PCA8534A is selected by sending the device-select command matching the first device's hardware subaddress. Then the data pointer is set to the preferred display RAM address by sending the load-data-pointer command. Once the display RAM of the first PCA8534A has been written, the second PCA8534A is selected by sending the device-select command again. This time however the command matches the second device's hardware subaddress. Next the load-data-pointer command is sent to select the preferred display RAM address of the second PCA8534A. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 17 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates This last step is very important because during writing data to the first PCA8534A, the data pointer of the second PCA8534A is incremented. In addition, the hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 7.13 Output bank selector The output bank selector (see Table 14), selects one of the four rows per display RAM address for transfer to the display register. The actual row selected depends on the LCD drive mode in operation and on the instant in the multiplex sequence. • In 1:4 multiplex mode: all RAM addresses of row 0 are selected, followed sequentially by the contents of row 1, row 2, and then row 3. • In 1:3 multiplex mode: rows 0, 1, and 2 are selected sequentially. • In 1:2 multiplex mode: rows 0 and 1 are selected. • In the static mode: row 0 is selected. The SYNC signal resets these sequences to the following starting points: row 3 for 1:4 multiplex, row 2 for 1:3 multiplex, row 1 for 1:2 multiplex and row 0 for static mode. The PCA8534A includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In static drive mode, the bank-select command may request the contents of row 2 to be selected for display instead of the contents of row 0. In 1:2 multiplex drive mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1. This enables preparation of display information in an alternative bank and the ability to switch to it once it has been assembled. 7.14 Input bank selector The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The input bank selector functions independently to the output bank selector. 7.15 Blinker The display blinking capabilities of the PCA8534A are very versatile. The whole display can be blinked at frequencies set by the blink-select command (see Table 15). The blinking frequencies are fractions of the clock frequency. The ratios between the clock and blinking frequencies depend on the mode in which the device is operating (see Table 7). PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 18 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates Table 7. Blink frequencies Assuming that fclk = 1536 Hz. Blink mode Off 1 Operating mode ratio f clk f blink = -------768 f clk f blink = ----------1536 f clk f blink = ----------3072 Blink frequency Blinking off 2 Hz 2 1 Hz 3 0.5 Hz An additional feature is for the arbitrary selection of LCD segments to be blinked. This applies to the static and 1:2 multiplex drive modes and is implemented without any communication overheads. Using the output bank selector, the displayed RAM banks are exchanged with alternate RAM banks at the blinking frequency. This mode can also be specified by the blink-select command. In the 1:3 and 1:4 multiplex modes, where no alternate RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. If the entire display needs to be blinked at a frequency other than the nominal blinking frequency, this can be done using the mode-set command to set and reset the display enable bit E at the required rate (see Table 11). 7.16 Characteristics of the I2C-bus The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.16.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 11). SDA SCL data line stable; data valid change of data allowed mba607 Fig 11. Bit transfer PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 19 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 7.16.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition - S. A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition - P (see Figure 12). SDA SDA SCL S START condition P STOP condition SCL mbc622 Fig 12. Definition of START and STOP conditions 7.16.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 13). MASTER TRANSMITTER/ RECEIVER SDA SCL SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER mga807 Fig 13. System configuration 7.16.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle. • A slave receiver, which is addressed, must generate an acknowledge after the reception of each byte. • A master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. • The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 20 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates • A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is illustrated in Figure 14. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement mbc602 1 2 8 9 Fig 14. Acknowledgement of the I2C-bus 7.16.5 I2C-bus controller The PCA8534A acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCA8534A are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. In single device applications, the hardware subaddress inputs A0, A1, and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1, and A2 are tied to VSS or VDD using a binary coding scheme, so that no two devices with a common I2C-bus slave address have the same hardware subaddress. 7.16.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 7.16.7 I2C-bus protocol Two I2C-bus slave addresses (0111 000 and 0111 001) are used to address the PCA8534A. The entire I2C-bus slave address byte is shown in Table 8. Table 8. Bit I2C slave address byte Slave address 7 MSB 0 1 1 1 0 0 SA0 6 5 4 3 2 1 0 LSB R/W PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 21 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates The PCA8534A is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCA8534A will respond to, is defined by the level tied to its SA0 input (VSS for logic 0 and VDD for logic 1). Having two reserved slave addresses allows the following on the same I2C-bus: • Up to 16 PCA8534A for very large LCD applications • The use of two types of LCD multiplex drive The I2C-bus protocol is shown in Figure 15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCA8534A slave addresses available. All PCA8534A whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCA8534A whose SA0 inputs are set to the alternative level. R/W = 0 slave address S CR S011100A0A OS 0 control byte RAM/command byte M AS B L SP B EXAMPLES a) transmit two bytes of RAM data S S011100A0A01 0 A RAM DATA A RAM DATA AP b) transmit two command bytes S S011100A0A10 0 A COMMAND A00 A COMMAND AP c) transmit one command byte and two RAM date bytes S S011100A0A10 0 A COMMAND A01 A RAM DATA A RAM DATA AP mgl752 Fig 15. I2C-bus protocol After an acknowledgement, one or more command bytes follow that define the status of each addressed PCA8534A. The last command byte sent is identified by resetting its most significant bit, continuation bit CO (see Figure 16). The command bytes are also acknowledged by all addressed PCA8534A on the bus. MSB 7 6 5 4 3 2 1 LSB 0 CO RS not relevant mgl753 Fig 16. Control byte format PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 22 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates Control byte description Symbol CO 0 1 Value Description continue bit last control byte control bytes continue register selection 0 1 command register data register not relevant Table 9. Bit 7 6 RS 5 to 0 - The command bytes and control bytes are also acknowledged by all addressed PCA8534A connected to the bus. The display bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated. The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed PCA8534A. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART I2C-bus access. 7.17 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. There are five commands: Table 10. Command Bit Mode-set Load-data-pointer Device-select Bank-select Blink-select Definition of commands Operation Code 7 1 0 1 1 1 6 1 P6 1 1 1 5 0 P5 1 1 1 4 0 P4 0 1 1 3 E P3 0 1 0 2 B P2 A2 0 A 1 M1 P1 A1 I BF1 0 M0 P0 A0 O BF0 Table 11 Table 12 Table 13 Table 14 Table 15 Reference PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 23 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates Mode-set command bit description Symbol E Value 1100 Description fixed value display status the possibility to disable the display allows implementation of blinking under external control 0 1 disabled enable LCD bias configuration 0 1 1⁄ 1⁄ 3 2 Table 11. Bit 7 to 4 3 2 B bias bias 1 to 0 M[1:0] 01 10 11 00 LCD drive mode selection static; 1 backplane 1:2 multiplex; 2 backplanes 1:3 multiplex; 3 backplanes 1:4 multiplex; 4 backplanes Table 12. Bit 7 6 to 0 Load-data-pointer command bit description Symbol P[6:0] Value 0 Description fixed value 000 0000 to 7-bit binary value of 0 to 59 011 1011 Table 13. Bit 7 to 3 2 to 0 Table 14. Bit 7 to 2 1 Device-select command bit description Symbol A[2:0] Value 11100 000 to 111 Description fixed value 3-bit binary value of 0 to 7 Bank-select command bit description Symbol I 0 1 Value 111110 Description Static fixed value input bank selection: storage of arriving display data RAM bit 0 RAM bit 2 RAM bit 0 RAM bit 2 RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 1:2 multiplex[1] 0 O 0 1 output bank selection: retrieval of LCD display data [1] The bank select command has no effect in 1:3 or 1:4 multiplex drive modes. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 24 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates Blink-select command bit description Symbol A 0 1 Value 11110 Description fixed value blink mode selection normal blinking[1] blinking by alternating display RAM banks blink frequency selection[2] 00 01 10 11 off 1 2 3 Table 15. Bit 7 to 3 2 1 to 0 BF[1:0] [1] [2] Only normal blinking can be selected in multiplexer 1:3 or 1:4 drive modes. The blink frequencies are shown in Table 7. 7.18 Display controller The display controller executes the commands identified by the command decoder. It contains the status registers of the PCA8534A and coordinates their effects. The controller also loads display data into the display RAM as required by the storage order. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 25 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 8. Internal circuitry VDD VDD SA0 VSS VDD VSS CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VDD VSS A0, A1, A2 VLCD VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VSS S0 to S59 VSS 001aah615 Fig 17. Device protection diagram PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 26 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 9. Limiting values CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. Table 16. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD IDD VLCD IDD(LCD) ISS VI II VO IO Ptot P/out VESD Parameter supply voltage supply current LCD supply voltage LCD supply current ground supply current input voltage input current output voltage output current total power dissipation power dissipation per output electrostatic discharge voltage HBM MM CDM Ilu Tstg Toper [1] [2] [3] [4] [5] [6] [7] [3] [4] [5] [6] [7] [1] [1] [1] [2] [1][2] Conditions Min −0.5 −50 −0.5 −50 −50 −0.5 −10 −0.5 −0.5 −10 −65 −40 Max +6.5 +50 +7.5 +50 +50 +6.5 +10 +6.5 +7.5 +10 400 100 ±3000 ±200 ±1000 200 +150 +85 Unit V mA V mA mA V mA V V mA mW mW V V V mA °C °C latch-up current storage temperature operating temperature Pins SDA, SCL, CLK, SYNC, SA0, OSC and A0 to A2. Pins S0 to S59 and BP0 to BP3. Pass level; Human Body Model (HBM), according to Ref. 5 “JESD22-A114”. Pass level; Machine Model (MM), according to Ref. 6 “JESD22-A115”. Pass level; Charged-Device Model (CDM), according to Ref. 7 “JESD22-C101” Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)). According to the NXP store and transport requirements (see Ref. 10 “NX3-00092”) the devices have to be stored at a temperature of +8 °C to +45 °C and a humidity of 25 % to 75 %. For long term storage products deviant conditions are described in that document. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 27 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 10. Static characteristics Table 17. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Parameter Supplies VDD VLCD IDD Logic VI VIL VIH VPOR IOL input voltage LOW-level input voltage HIGH-level input voltage power-on reset voltage LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V; on pins CLK and SYNC HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V; on pin CLK leakage current VI = VDD or VSS; on pins SA0, A0 to A2 and CLK VI = VDD; on pin OSC CI VI VIL VIH IOL IL Ci input capacitance input voltage LOW-level input voltage HIGH-level input voltage LOW-level output current VOL = 0.4 V; VDD = 5 V; on pin SDA leakage current input capacitance VI = VDD or VSS [4] [4] Conditions Min 1.8 2.5 Typ - Max 5.5 6.5 20 60 Unit V V μA μA supply voltage LCD supply voltage supply current fclk(ext) = 1536 Hz fclk(ext) = 1536 Hz [1][2] [1][3] VSS − 0.5 IDD(LCD) LCD supply current VDD + 0.5 V 1.3 0.3VDD VDD 1.6 V V V mA on pins CLK, SYNC, OSC, A0 to A2 and SA0 on pins CLK, SYNC, OSC, A0 to A2 and SA0 VSS 0.7VDD 1.0 1 IOH IL 1 −1 −1 - - +1 +1 7 5.5 0.3VDD 0.2VDD 5.5 +1 7 mA μA μA pF V V V V mA μA pF I2C-bus; pins SDA and SCL VSS − 0.5 pin SCL pin SDA VSS VSS 0.7VDD 3 −1 - LCD outputs Output pins BP0, BP1, BP2 and BP3 VBP RBP VS RS [1] [2] [3] [4] [5] voltage on pin BP resistance on pin BP voltage on pin S resistance on pin S Cbpl = 35 nF VLCD = 5 V Csgm = 35 nF VLCD = 5 V [5] [5] −100 −100 - 1.5 6.0 +100 10 +100 13.5 mV kΩ mV kΩ Output pins S0 to S59 LCD outputs are open circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. For typical values, see Figure 18. For typical values, see Figure 19. Not tested, design specification only. Outputs measured individually and sequentially. All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. PCA8534A_2 Product data sheet Rev. 02 — 1 June 2010 28 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 5 IDD (μA) 4 001aal523 3 2 1 0 2 3 4 5 VDD (V) 6 Tamb = 30 °C; 1:4 multiplex; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected; I2C-bus inactive. Fig 18. Typical IDD with respect to VDD 20 IDD(LCD) (μA) 16 001aal524 12 8 4 0 3 5 7 VLCD (V) 9 Tamb = 30 °C; 1:4 multiplex; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected. Fig 19. Typical IDD(LCD) with respect to VLCD PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 29 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 11. Dynamic characteristics Table 18. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Clock Internal: output pin CLK fosc fclk(ext) tclk(H) tclk(L) tPD(SYNC_N) tSYNC_NL tPD(drv) I2C-bus: Pin SCL fSCL tLOW tHIGH Pin SDA tSU;DAT tHD;DAT tBUF tSU;STO tHD;STA tSU;STA tr tf Cb tw(spike) [1] [2] Parameter Conditions Min Typ Max Unit oscillator frequency external clock frequency HIGH-level clock time LOW-level clock time SYNC propagation delay SYNC LOW time driver propagation delay timing[2] SCL frequency LOW period of the SCL clock HIGH period of the SCL clock data set-up time data hold time bus free time between a STOP and START condition set-up time for STOP condition hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line spike pulse width VDD = 5 V VDD = 5 V [1] 960 797 130 130 1 1536 1536 30 - 3046 3046 30 Hz Hz μs μs ns μs μs External: input pin CLK Synchronization: input pin SYNC Outputs: pins BP0 to BP3 and S0 to S59 VLCD = 5 V - 1.3 0.6 100 0 1.3 0.6 0.6 0.6 - - 400 0.3 0.3 400 50 kHz μs μs ns ns μs μs μs μs μs μs pF ns Pins SCL and SDA Typical output (duty cycle δ = 50 %). All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 30 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 1 / fclk tclk(H) tclk(L) 0.7VDD CLK 0.3VDD SYNC 0.7VDD 0.3VDD tPD(SYNC_N) tSYNC_NL 0.5 V tPD(SYNC_N) BP0 to BP3, and S0 to S59 tPD(drv) (VDD = 5 V) 0.5 V 001aah618 Fig 20. Driver timing waveforms SDA tBUF tLOW tf SCL tHD;STA tr tHD;DAT tHIGH tSU;DAT SDA tSU;STA tSU;STO mga728 Fig 21. I2C-bus timing waveforms PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 31 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 12. Application information 12.1 Cascaded operation Large display configurations of up to 16 PCA8534A can be recognized on the same I2C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable I2C-bus slave address (SA0). Table 19. Cluster 1 Addressing cascaded PCA8534A Bit SA0 0 Pin A2 0 0 0 0 1 1 1 1 2 1 0 0 0 0 1 1 1 1 Pin A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Pin A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Device 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 If cascaded PCA8534A are synchronized, they can share the backplane signals from one of the devices in the cascade. This is cost-effective in large LCD applications because the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other PCA8534A in the cascade contribute additional segment outputs but their backplane outputs are left open-circuit (see Figure 22). PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 32 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates VDD SDA SCL SYNC CLK OSC A0 VLCD VDD tr 2Cb SDA SCL SYNC CLK OSC VSS A0 A1 A2 A1 A2 VLCD 60 segment drives PCA8534A BP0 to BP3 (open-circuit) SA0 VSS LCD PANEL R≤ VDD VLCD 60 segment drives HOST MICROPROCESSOR/ MICROCONTROLLER PCA8534A 4 backplanes BP0 to BP3 SA0 VSS 013aaa271 Fig 22. Cascaded PCA8534A configuration The SYNC line is provided to maintain the correct synchronization between all cascaded PCA8534A. Synchronization is guaranteed after a power-on reset. The only time that SYNC is likely to be needed is if synchronization is accidentally lost (e.g. by noise in adverse electrical environments or by defining a multiplex mode when PCA8534A with different SA0 levels are cascaded). SYNC is organized as an input/output pin. The output selection is realized as an open-drain driver with an internal pull-up resistor. A PCA8534A asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost, it is restored by the first PCA8534A to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCA8534A are shown in Figure 23. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 33 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates Tfr = 1 ffr BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. BP0 (1/3 bias) SYNC (d) 1:4 multiplex drive mode. mgl755 Fig 23. Synchronization of the cascade for various PCA8534A drive modes The contact resistance between the SYNC pins of cascaded devices must be controlled. If the resistance is too high, the device will not be able to synchronize properly. Table 20 shows the maximum contact resistance values. Table 20. 2 3 to 5 6 to 10 11 to 16 SYNC contact resistance Maximum contact resistance 6000 Ω 2200 Ω 1200 Ω 700 Ω Number of devices The PCA8534A can always be cascaded with other devices of the same type or conditionally with other devices of the same family. This allows optimal drive selection for a given number of pixels to display. Figure 20 and Figure 23 show the timing of the synchronization signals. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 34 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates In a cascaded configuration only one PCA8534A master must be used as clock source. All other PCA8534A in the cascade must be configured as slave such that they receive the clock from the master. If an external clock source is used, all PCA8534A in the cascade must be configured such as to receive the clock from that external source (pin OSC connected to VDD). Thereby it must be ensured that the clock tree is designed such that on all PCA8534A the clock propagation delay from the clock source to all PCA8534A in the cascade is as equal as possible since otherwise synchronization artefacts may occur. In mixed cascading configurations, care has to be taken that the specifications of the individual cascaded devices are met at all times. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 35 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 13. Package outline LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1 c y X A 60 61 41 40 Z E e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3) θ e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 θ 7 o 0 o 14.15 14.15 13.85 13.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 24. Package outline SOT315-1 (LQFP80) PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 36 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 37 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 25) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 21 and 22 Table 21. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 22. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 25. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 38 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 39 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 16. Abbreviations Table 23. Acronym AEC CMOS CDM DC HBM I2C IC LCD LSB MM MSB MSL PCB POR RAM RC RMS SCL SDA SMD Abbreviations Description Automotive Electronics Council Complementary Metal-Oxide Semiconductor Charged Device Model Direct Current Human Body Model Inter-Integrated Circuit Integrated Circuit Liquid Crystal Display Least Significant Bit Machine Model Most Significant Bit Moisture Sensitivity Level Printed-Circuit Board Power-On Reset Random Access Memory Resistance and Capacitance Root Mean Square Serial Clock Line Serial DAta line Surface-Mount Device PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 40 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 17. References [1] [2] [3] [4] [5] [6] [7] [8] [9] AN10365 — Surface mount reflow soldering description IEC 60134 — Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 — Protection of electronic devices from electrostatic phenomena IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model (MM) JESD22-C101 — Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components JESD78 — IC Latch-Up Test JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [10] NX3-00092 — NXP store and transport requirements [11] SNV-FA-01-02 — Marking Formats Integrated Circuits [12] UM10204 — I2C-bus specification and user manual 18. Revision history Table 24. Revision history Release date 20100601 Data sheet status Product data sheet Product data sheet Change notice Supersedes PCA8534A_1 Document ID PCA8534A_2 Modifications: PCA8534A_1 • Corrected marking code in Table 2 20100415 PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 41 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 42 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA8534A_2 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 02 — 1 June 2010 43 of 44 NXP Semiconductors PCA8534A Universal LCD driver for low multiplex rates 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . 6 7.2 LCD bias generator . . . . . . . . . . . . . . . . . . . . . 7 7.3 LCD voltage selector . . . . . . . . . . . . . . . . . . . . 7 7.4 LCD drive mode waveforms . . . . . . . . . . . . . . . 9 7.4.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9 7.4.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10 7.4.3 1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12 7.4.4 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13 7.5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.1 Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.5.2 External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.6 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.7 Display register . . . . . . . . . . . . . . . . . . . . . . . . 14 7.8 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14 7.9 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14 7.10 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.11 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.12 Subaddress counter . . . . . . . . . . . . . . . . . . . . 17 7.13 Output bank selector . . . . . . . . . . . . . . . . . . . 18 7.14 Input bank selector . . . . . . . . . . . . . . . . . . . . . 18 7.15 Blinker. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.16 Characteristics of the I2C-bus. . . . . . . . . . . . . 19 7.16.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.16.2 START and STOP conditions . . . . . . . . . . . . . 20 7.16.3 System configuration . . . . . . . . . . . . . . . . . . . 20 7.16.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.16.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 21 7.16.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.16.7 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21 7.17 Command decoder . . . . . . . . . . . . . . . . . . . . . 23 7.18 Display controller . . . . . . . . . . . . . . . . . . . . . . 25 8 Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 28 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 12 Application information. . . . . . . . . . . . . . . . . . 32 12.1 Cascaded operation . . . . . . . . . . . . . . . . . . . . 32 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 19.1 19.2 19.3 19.4 20 21 Package outline. . . . . . . . . . . . . . . . . . . . . . . . Handling information . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 37 37 37 37 38 38 40 41 41 42 42 42 42 43 43 44 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2010. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 June 2010 Document identifier: PCA8534A_2