PCA8576FUG/2DA/QKP

PCA8576F Automotive 40 × 4 LCD driver Rev. 3 — 3 December 2014 Product data sheet 1. General description The PCA8576F is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily cascaded for larger LCD applications. The PCA8576F is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). For a selection of NXP LCD segment drivers, see Table 28 on page 46. 2. Features and benefits                   1. AEC-Q100 grade 2 compliant for automotive applications Single chip LCD controller and driver Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing Selectable display bias configuration: static, 1⁄2, or 1⁄3 Internal LCD bias generation with voltage-follower buffers 40 segment drives:  Up to 20 7-segment numeric characters  Up to 10 14-segment alphanumeric characters  Any graphics of up to 160 segments/elements 40  4-bit RAM for display data storage Auto-incremented display data loading across device subaddress boundaries Display memory bank switching in static and duplex drive modes Versatile blinking modes Independent supplies possible for LCD and logic voltages Wide power supply range: from 1.8 V to 5.5 V Wide LCD supply range:  From 2.5 V for low-threshold LCDs  Up to 8.0 V for high-threshold twisted nematic LCDs Low power consumption 400 kHz I2C-bus interface May be cascaded for large LCD applications (up to 1280 segments/elements possible) No external components required Compatible with chip-on-glass and chip-on-board technology The definition of the abbreviations and acronyms used in this data sheet can be found in Section 19. PCA8576F NXP Semiconductors Automotive 40 × 4 LCD driver 3. Ordering information Table 1. Ordering information Type number Package PCA8576FUG Name Description Version bare die 59 bumps PCA8576FUG 3.1 Ordering options Table 2. Ordering options Product type number Sales item (12NC) Orderable part number IC revision Delivery form PCA8576FUG/2DA/Q1 935302565026 PCA8576FUG/2DA/QKP 1 chips in tray 4. Marking Table 3. Marking codes Product type number Marking code PCA8576FUG/2DA/Q1 PC8576F-1 5. Block diagram %3 %3 %3 %3 6WR6  9/&' %$&.3/$1( 2873876 ',63/$ 6.5 V 2.5 - 5.5 V VDD < 2.5 V 2.5 - 6.5 V 2.5 - 8.0 V Supplies VDD VLCD LCD supply voltage VDD  2.5 V supply current IDD - 6 20 A - 2.7 - A - 18 30 A - 17.5 - A VSS - 0.3VDD V 0.7VDD - VDD V on pins CLK and SYNC 1 - - mA on pin SDA 3 - - mA fclk(ext) = 1536 Hz [1][2] VDD = 3.0 V; Tamb = 25 C IDD(LCD) LCD supply current [1] fclk(ext) = 1536 Hz VDD(LCD) = 3.0 V; Tamb = 25 C Logic[3] VIL LOW-level input voltage on pins CLK, SYNC, OSC, A0, A1, T1, SA0, SCL, SDA VIH HIGH-level input voltage on pins CLK, SYNC, OSC, A0, A1, T1, SA0, SCL, SDA IOL LOW-level output current output sink current; VOL = 0.4 V; VDD = 5 V [4][5] IOH(CLK) HIGH-level output current on pin CLK output source current; VOH = 4.6 V; VDD = 5 V 1 - - mA IL leakage current VI = VDD or VSS; on pins CLK, SCL, SDA, A0, A1, T1, SA0 1 - +1 A IL(OSC) leakage current on pin OSC VI = VDD 1 - +1 A CI input capacitance - - 7 pF 100 - +100 mV on pins BP0 to BP3 - 1.5 - k on pins S0 to S39 - 6.0 - k [6] LCD outputs VO output voltage variation on pins BP0 to BP3 and S0 to S39 RO output resistance VLCD = 5 V [7] [1] LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. [2] For typical values, see Figure 26. [3] The I2C-bus interface of PCA8576F is 5 V tolerant. [4] When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 19 (see Figure 25 as well). [5] Propagation delay of driver between clock (CLK) and LCD driving signals. [6] Periodically sampled, not 100 % tested. [7] Outputs measured one at a time. PCA8576F Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 34 of 54 PCA8576F NXP Semiconductors Automotive 40 × 4 LCD driver DDD  ,'' —$          9''9  Tamb = 30 C; 1:4 multiplex drive mode; VLCD = 6.5 V; fclk(ext) = 1.536 kHz; all RAM written with logic 1; no display connected; I2C-bus inactive. Fig 26. Typical IDD with respect to VDD PCA8576F Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 35 of 54 PCA8576F NXP Semiconductors Automotive 40 × 4 LCD driver 13. Dynamic characteristics Table 21. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 8.0 V; Tamb = 40 C to +105 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Clock fclk(int) internal clock frequency fclk(ext) external clock frequency ffr frame frequency [1] 3505 4800 6240 Hz 960 - 6720 Hz internal clock 146 200 260 Hz external clock 40 - 280 Hz tclk(H) HIGH-level clock time 60 - - s tclk(L) LOW-level clock time 60 - - s - 30 - ns Synchronization tPD(SYNC_N) SYNC propagation delay tSYNC_NL SYNC LOW time tPD(drv) driver propagation delay VLCD = 5 V [2] 1 - - s - - 30 s I2C-bus[3] Pin SCL fSCL SCL clock frequency - - 400 kHz tLOW LOW period of the SCL clock 1.3 - - s tHIGH HIGH period of the SCL clock 0.6 - - s tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - s tSU;STO set-up time for STOP condition 0.6 - - s tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 s fSCL < 125 kHz - - 1.0 s tf fall time of both SDA and SCL signals - - 0.3 s Cb capacitive load for each bus line - - 400 pF tw(spike) spike pulse width - - 50 ns on the I2C-bus [1] Typical output duty factor: 50 % measured at the CLK output pin. [2] Not tested in production. PCA8576F Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 December 2014 © NXP Semiconductors N.V. 2014. All rights reserved. 36 of 54 PCA8576F NXP Semiconductors Automotive 40 × 4 LCD driver [3] All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. IFON WFON+ WFON/ 9'' &/. 9'' 9'' 6