PCA8802B

PCA8802 Smartcard RTC; ultra low power oscillator with integrated counter for initiating one time password generation Rev. 01 — 19 February 2009 Product data sheet 1. General description The PCA8802 is a CMOS integrated circuit for battery operation, typically supplied by button cells or flexible polymer batteries. Incorporated is a 32.768 kHz quartz crystal oscillator circuit including the two load capacitors. The circuit is optimized for a quartz with 6 pF load capacitance specification. Higher values can also be used with the addition of external load capacitors. The main function of the oscillator is to generate a 1⁄32 Hz clock signal which is used to increment a 24 bit binary counter. The counter can be read over the serial interface and may also be set to any desired value. Control over the divider chain also allows for accurate starting of the counter. Incrementing of the counter value during read is prevented by freezing of the counter during access. An interrupt signal is also available and is triggered coincident with the counter updating. This signal may be used as a wake-up for a microcontroller. 2. Features I 32.768 kHz quartz oscillator, amplitude regulated with excellent frequency stability and high immunity to leakage currents I Very low current consumption: typically 130 nA I Two wire serial interface (I2C-bus) I Integrated 24 bit counter with auto increment every 32 seconds I Interrupt output for processor wake-up I Stop function for accurate time setting and current saving during shelf life I User test modes for accelerated application testing and development I Two integrated quartz crystal oscillator capacitors 3. Applications I One time password function generators I Ultra low power time keeper circuit NXP Semiconductors PCA8802 Smartcard RTC 4. Ordering information Table 1. Ordering information Package Name Description Delivery form Version PCA8802CX PCA8802U Type number PCA8802CX8/B/1 PCA8802CX wafer level chip-size package; 8 bumps; chip with solder bumps in tape 1.19 × 1.14 × 0.29 mm and reel PCA8802U/2AA/1 PCA8802U wafer level chip-size package; 8 bumps; chip with gold bumps in tray 1.19 × 1.14 × 0.22 mm 5. Marking Table 2. Marking codes Marking code PC8802-1 PC8802-1 Type number PCA8802CX8/B/1 PCA8802U/2AA/1 6. Block diagram VDD VSS OSCI 32.768 kHz OSCILLATOR DIVIDE 220 PULSE GENERATOR INT OSCO 1/32 Hz 24-BIT COUNTER reset TEST SERIAL INTERFACE AND CONTROL REGISTERS SDA SCL 001aaj164 Fig 1. Block diagram PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 2 of 34 NXP Semiconductors PCA8802 Smartcard RTC 7. Pinning information 7.1 Pinning OSCI SCL 7 8 SDA 7 8 SDA INT 001aaj151 5 OSCO 4 PCA8802CX 6 VSS 3 VDD 2 TEST Top view. For mechanical details, see Figure 30. Fig 2. Pinning diagram of PCA8802CX OSCI 5 OSCO 4 PCA8802U 6 3 Top view. For mechanical details, see Figure 31. Fig 3. Pinning diagram of PCA8802U PCA8802_1 TEST VDD 2 1 SCL VSS INT 001aaj257 1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 3 of 34 NXP Semiconductors PCA8802 Smartcard RTC 7.2 Pin description Table 3. Symbol INT VDD TEST OSCO OSCI VSS SCL SDA Pin description for PCA8802 Pin 1 2 3 4 5 6 7 8 Description interrupt and test mode output, push-pull supply voltage test pin; must be connected to VSS oscillator output oscillator input ground serial interface, clock serial interface, bidirectional data line; push-pull 8. Device protection diagram VSS OSCI SCL OSCO SDA TEST INT PCA8802 VDD 001aaj167 Fig 4. Diode protection diagram PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 4 of 34 NXP Semiconductors PCA8802 Smartcard RTC 9. Functional description The PCA8802 is an ultra low power device for battery operations. The integrated oscillator circuit generates a 1⁄32 Hz clock signal to increment a 24 bit counter. The communication between the PCA8802 and other devices is made via an I2C-bus. The device is always running but for longer storage time it can be switched off and on again in case of delivery. The functions of the device can be controlled with the following instruction set: Table 4. wrt_cmd dvs_cmd pwd_cmd 32k_cmd fst_cmd set_cmd rd_cmd Instruction set overview Description device write access divider start or stop switch low power mode switch 32.768 kHz clock signal on the pin INT switch fast system development mode switch set counter instruction counter read instruction Reference Section 9.6.2 Section 9.6.3 Section 9.6.4 Section 9.6.5 Section 9.6.6 Section 9.6.7 Section 9.6.8 Instruction 9.1 Oscillator The 32.768 kHz oscillator includes two integrated load capacitors and an automatic gain control to ensure a reliable start-up. For prototype development and system debugging, it is possible to output a 32.768 kHz square wave on the INT pin with the 32k_cmd instruction. 9.1.1 Power-on At initial power-on, when the oscillator has not yet started, a reset will be generated. During this state the serial interface will not respond when accessed. To ensure that the oscillator has started and the serial interface is accessible, it is recommended that the master attempts to make write-read accesses to the counter register. instructions will be ignored instructions will be accepted VDD oscillation t oscillation now stable 001aaj166 Exit from Power-down mode will give the same behavior as start-up. Fig 5. Power-on reset PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 5 of 34 NXP Semiconductors PCA8802 Smartcard RTC 9.1.2 Low power operation With the power-down instruction (pwd_cmd) the oscillator can be stopped and the device can be put into a low power state where power consumption is reduced to an absolute minimum. The chip would normally reset when the oscillator is stopped, so to prevent a reset of the chip during this state, a special software power-down sequence must be used (see Table 7). In power-down state, the interface is still accessible. A prime consideration for low power consumption is the series resistance Rs of the quartz used. The series resistance acts as a loss element. Low Rs will reduce current consumption further. 250 IDD (nA) 210 001aaj165 170 130 90 50 0 20 40 60 80 100 Quartz series resistance, Rs (kΩ) VDD = 3 V. Fig 6. IDD with respect to Rs 9.2 Divider The divider chain is responsible for reducing the 32.768 kHz oscillator frequency down to 1⁄ Hz. 32 The dividers (see Figure 7) divider_2 and divider_3 may be reset with the dvs_cmd instruction. The 24 bit counter may be set when the dividers are held in reset, but this is not a requirement. This allows for accurate setting and restarting of the counter. The interface is asynchronous to the quartz oscillator and the state of divider_1 can not be known when the dvs_cmd is enabled. The 8.192 kHz clock could have just occurred and hence a delay of 1⁄8192 seconds will occur before the next increment of the divider_2, or the 8.192 kHz clock could be just about to occur and immediately increment the divider_2. As a consequence, an uncertainty of between zero and one 8192 Hz clock period (i.e. a time uncertainty of about 0 s to 122 µs) will be present when restarting the counter. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 6 of 34 NXP Semiconductors PCA8802 Smartcard RTC OSCILLATOR STOP DETECTOR power-on reset signal clock for fast mode 32.768 kHz DIVIDER_1 8.192 kHz DIVIDER_2 reset 1 Hz DIVIDER_3 reset clock 1/32 Hz 24-BIT COUNTER dvs_cmd - divider stop command 001aaj168 Divider_1 = dividing by 4. Divider_2 = dividing by 8192. Divider_3 = dividing by 32. Fig 7. Divider chain 9.3 Binary counter A 24 bit binary roll over counter is implemented. The counter is reset at power-on. The counter can be set to any value using the set_cmd instruction. The set_cmd instruction allows partial writing of data. Partial writing of the data parameters will result in partial setting of the counter, e.g. if data transfer is stopped after P1[23:16] (see Table 5) is transmitted, then only bit 23 to bit 16 will be updated. The counter will not increment whilst being set. The counter can be halted by means of stopping the dividers using the dvs_cmd instruction. The counter can be read at any time and the counter value will remain stable during reading. If the counter is due to increment during the read or write cycle, then the request to increment will be held off until after the read has concluded. For this reason it is important to read the counter in bursts, ensuring that an interface STOP condition (see Section 9.5.4) is present between read accesses. Reading for periods of more then 32 seconds at a time will result in loss of counts. interface state counter state 1/32 Hz pulse free increment read frozen free read frozen (1) increment 001aaj206 (1) Increment delayed until after the read has finished. Fig 8. Counter behavior during read access PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 7 of 34 NXP Semiconductors PCA8802 Smartcard RTC 9.4 Pulse generator An interrupt pulse is available at the INT pin. This pulse is generated once every 32 seconds and could be used to wake up a microcontroller to perform a periodic function e.g. to calculate and update an LCD display with a new one-time password. A pulse is generated coincident with the increment of the counter. The new counter value will be available immediately. INT counter 001aaj169 Fig 9. Pulse generator 9.5 I2C-bus interface 9.5.1 Interface protocol The serial interface is based on the I2C-bus protocol. The I2C-bus protocol has the advantage of being robust in terms of immunity to electrical noise. Although the PCA8802 does not have the signal filters inside the interface pins, the slave address and acknowledge hand shaking is nevertheless implemented. For power saving, the SDA output is push-pull instead of the more traditional open-drain output. Push-pull prevents the need for power consuming pull-up resistors, but does limit the operation to point to point only. The following slave addresses plus a write and read bit are reserved for the PCA8802: • write: 1010 0000 • read: 1010 0001 An incorrect slave address will result in the device ignoring all bus data. A STOP or START condition (see Section 9.5.4) will be required before a new transfer can be made. 9.5.1.1 The writing protocol The writing protocol is shown in Figure 10. There is no restriction for the order of sending instructions. As many instructions as needed may be sent in one access. The total duration of one access must not exceed 32 seconds (see Figure 12). PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 8 of 34 NXP Semiconductors PCA8802 Smartcard RTC writing 2 consecutive instructions S wrt_cmd A instruction A instruction A P writing 2 consecutive instructions with instruction parameters S wrt_cmd A instruction A instr. parameter 1 A instr. parameter 2 A instr. parameter 3 A instruction A P S START condition P STOP condition A acknowledge from slave 001aaj213 Wrt_cmd is slave address plus write bit. Fig 10. Writing protocol 9.5.1.2 The reading protocol The reading protocol is shown in Figure 11. reading multiple data parameters S rd_cmd A 1st parameter A 2nd parameter A 3rd parameter A 4th parameter A nth parameter A P S A START condition P STOP condition A A acknowledge from slave not acknowledge from master acknowledge from master 001aaj207 Rd_cmd is slave address plus read bit. Fig 11. Reading protocol 9.5.1.3 Reading and writing limitations As the counter is frozen during interface accesses, all access must be completed within 32 seconds (see Figure 12). If this rule is not adhered to, then counts will be dropped. wrt_cmd/ rd_cmd S A instruction transfer must be < 32 seconds S A P START condition acknowledge from slave STOP condition P 001aaj205 Wrt_cmd is slave address plus write bit. Rd_cmd is slave address plus read bit. Fig 12. Access restrictions PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 9 of 34 NXP Semiconductors PCA8802 Smartcard RTC 9.5.2 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal. Bit transfer is shown in Figure 13. SDA SCL data line stable; data valid change of data allowed mba607 Fig 13. Bit transfer 9.5.3 Bit order Data is transferred MSB first. b7 MSB b6 b5 b4 b3 b2 b1 b0 LSB 001aaj212 Fig 14. Bit transfer 9.5.4 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 15. The data on SDA is sampled with the rising edge of SCL. Data is output to SDA on the falling edge of SCL. SDA SDA SCL S START condition P STOP condition SCL mbc622 Fig 15. Definition of START and STOP conditions 9.5.5 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the device which is controlled by the master is the slave. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 10 of 34 NXP Semiconductors PCA8802 Smartcard RTC 9.5.6 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited, but the duration of the access must not exceed 32 seconds. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement is shown in Figure 16. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement mbc602 1 2 8 9 Fig 16. Acknowledgement on the I2C-bus 9.5.7 Data transfer SDA SCL S START condition 1 to 7 8 9 1 to 7 8 9 1 to 7 8 9 P ADDRESS ACK DATA ACK DATA ACK STOP condition 001aaj201 Fig 17. A complete data transfer PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 11 of 34 NXP Semiconductors PCA8802 Smartcard RTC S SLAVE ADDRESS + write A DATA A DATA A/A P data transferred (n bytes + acknowledge) from master to slave A = acknowledge (SDA LOW) A = not acknowledge (SDA HIGH) S = START condition P = STOP condition 001aaj202 from slave to master Fig 18. A master-transmitter addresses a slave receiver S SLAVE ADDRESS + read A DATA A DATA A P data transferred (n bytes + acknowledge) 001aaj203 Fig 19. A master reads from a slave immediately after the first byte S SLAVE ADDRESS + write or read A DATA A/A Sr n bytes + ack.(1) SLAVE ADDRESS + write or read A DATA A/A n bytes + ack.(1) P Sr = repeated START condition direction of transfer may change at this point 001aaj204 (1) Not shaded because transfer direction of data and acknowledge bits depends on R/W bits. Fig 20. Combined format 9.5.7.1 Example data transfers Example 1: Sending the instruction dvs_cmd followed by fst_cmd is shown in Figure 21. wrt_cmd S 1 0 1 0 0 0 0 0 A 0 0 dvs_cmd enable 0 1 0 0 0 1 A 0 1 fst_cmd enable 0 0 0 0 0 1 A P S START condition P STOP condition A acknowledge from slave 001aaj209 Wrt_cmd is slave address plus write bit. Fig 21. Sending instructions PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 12 of 34 NXP Semiconductors PCA8802 Smartcard RTC Example 2: Sending dvs_cmd followed by setting the counter to A90001h is shown in Figure 22 WRT_CMD S 1 0 1 0 0 0 0 0 A 0 0 DVS_CMD enable 0 1 0 0 0 1 A SET_CMD enable 1 0 0 0 0 0 0 0 A 1 0 bits 23...16 = A9h 1 0 1 0 0 1 A bits 15...8 = 00h 0 0 0 0 0 0 0 0 A 0 0 bits 7...0 = 01h 0 0 0 0 0 1 A P S START condition P STOP condition A acknowledge from slave 001aaj210 Wrt_cmd is slave address plus write bit. Fig 22. Setting the counter Example 3: Reading the counter (counter = 000011h) is shown in Figure 23. RD_CMD S master driving SDA slave driving SDA S START condition P STOP condition A 1 0 1 0 0 0 0 1 A 0 0 bits 23...16 = 00h 0 0 0 0 0 0 A 0 0 bits 15...8 = 00h 0 0 0 0 0 0 A 0 0 bits 7...0 = 11h 0 1 0 0 0 1 A P acknowledge from slave A acknowledge from master A not acknowledge from master 001aaj211 Rd_cmd is slave address plus read bit. Fig 23. Reading the counter PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 13 of 34 NXP Semiconductors PCA8802 Smartcard RTC 9.6 Instructions 9.6.1 Instruction set Table 5. Write instructions The writing protocol is illustrated in Figure 10. First byte wrt_cmd 1010 0000 dvs_cmd pwd_cmd 32k_cmd fst_cmd 0001 0001 0001 0000 0010 0001 0010 0000 0011 0001 0011 0000 0100 0001 0100 0000 set_cmd 1000 0000 P1[23:16] P2[15:8] P3[7:0] Table 6. Read instructions The reading protocol is illustrated in Figure 11. First byte rd_cmd[1] 1010 0001 P1[23:16] P2[15:8] P3[7:0] P4[23:16] : [1] Read of the counter is implicit with an interface read. Second byte Further bytes Action device slave write address: slave address plus write bit stop and reset dividers start dividers shut down the device enable the device enable output of 32.768 kHz on pin INT disable output of 32.768 kHz on pin INT fast mode; increments counter every second fast mode disable set the counter value parameter with counter values Instruction Instruction code Instruction Instruction code Parameters Further bytes Action device slave read address: slave address plus read bit parameter with counter values; continues to read until no ACK is received; counter is not updated during this time Instruction Instruction code Parameters 9.6.2 Instruction wrt_cmd The write instruction (wrt_cmd) precedes each write sequence. Details of the writing protocol can be found in Section 9.5.1.1. 9.6.3 Instruction dvs_cmd The divider switch instruction (dvs_cmd) can be used to freeze the divider chain and to put it in a defined state. The first two bits of the divider chain can not be influenced. With this instruction it is possible to control the time to the next increment of the counter. See Table 8. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 14 of 34 NXP Semiconductors PCA8802 Smartcard RTC When the dividers are restarted, the first increment of the 24 bit counter will be after 32 seconds. 8.192 kHz dvs_cmd disable counter first increment after dvs_cmd disable will be after 32 seconds ±61 µs 32.768 kHz DIVIDER_1 8.192 kHz DIVIDER_2 reset 1 Hz DIVIDER_3 reset clock 1/32 Hz 24 BIT COUNTER dvs_cmd 001aaj170 Divider_1 = dividing by 4. Divider_2 = dividing by 8192. Divider_3 = dividing by 32. Fig 24. Instruction dvs_cmd When the dividers are restarted, the 8192 Hz clock could have just occurred and hence a delay of 1⁄8192 seconds will occur before the next increment of the divider_2, or the 8192 Hz clock could be just about to occur and immediately increment the divider_2. As a consequence, an uncertainty of one half clock period will be present when restarting (see Figure 24). 9.6.4 Instruction pwd_cmd The power down instruction (pwd_cmd) is intended to be used to put the system into a low power mode for storage. Static leakage current will be the only power consumed. Storage at temperatures above room temperature may increase leakage currents. Entering power-down requires a specific sequence of events since under normal circumstances stopping the oscillator would result in a chip reset. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 15 of 34 NXP Semiconductors PCA8802 Smartcard RTC Power-down sequence Code sequence Note START condition 1010 0000 0001 0001 1000 0000 1010 1010 1010 1010 1010 1010 stop the divider set the counter = AAAAAAh P1[23:16] P2[15:8] P3[7:0] stop the oscillator - Table 7. Step Action To enter power-down 1 2 3 4 initiate transfer send wrt_cmd enable dvs_cmd set counter with set_cmd 5 6 7 enable pwd_cmd end transfer device is now in a power-down state initiate transfer send wrt_cmd disable pwd_cmd disable dvs_cmd end transfer 0010 0001 STOP condition - To exit power-down 1 2 3 4 5 START condition 1010 0000 0010 0000 0001 0000 STOP condition oscillator starts on the ACK cycle of this instruction enable the divider again - 9.6.5 Instruction 32k_cmd The 32.768 kHz enable instruction (32k_cmd) is intended to aid with oscillator characterization during system development. With this instruction it is possible to obtain a 32.768 kHz clock on the INT pin which may be used for measurement. This mode does not affect other operation of the chip with the exception of loss of interrupt output. 9.6.6 Instruction fst_cmd The fast mode instruction (fst_cmd) is intended to enable faster system development. When enabled, the counter will increment once every second instead of once every 32 seconds. Interrupt pulses will also be generated once every second. When using fst_cmd, data access to the device must be completed within 1 second, if not then counter increments will be lost. The 1 second period is measured from the ACK cycle of a valid slave address to the next STOP or repeated START. A repeated START will be sufficient to allow the counter to increment. 9.6.7 Instruction set_cmd The counter can be set to any value using the set instruction (set_cmd). Partial writing of the data parameters will result in partial setting of the counter. E.g. if data transfer is stopped after P1[23:16] is transmitted, then only bit 23 to bit 16 will be updated. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 16 of 34 NXP Semiconductors PCA8802 Smartcard RTC This instruction takes only 3 parameters in one command. Data after the 3rd parameter will be interpreted as the next instruction. Accurate setting and start-up can be implemented using the dvs_cmd instruction in cooperation with the set_cmd instruction. An example is shown in Table 8. Table 8. Step 1 2 3 4 Example of accurate setting of the counter Code sequence Note START condition 1010 0000 0001 0001 1000 0000 0000 0000 0000 0000 0000 0001 5 6 7 8 9 10 end transfer wait for an external time marker initiate transfer send wrt_cmd disable dvs_cmd end transfer STOP condition set the counter = 1 P1[23:16] P2[15:8] P3[7:0] - Action initiate transfer send wrt_cmd enable dvs_cmd set counter with set_cmd START condition 1010 0000 0001 0000 STOP condition counter starts on the ACK cycle of this instruction - 9.6.8 Instruction rd_cmd With the read instruction (rd_cmd) the counter value can be read at any time. When the counter value is read, the counter is frozen so that there will be no changes during the read back. After a read is terminated, the counter will be allowed to increment again. Any increment that was scheduled during the frozen period will then be effected. Reading the counter is cyclic i.e. the device will repeatedly return the present counter value until the read is terminated. Reading the counter more than once may be useful in the case that the application is subject to a strong Electromagnetic Interference (EMI) environment so that read back values can be compared. Read back must be terminated within 32 seconds else a count will be dropped. b23 b22 b21 b20 b19 b18 b17 b16 b15 b14 b13 b12 b11 b10 MSB b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 LSB 001aaj208 Fig 25. Read bit order PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 17 of 34 NXP Semiconductors PCA8802 Smartcard RTC 9.7 Reset As described in Section 9.1, the device will be in reset when the oscillator is stopped with the exception of a controlled power-down using the pwd_cmd. The state of the device after reset is shown in Table 9. Table 9. dvs_cmd pwd_cmd 32k_cmd fst_cmd 24 bit counter Reset state State after reset disabled disabled disabled disabled 000000h Instruction name PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 18 of 34 NXP Semiconductors PCA8802 Smartcard RTC 10. Limiting values Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD IDD VI II VO IO Ptot Vesd Ilu Tamb Tstg [1] [2] [3] [4] Conditions Min −0.5 −50 −0.5 −10 −0.5 −10 - Max +6.5 +50 +6.5 +10 +6.5 +10 300 ±2500 ±200 200 +85 +150 Unit V mA V mA V mA mW V V mA °C °C supply voltage supply current input voltage input current output voltage output current total power dissipation electrostatic discharge voltage latch-up current ambient temperature storage temperature Pass level; Human Body Model (HBM) according to JESD22-A114. Pass level; Machine Model (MM), according to JESD22-A115. Pass level; Latch-up testing, according to JESD78. [4] HBM MM [1] [2] [3] −40 −65 According to the NXP store and transport conditions (document SNW-SQ-623) the devices have to be stored at a temperature of +5 °C to +45 °C and a humidity of 25 % to 75 %. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 19 of 34 NXP Semiconductors PCA8802 Smartcard RTC 11. Static characteristics Table 11. Static characteristics VDD = 1.6 V to 5.5 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = −40 °C to +85 °C; quartz crystal: Rs = 30 kΩ, CL = 6.0 pF; unless otherwise specified. Symbol Supplies VDD supply voltage Tamb = 25 °C; fSCL = 0 Hz ∆VDD IDD supply voltage variation supply current ∆V/∆t = 1 V/µs power-down active Tamb = 25 °C; VDD = 3 V; fSCL = 0 Hz device running fSCL = 0 Hz Tamb = 25 °C; VDD = 3 V; fSCL = 0 Hz interface active fSCL = 100 kHz fSCL = 1 MHz Oscillator Vstart tstartup CL(itg) Inputs VIL VIH VI ILI Outputs VO IOH output voltage HIGH-level output current VOH = 4.0 V; VDD = 5 V; on pins INT and SDA VOH = 1.28 V; VDD = 1.6 V; on pins INT and SDA −0.5 5 VDD+0.5 2 V mA LOW-level input voltage HIGH-level input voltage input voltage input leakage current on pins SCL, OSCI, TEST on pin SDA VI = VDD or VSS; on pins SCL, SDA and TEST 0.7VDD −0.5 −0.5 −200 0 0.3VDD 5.5 +200 V V V nA start voltage start-up time integrated load capacitance [2] [1] Parameter Conditions Min 1.6 - Typ 1.0 0.25 3 Max 5.5 - Unit V V V nA - 130 400 - nA nA - 5 50 1.1 0.2 6.0 20 100 - µA µA V s pF VDD + 0.5 V - 0.5 0.2 mA PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 20 of 34 NXP Semiconductors PCA8802 Smartcard RTC Table 11. Static characteristics …continued VDD = 1.6 V to 5.5 V; VSS = 0 V; fosc = 32.768 kHz; Tamb = −40 °C to +85 °C; quartz crystal: Rs = 30 kΩ, CL = 6.0 pF; unless otherwise specified. Symbol IOL Parameter LOW-level output current Conditions VOL = 1.0 V; VDD = 5 V; on pins INT and SDA VOL = 0.32 V; VDD = 1.6 V; on pins INT and SDA ILO output leakage current VO = VDD or VSS; on pins SDA and INT Min −2 Typ −7 Max Unit mA −0.4 −1 - mA −200 0 +200 nA [1] [2] Unless otherwise defined, IDD is measured with the reset state, see Section 9.7. Integrated load capacitance, CL(itg), is a calculation of COSCI and COSCO in series: C L ( itg ) = -------------------------------------------- . ( C OSCI ⋅ C OSCO ) ( C OSCI + C OSCO ) 12. Dynamic characteristics Table 12. Dynamic characteristics VDD = 1.6 V to 5.5 V; VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. [1] Symbol fSCL tLOW tHIGH tBUF tHD;STA tSU;STA tr tf tSU;DAT tHD;DAT tSU;STO tVD;DAT Cb tw(int) [1] [2] Parameter SCL clock frequency LOW period of the SCL clock HIGH period of the SCL clock bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition rise time of both SDA and SCL signals fall time of both SDA and SCL signals data set-up time data hold time set-up time for STOP condition data valid time capacitive load for each bus line interrupt pulse width Conditions Min 500 260 500 260 260 [2] [2] Typ 10 10 40 Max 1 450 50 80 Unit MHz ns ns ns ns ns ns ns ns ns ns ns pF µs Timing characteristics: serial bus 50 0 260 75 20 Timing characteristics: INT All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. Rise and fall times are not limited. Fast edges may lead to system EMI problems, whilst slow edges are susceptible to noise. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 21 of 34 NXP Semiconductors PCA8802 Smartcard RTC tSU;STA tLOW tHIGH 1 / fSCL SCL tBUF tr tf SDA tHD;STA tSU;DAT tHD;DAT tVD;DAT tSU;STO 001aaj217 Fig 26. Serial bus timing waveforms INT tw(int) 001aaj259 Fig 27. INT timing PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 22 of 34 NXP Semiconductors PCA8802 Smartcard RTC 13. Bare die information 13.1 Locations Table 13. Symbol INT VDD TEST OSCO OSCI VSS[2] SCL SDA pin 1 identifier top right die corner[3] [1] [2] [3] Bump and reference point locations Pad 1 2 3 4 5 6 7 8 Coordinates[1] x 437 −12 −460 −460 −460 −12 437 437 474.7 −594.8 594.7 y −396 −430 −396 1 396 430 396 1 −472.0 −568.2 568.3 bottom left die corner[3] - All coordinates are referenced, in µm, to the center of the die (see Figure 30 and Figure 31). The substrate (rear side of the die) is wired to VSS but should not be electrically connected. Die size before dicing. Final dimensions will be 10 µm to 20 µm smaller. REF 001aaj154 Pin 1 is identified by this symbol. Fig 28. Pin 1 identifier 13.2 PCB or foil landing site The layout of the landing sites is important. It is recommended to follow the following guidelines 1. All landing sites should be the same size. When one site has a different size or shape, e.g. to indicate pad one, then the pull on the die produced by the surface tension of the solder will be different in one place. This variation can lead to the die not laying flat on the Printed-Circuit Board (PCB) or foil. This can also result in weak solder joints for some pins. 2. It is recommended to use circular landing sites of the same diameter as the solder ball. This will help with self alignment. Solder bump dimensions may be found in Figure 30. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 23 of 34 NXP Semiconductors PCA8802 Smartcard RTC 3. If no solder resist is used on the PCB or foil, then consideration should be given to the amount of run-off of the solder along the track connected to the landing site. Uneven run-off may result in similar problems as described in 1. 001aaj171 Fig 29. Example of PCB or foil landing sites PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 24 of 34 NXP Semiconductors PCA8802 Smartcard RTC 14. Bare die outline WLCSP8: wafer level chip-size package; 8 bumps; 1.19 x 1.14 x 0.29 mm D b 7 PCA8802CX 5 6 e 4 (1) x 0 0 y A2 E A A1 8 e 3 e1 Dimensions Unit mm max nom min A A1 2 e1 1 X detail X A2 0.2 b D E e 0.4 e1 0.45 0 0.5 scale pca8802cx_po 0.105 0.29 0.090 0.075 0.136 0.109 1.19 1.14 0.082 1 mm Note 1. Marking code: PC8802-1. Outline version PCA8802CX References IEC JEDEC JEITA European projection Issue date 08-11-28 Fig 30. Bare die outline PCA8802CX PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 25 of 34 NXP Semiconductors PCA8802 Smartcard RTC WLCSP8: wafer level chip-size package; 8 bumps; 1.19 x 1.14 x 0.22 mm A 5 D 6 7 A1 P1 P2 e 4 (1) PCA8802U x 0 0 y 8 e E P4 P3 X Dimensions Unit mm A A1 detail X 3 e1 D E 2 e2 e e1 e2 P1(2) P2(3) P3(2) P4(3) 1 max 0.018 0.093 0.093 nom 0.215 0.015 1.19 1.14 0.396 0.448 0.449 0.099 0.090 0.099 0.090 min 0.012 0.087 0.087 0 0.5 scale pca8802u_po Notes 1. Marking code: PC8802-1. 2. P1 and P3: pad size. 3. P2 and P4: bump size. Outline version PCA8802U References IEC JEDEC JEITA 1 mm European projection Issue date 08-11-28 Fig 31. Bare die outline PCA8802U PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 26 of 34 NXP Semiconductors PCA8802 Smartcard RTC 15. Packing information 15.1 Tray information A G H 1,1 1,2 1,3 2,1 3,1 2,2 x,1 x C y D B F 1,y x,y A E M A J SECTION A-A mgu653 Fig 32. Tray details for PCA8802U Table 14. A B C D E F G H J M x y [1] Tray dimensions [1] Description pocket pitch; x direction pocket pitch; y direction pocket width; x direction pocket width; y direction tray width; x direction tray width; y direction distance from cut corner to pocket (1,1) center distance from cut corner to pocket (1,1) center tray thickness pocket depth number of pockets in x direction number of pockets in y direction Value 3.1 mm 3.1 mm 1.29 mm 1.24 mm 50.8 mm 50.8 mm 5.25 mm 5.25 mm 3.96 mm 0.5 mm 14 14 Dimension Die is placed in pocket bump side up. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 27 of 34 NXP Semiconductors PCA8802 Smartcard RTC The orientation of the IC in a pocket is indicated by the position of the IC type name on the surface of the die, with respect to the cut corner on the upper left of the tray. Fig 33. Tray alignment 15.2 Tape and reel 4 mm W B0 P1 direction of feed Fig 34. Tape and reel details for PCA8802CX Table 15. W A0 B0 K0 P1 [1] Tape and reel dimensions [1] Description tape width pocked length pocket width pocket depth pocket pitch Value 8.0 mm 1.3 mm 1.3 mm 0.5 mm 4.0 mm Dimension Die is placed in pocket bump side down. The orientation of the IC in a pocket is indicated by the position of pin 1, with respect to the sprocket holes. Fig 35. Pocket alignment for PCA8802CX PCA8802_1 Product data sheet Rev. 01 — 19 February 2009 PC8802 001aaj258 A0 K0 001aai040 pin 1 001aaj153 © NXP B.V. 2009. All rights reserved. 28 of 34 NXP Semiconductors PCA8802 Smartcard RTC 16. Soldering of WLCSP packages 16.1 Introduction to soldering WLCSP packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering WLCSP (Wafer Level Chip-Size Packages) can be found in application note AN10439 “Wafer Level Chip Scale Package” and in application note AN10365 “Surface mount reflow soldering description”. Wave soldering is not suitable for this package. All NXP WLCSP packages are lead-free. 16.2 Board mounting Board mounting of a WLCSP requires several steps: 1. Solder paste printing on the PCB 2. Component placement with a pick and place machine 3. The reflow soldering itself 16.3 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 36) than a PbSn process, thus reducing the process window • Solder paste printing issues, such as smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature), and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic) while being low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16. Table 16. Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 36. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 29 of 34 NXP Semiconductors PCA8802 Smartcard RTC temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 36. Temperature profiles for large and small components For further information on temperature profiles, refer to application note AN10365 “Surface mount reflow soldering description”. 16.3.1 Stand off The stand off between the substrate and the chip is determined by: • The amount of printed solder on the substrate • The size of the solder land on the substrate • The bump height on the chip The higher the stand off, the better the stresses are released due to TEC (Thermal Expansion Coefficient) differences between substrate and chip. 16.3.2 Quality of solder joint A flip-chip joint is considered to be a good joint when the entire solder land has been wetted by the solder from the bump. The surface of the joint should be smooth and the shape symmetrical. The soldered joints on a chip should be uniform. Voids in the bumps after reflow can occur during the reflow process in bumps with high ratio of bump diameter to bump height, i.e. low bumps with large diameter. No failures have been found to be related to these voids. Solder joint inspection after reflow can be done with X-ray to monitor defects such as bridging, open circuits and voids. 16.3.3 Rework In general, rework is not recommended. By rework we mean the process of removing the chip from the substrate and replacing it with a new chip. If a chip is removed from the substrate, most solder balls of the chip will be damaged. In that case it is recommended not to re-use the chip again. PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 30 of 34 NXP Semiconductors PCA8802 Smartcard RTC Device removal can be done when the substrate is heated until it is certain that all solder joints are molten. The chip can then be carefully removed from the substrate without damaging the tracks and solder lands on the substrate. Removing the device must be done using plastic tweezers, because metal tweezers can damage the silicon. The surface of the substrate should be carefully cleaned and all solder and flux residues and/or underfill removed. When a new chip is placed on the substrate, use the flux process instead of solder on the solder lands. Apply flux on the bumps at the chip side as well as on the solder pads on the substrate. Place and align the new chip while viewing with a microscope. To reflow the solder, use the solder profile shown in application note AN10365 “Surface mount reflow soldering description”. 16.3.4 Cleaning Cleaning can be done after reflow soldering. 17. Abbreviations Table 17. Acronym CMOS EMI HBM IC LCD LSB MM MSB PCB RTC WLCSP Abbreviations Description Complementary Metal Oxide Semiconductor ElectroMagnetic Interference Human Body Model Integrated Circuit Liquid Crystal Display Least Significant Bit Machine Model Most Significant Bit Printed-Circuit Board Real Time Clock Wafer Level Chip-Size Package PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 31 of 34 NXP Semiconductors PCA8802 Smartcard RTC 18. Revision history Table 18. Revision history Release date 20090219 Data sheet status Change notice Product data sheet Supersedes Document ID PCA8802_1 PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 32 of 34 NXP Semiconductors PCA8802 Smartcard RTC 19. Legal information 19.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Bare die — All die are tested on compliance with their related technical specifications as stated in this data sheet up to the point of wafer sawing and are handled in accordance with the NXP Semiconductors storage and transportation conditions. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post-packing tests performed on individual die or wafers. NXP Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, NXP Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. All die sales are conditioned upon and subject to the customer entering into a written die sale agreement with NXP Semiconductors through its legal department. 19.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA8802_1 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 01 — 19 February 2009 33 of 34 NXP Semiconductors PCA8802 Smartcard RTC 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 9 9.1 9.1.1 9.1.2 9.2 9.3 9.4 9.5 9.5.1 9.5.1.1 9.5.1.2 9.5.1.3 9.5.2 9.5.3 9.5.4 9.5.5 9.5.6 9.5.7 9.5.7.1 9.6 9.6.1 9.6.2 9.6.3 9.6.4 9.6.5 9.6.6 9.6.7 9.6.8 9.7 10 11 12 13 13.1 13.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Device protection diagram . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Power-on. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Low power operation. . . . . . . . . . . . . . . . . . . . . 6 Divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Binary counter . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pulse generator . . . . . . . . . . . . . . . . . . . . . . . . 8 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . 8 Interface protocol . . . . . . . . . . . . . . . . . . . . . . . 8 The writing protocol . . . . . . . . . . . . . . . . . . . . . 8 The reading protocol. . . . . . . . . . . . . . . . . . . . . 9 Reading and writing limitations . . . . . . . . . . . . . 9 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bit order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 START and STOP conditions . . . . . . . . . . . . . 10 System configuration . . . . . . . . . . . . . . . . . . . 10 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Example data transfers . . . . . . . . . . . . . . . . . . 12 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . 14 Instruction wrt_cmd . . . . . . . . . . . . . . . . . . . . 14 Instruction dvs_cmd . . . . . . . . . . . . . . . . . . . . 14 Instruction pwd_cmd. . . . . . . . . . . . . . . . . . . . 15 Instruction 32k_cmd . . . . . . . . . . . . . . . . . . . . 16 Instruction fst_cmd . . . . . . . . . . . . . . . . . . . . . 16 Instruction set_cmd . . . . . . . . . . . . . . . . . . . . 16 Instruction rd_cmd . . . . . . . . . . . . . . . . . . . . . 17 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 Static characteristics. . . . . . . . . . . . . . . . . . . . 20 Dynamic characteristics . . . . . . . . . . . . . . . . . 21 Bare die information . . . . . . . . . . . . . . . . . . . . 23 Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 PCB or foil landing site . . . . . . . . . . . . . . . . . . 23 14 15 15.1 15.2 16 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . Packing information . . . . . . . . . . . . . . . . . . . . Tray information . . . . . . . . . . . . . . . . . . . . . . . Tape and reel . . . . . . . . . . . . . . . . . . . . . . . . . Soldering of WLCSP packages . . . . . . . . . . . Introduction to soldering WLCSP packages. . Board mounting . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Stand off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quality of solder joint . . . . . . . . . . . . . . . . . . . Rework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cleaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 27 27 28 29 29 29 29 30 30 30 31 31 32 33 33 33 33 33 33 34 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 February 2009 Document identifier: PCA8802_1