PCA9512ADP

PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer Rev. 04 — 19 August 2009 Product data sheet 1. General description The PCA9512A is a hot swappable I2C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512A provides bidirectional buffering, keeping the backplane and card capacitances isolated. The PCA9512A rise time accelerator circuitry allows the use of weaker DC pull-up currents while still meeting rise time requirements. The PCA9512A incorporates a digital input pin that enables and disables the rise time accelerators on all four SDAn and SCLn pins. During insertion, the PCA9512A SDAn and SCLn pins are precharged to 1 V to minimize the current required to charge the parasitic capacitance of the chip. The dynamic offset design of the PCA9510A/11A/12A/13A/14A I/O drivers allow them to be connected to another PCA9510A/11A/12A/13A/14A device in series or in parallel and to the A side of the PCA9517. The PCA9510A/11A/12A/13A/14A cannot connect to the static offset I/Os used on the PCA9515/15A/16/16A/18, PCA9517 B side, or P82B96 Sx/y side. 2. Features I Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems I Compatible with I2C-bus Standard mode, I2C-bus Fast mode, and SMBus standards I Built-in ∆V/∆t rise time accelerators on all SDA and SCL lines (0.6 V threshold) with ability to disable ∆V/∆t rise time accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2) to be the same I 5 V to 3.3 V level translation with optimum noise margin I High-impedance SDAn and SCLn pins for VCC or VCC2 = 0 V I 1 V precharge on all SDAn and SCLn pins I Supports clock stretching and multiple master arbitration and synchronization I Operating power supply voltage range: 2.7 V to 5.5 V I 0 Hz to 400 kHz clock frequency NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO8, TSSOP8 (MSOP8) 3. Applications I cPCI, VME, AdvancedTCA cards and other multipoint backplane cards that are required to be inserted or removed from an operating system 4. Feature selection Table 1. Feature Idle detect High-impedance SDAn, SCLn pins for VCC = 0 V Rise time accelerator circuitry on SDAn and SCLn pins Rise time accelerator circuitry hardware disable pin for lightly loaded systems Rise time accelerator threshold 0.8 V versus 0.6 V improves noise margin Ready open-drain output Feature selection chart PCA9510A PCA9511A PCA9512A PCA9513A PCA9514A yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes yes - Two VCC pins to support 5 V to 3.3 V level translation with improved noise margins 1 V precharge on all SDAn and SCLn pins 92 µA current source on SCLIN and SDAIN for PICMG applications in only - 5. Ordering information Table 2. Ordering information Tamb = −40 °C to +85 °C Type number PCA9512AD PCA9512ADP [1] Topside mark PA9512A 9512A Package Name SO8 TSSOP8[1] Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 Also known as MSOP8. Standard packing quantities and other packaging data are available at the NXP web site. PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 2 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 6. Block diagram PCA9512A VCC 2 mA 2 mA VCC2 ACC SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT 100 kΩ RCH1 SLEW RATE DETECTOR SDAOUT CONNECT 100 kΩ RCH3 SDAIN CONNECT 1 VOLT PRECHARGE 100 kΩ RCH2 2 mA 100 kΩ RCH4 2 mA ACC SLEW RATE DETECTOR BACKPLANE-TO-CARD CONNECTION CONNECT SLEW RATE DETECTOR ACC SCLIN SCLOUT CONNECT 0.5 µA STOP BIT AND BUS IDLE 0.55VCC/ 0.45VCC 20 pF 0.55VCC/ 0.45VCC UVLO 100 µs DELAY CONNECT UVLO CONNECT RD S GND QB 0.5 pF 002aab788 Fig 1. Block diagram of PCA9512A PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 3 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 7. Pinning information 7.1 Pinning VCC2 SCLOUT SCLIN GND 1 2 8 7 VCC SDAOUT SDAIN ACC VCC2 SCLOUT SCLIN GND 1 2 3 4 002aab790 8 7 VCC SDAOUT SDAIN ACC PCA9512AD 3 4 002aab789 6 5 PCA9512ADP 6 5 Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 7.2 Pin description Table 3. Symbol VCC2 SCLOUT SCLIN GND ACC Pin description Pin 1 2 3 4 5 Description Supply voltage for devices on the card I2C-bus. Connect pull-up resistors from SDAOUT and SCLOUT to this pin. serial clock output to and from the SCL bus on the card serial clock input to and from the SCL bus on the backplane ground supply; connect this pin to a ground plane for best results. CMOS threshold digital input pin that enables and disables the rise time accelerators on all four SDAn and SCLn pins. ACC enables all accelerators when set to VCC2, and turns them off when set to GND. serial data input to and from the SDA bus on the backplane serial data output to and from the SDA bus on the card supply voltage; from the backplane, connect pull-up resistors from SDAIN and SCLIN to this pin. SDAIN SDAOUT VCC 6 7 8 8. Functional description Refer to Figure 1 “Block diagram of PCA9512A”. 8.1 Start-up When the PCA9512A is powered up, either VCC or VCC2 may rise first and either may be more positive or they may be equal, however the PCA9512A will not leave the undervoltage lock out or initialization state until both VCC and VCC2 have gone above 2.5 V. If either VCC or VCC2 drops below 2.0 V it will return to the undervoltage lock out state. In the undervoltage lock out state the connection circuitry is disabled, the rise time accelerators are disabled, and the precharge circuitry is also disabled. After both VCC and VCC2 are valid, independent of which is higher, the PCA9512A enters the initialization state; during this state the 1 V precharge circuitry is activated and pulls up the SDAn and SCLn pins to 1 V through individual 100 kΩ nominal resistors. At the end of the initialization state the ‘Stop bit and bus idle’ detect circuit is enabled. When all the SDAn and SCLn pins have been HIGH for the bus idle time or when all pins are HIGH and a PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 4 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer STOP condition is seen on the SDAIN and SCLIN pins, the connect circuitry is activated, connecting SDAIN to SDAOUT and SCLIN to SCLOUT. The 1 V precharge circuitry is disabled when the connection is made, unless the ACC pin is LOW; the rise time accelerators are enabled at this time also. 8.2 Connect circuitry Once the connection circuitry is activated, the behavior of SDAIN and SDAOUT as well as SCLIN and SCLOUT become identical, with each acting as a bidirectional buffer that isolates the input bus capacitance from the output bus capacitance while communicating. If VCC ≠ VCC2, then a level shifting function is performed between input and output. A LOW forced on either SDAIN or SDAOUT will cause the other pin to be driven to a LOW by the PCA9512A. The same is also true for the SCLn pins. Noise between 0.7VCC and VCC on the SDAIN and SCLIN pins, and 0.7VCC2 and VCC2 on the SDAOUT and SCLOUT pins is generally ignored because a falling edge is only recognized when it falls below 0.7VCC for SDAIN and SCLIN (or 0.7VCC2 for SDAOUT and SCLOUT pins) with a slew rate of at least 1.25 V/µs. When a falling edge is seen on one pin, the other pin in the pair turns on a pull-down driver that is referenced to a small voltage above the falling pin. The driver will pull the pin down at a slew rate determined by the driver and the load. The first falling pin may have a fast or slow slew rate; if it is faster than the pull-down slew rate, then the initial pull-down rate will continue until it is LOW. If the first falling pin has a slow slew rate, then the second pin will be pulled down at its initial slew rate only until it is just above the first pin voltage then they will both continue down at the slew rate of the first. Once both sides are LOW they will remain LOW until all the external drivers have stopped driving LOWs. If both sides are being driven LOW to the same (or nearly the same) value by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving, that pin will rise and rise above the nominal offset voltage until the internal driver catches up and pulls it back down to the offset voltage. This bounce is worst for low capacitances and low resistances, and may become excessive. When the last external driver stops driving a LOW, that pin will bounce up and settle out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the RC time constant. As long as the slew rate is at least 1.25 V/µs, when the pin voltage exceeds 0.6 V, the rise time accelerator circuits are turned on and the pull-down driver is turned off. If the ACC pin is LOW, the rise time accelerator circuits will be disabled, but the pull-down driver will still turn off. 8.3 Maximum number of devices in series Each buffer adds about 0.1 V dynamic level offset at 25 °C with the offset larger at higher temperatures. Maximum offset (Voffset) is 0.150 V with a 10 kΩ pull-up resistor. The LOW level at the signal origination end (master) is dependent upon the load and the only specification point is the I2C-bus specification of 3 mA will produce VOL < 0.4 V, although if lightly loaded the VOL may be ~0.1 V. Assuming VOL = 0.1 V and Voffset = 0.1 V, the level after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the rising edge accelerator (about 0.6 V). With great care a system with four buffers may work, but as the VOL moves up from 0.1 V, noise or bounces on the line will result in firing the rising edge accelerator thus introducing false clock edges. Generally it is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset. PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 5 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off. If the VIL is above ~0.6 V and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected. buffer A MASTER common node buffer B SLAVE B buffer C SLAVE C 002aab581 Fig 4. System with 3 buffers connected to common node Consider a system with three buffers connected to a common node and communication between the Master and Slave B that are connected at either end of buffer A and buffer B in series as shown in Figure 4. Consider if the VOL at the input of buffer A is 0.3 V and the VOL of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to Slave B and then from Slave B to Master. Before the direction change you would observe VIL at the input of buffer A of 0.3 V and its output, the common node, is ~0.4 V. The output of buffer B and buffer C would be ~0.5 V, but Slave B is driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of buffer C is ~0.5 V. When the Master pull-down turns off, the input of buffer A rises and so does its output, the common node, because it is the only part driving the node. The common node will rise to 0.5 V before buffer B’s output turns on, if the pull-up is strong the node may bounce. If the bounce goes above the threshold for the rising edge accelerator ~0.6 V the accelerators on both buffer A and buffer C will fire contending with the output of buffer B. The node on the input of buffer A will go HIGH as will the input node of buffer C. After the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to ~0.5 V because the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to ~0.6 V until Slave B turned off. This would not cause a failure on the data line as long as the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occurred before the data setup time. If this were the SCL line, the parts on buffer A and buffer C would see a false clock rather than a stretched clock, which would cause a system error. 8.4 Propagation delays The delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. If the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. The tPLH may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. The tPHL can never be negative because the output does not start to fall until the input is below 0.7VCC (or 0.7VCC2 for SDAOUT and SCLOUT), and the output turn on has a non-zero delay, and the output has a limited maximum slew rate, and even if the input slew PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 6 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. The maximum tPHL occurs when the input is driven LOW with zero delay and the output is still limited by its turn-on delay and the falling edge slew rate. The output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature, VCC or VCC2 and process, as well as the load current and the load capacitance. 8.5 Rise time accelerators During positive bus transactions, a 2 mA current source is switched on to quickly slew the SDA and SCL lines HIGH once the input level of 0.6 V for the PCA9512A is exceeded. The rising edge rate should be at least 1.25 V/µs to guarantee turn on of the accelerators. The built-in ∆V/∆t rise time accelerators on all SDA and SCL lines requires the bus pull-up voltage and respective supply voltage (VCC or VCC2) to be the same. The built-in ∆V/∆t rise time accelerators can be disabled through the ACC pin for lightly loaded systems. 8.6 ACC boost current enable Users having lightly loaded systems may wish to disable the rise time accelerators. Driving this pin to ground turns off the rise time accelerators on all four SDAn and SCLn pins. Driving this pin to the VCC2 voltage enables normal operation of the rise time accelerators. 8.7 Resistor pull-up value selection The system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 V/µs on the SDAn and SCLn pins, in order to activate the boost pull-up currents during rising edges. Choose maximum resistor value using the formula given in Equation 1: 3 V CC ( min ) – 0.6 R PU ≤ 800 × 10  ----------------------------------  -  C (1) where RPU is the pull-up resistor value in Ω, VCC(min) is the minimum VCC voltage in volts, and C is the equivalent bus capacitance in picofarads. In addition, regardless of the bus capacitance, always choose RPU ≤ 65.7 kΩ for VCC = 5.5 V maximum, RPU ≤ 45 kΩ for VCC = 3.6 V maximum. The start-up circuitry requires logic HIGH voltages on SDAOUT and SCLOUT to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. See the curves in Figure 5 and Figure 6 for guidance in resistor pull-up selection. PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 7 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 50 RPU (kΩ) 40 (1) 002aae782 Rmax = 45 kΩ 30 rise time = 300 ns(2) 20 rise time = 20 ns 10 Rmin = 1 kΩ 0 0 100 200 300 Cb (pF) 400 (1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with rise time accelerator turned on. (2) Rise time accelerator off. Fig 5. Bus requirements for 3.3 V systems 002aae783 70 RPU (kΩ) 60 50 (1) Rmax = 65.7 kΩ 40 rise time = 300 ns(2) 30 20 rise time = 20 ns 10 0 0 100 200 300 Cb (pF) 400 Rmin = 1.7 kΩ (1) Unshaded area indicates recommended pull-up, for rise time < 300 ns, with rise time accelerator turned on. (2) Rise time accelerator off. Fig 6. Bus requirements for 5 V systems PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 8 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 8.8 Hot swapping and capacitance buffering application Figure 7 through Figure 9 illustrate the usage of the PCA9512A in applications that take advantage of both its hot swapping and capacitance buffering features. In all of these applications, note that if the I/O cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise time and fall time requirements difficult to meet. Placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. For a given I/O card, the PCA9512A drives the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pF, the connector, trace, and all additional cards on the backplane. See Application Note AN10160, ‘Hot Swap Bus Buffer’ for more information on applications and technical assistance. BACKPLANE CONNECTOR BACKPLANE VCC2 BD_SEL VCC SDA SCL STAGGERED CONNECTOR POWER SUPPLY HOT SWAP I/O PERIPHERAL CARD 1 C1 0.01 µF R4 10 kΩ R5 10 kΩ R6 10 kΩ R3 5.1 Ω PCA9512A VCC SDAIN SCLIN VCC2 SDAOUT SCLOUT ACC CARD1_SDA CARD1_SCL C2 0.01 µF GND R1 10 kΩ R2 10 kΩ I/O PERIPHERAL CARD 2 STAGGERED CONNECTOR POWER SUPPLY HOT SWAP C3 0.01 µF R8 10 kΩ R9 10 kΩ R10 10 kΩ R7 5.1 Ω PCA9512A VCC SDAIN SCLIN VCC2 SDAOUT SCLOUT ACC CARD2_SDA CARD2_SCL C4 0.01 µF GND I/O PERIPHERAL CARD N STAGGERED CONNECTOR POWER SUPPLY HOT SWAP C5 0.01 µF R12 10 kΩ R13 10 kΩ R14 10 kΩ R11 5.1 Ω PCA9512A VCC SDAIN SCLIN VCC2 SDAOUT SCLOUT ACC CARDN_SDA CARDN_SCL C6 0.01 µF GND 002aab791 Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure 5 and Figure 6. Fig 7. Hot swapping multiple I/O cards into a backplane using the PCA9512A in a cPCI, VME, and AdvancedTCA system PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 9 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer BACKPLANE CONNECTOR BACKPLANE VCC2 STAGGERED CONNECTOR I/O PERIPHERAL CARD 1 C1 0.01 µF R3 5.1 Ω R4 10 kΩ R5 10 kΩ R6 10 kΩ PCA9512A VCC SDAIN SCLIN VCC2 SDAOUT SCLOUT ACC CARD1_SDA CARD1_SCL VCC SDA SCL C2 0.01 µF GND R1 10 kΩ R2 10 kΩ I/O PERIPHERAL CARD 2 STAGGERED CONNECTOR C3 0.01 µF R7 5.1 Ω R8 10 kΩ R9 10 kΩ R10 10 kΩ PCA9512A VCC SDAIN SCLIN VCC2 SDAOUT SCLOUT ACC CARD2_SDA CARD2_SCL C4 0.01 µF GND 002aab792 Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure 5 and Figure 6. Fig 8. Hot swapping multiple I/O cards into a backplane using the PCA9512A with a custom connector VCC (5 V) R1 10 kΩ R4 10 kΩ CARD_VCC (3 V) C2 0.01 µF C1 0.01 µF R3 10 kΩ R2 10 kΩ VCC SDA SCL SDAIN SCLIN VCC2 SDAOUT CARD_SDA CARD_SCL PCA9512A SCLOUT GND ACC 002aab793 Remark: Application assumes bus capacitance within ‘proper operation’ region of Figure 5 and Figure 6. Fig 9. 5 V to 3.3 V level translator and bus buffer PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 10 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 9. Application design-in information VCC (5 V) CARD_VCC (3 V) R1 10 kΩ R2 10 kΩ C2 0.01 µF C1 0.01 µF R3 10 kΩ R4 10 kΩ R5 10 kΩ VCC SDA SDAIN VCC2 SDAOUT CARD_SDA SCL SCLIN SCLOUT CARD_SCL PCA9512A ACC GND 002aab794 Fig 10. Typical application 10. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VCC2 Vn II II/O Toper Tstg Tsp Tj(max) [1] [2] [3] Parameter supply voltage supply voltage input current input/output current operating temperature storage temperature solder point temperature maximum junction temperature 2[1] voltage on any other pin Conditions Min −0.5 −0.5 −0.5 [2] [3] Max +7 +7 +7 ±20 ±50 +85 +125 300 125 Unit V V V mA mA °C °C °C °C −40 −65 10 s maximum - Card side supply voltage. Maximum current for inputs. Maximum current for I/O pins. PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 11 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 11. Characteristics Table 5. Characteristics VCC = 2.7 V to 5.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Power supply VCC VCC2 ICC ICC2 supply voltage supply voltage 2[2] supply current supply current 2 VCC = 5.5 V; VSDAIN = VSCLIN = 0 V VCC = 5.5 V; VSDAOUT = VSCLOUT = 0 V SDA, SCL floating on power-up [1] [3] [1][4] [1] [1] Parameter Conditions Min 2.7 2.7 - Typ 1.8 1.7 Max 5.5 5.5 3.6 2.9 Unit V V mA mA Start-up circuitry Vpch ten tidle Itrt(pu) precharge voltage enable time idle time transient boosted pull-up current positive transition on SDA, SCL; VACC = 0.7 × VCC2; VCC = 2.7 V; slew rate = 1.25 V/µs 0.8 50 1 1.1 180 140 2 1.2 250 V µs µs mA Rise time accelerators [5][6] Vth(dis)(ACC) Vth(en)(ACC) II(ACC) disable threshold voltage on pin ACC enable threshold voltage on pin ACC input current on pin ACC 0.3VCC2 −1 - 0.5VCC2 - V 0.5VCC2 0.7VCC2 V ±0.1 5 +1 µA ns tPD(on/off)(ACC) on/off propagation delay on pin ACC Input-output connection Voffset offset voltage 10 kΩ to VCC on SDA, SCL; VCC = 3.3 V; VCC2 = 3.3 V; VI = 0.2 V digital; guaranteed by design, not subject to test VI = 0 V; SDAn, SCLn pins; Isink = 3 mA; VCC = 2.7 V; VCC2 = 2.7 V SDAn, SCLn pins; VCC = 5.5 V; VCC2 = 5.5 V [1] [1][7] 0 115 175 mV Ci VOL input capacitance LOW-level output voltage 0 0.3 10 0.4 pF V ILI input leakage current −1 - +1 µA PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 12 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer Table 5. Characteristics …continued VCC = 2.7 V to 5.5 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol fSCL tBUF tHD;STA tSU;STA tSU;STO tHD;DAT tSU;DAT tLOW tHIGH tf tr Parameter SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals This specification applies over the full operating temperature range. Card side supply voltage. The enable time is from power-up of VCC and VCC2 ≥ 2.7 V to when idle or stop time begins. Idle time is from when SDAn and SCLn are HIGH after enable time has been met. Itrt(pu) varies with temperature and VCC voltage, as shown in Section 11.1 “Typical performance characteristics”. Input pull-up voltage should not exceed power supply voltage in operating mode because the rise time accelerator will clamp the voltage to the positive supply rail. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the pull-up resistor and VCC voltage is shown in Section 11.1 “Typical performance characteristics”. Guaranteed by design, not production tested. Cb = total capacitance of one bus line in pF. Conditions [8] [8] Min 0 1.3 0.6 0.6 0.6 300 100 1.3 0.6 Typ - Max 400 300 300 Unit kHz µs µs µs µs ns ns µs µs ns ns System characteristics [8] [8] [8] [8] [8] [8] [8] [8][9] 20 + 0.1 × Cb 20 + 0.1 × Cb - [8][9] [1] [2] [3] [4] [5] [6] [7] [8] [9] PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 13 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 11.1 Typical performance characteristics 2.15 ICC (mA) 1.95 002aab795 12 Itrt(pu) (mA) 8 002aab796 VCC = 5.5 V 3.3 V 2.7 V VCC = 5 V 1.75 4 1.55 3.3 V 2.7 V 1.35 −40 +25 Tamb (°C) +90 0 −40 +25 Tamb (°C) +90 ICC2 (pin 1) typical current averages 0.1 mA less than ICC on pin 8. Fig 11. ICC versus temperature 90 VCC = 5.5 V tPHL (ns) 80 002aab589 Fig 12. Itrt(pu) versus temperature 350 V O − VI (mV) 250 002aab591 2.7 V 3.3 V 70 150 VCC = 5 V 3.3 V 60 −40 50 +25 Tamb (°C) +90 0 10 20 30 RPU (kΩ) 40 Ci = Co > 100 pF; RPU(in) = RPU(out) = 10 kΩ VCC = 3.3 V or 5.5 V Fig 13. Input/output tPHL versus temperature Fig 14. Connection circuitry VO − VI PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 14 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 12. Test information VCC VCC PULSE GENERATOR VI DUT RT CL 100 pF RL 10 kΩ VO 002aab595 RL = load resistor CL = load capacitance includes jig and probe capacitance RT = termination resistance should be equal to the output impedance Zo of the pulse generator Fig 15. Test circuitry for switching times PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 15 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 13. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 A1 pin 1 index θ Lp 1 e bp 4 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 8o o 0 ISSUE DATE 99-12-27 03-02-18 Fig 16. Package outline SOT96-1 (SO8) PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 16 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 D E A X c y HE vMA Z 8 5 A2 pin 1 index A1 (A3) A θ Lp L 1 e bp 4 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 θ 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 Fig 17. Package outline SOT505-1 (TSSOP8) PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 17 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 18 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 18) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6 and 7 Table 6. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 7. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 18. PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 19 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 18. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 8. Acronym AdvancedTCA CDM cPCI ESD HBM I2C-bus MM PCI PICMG SMBus VME Abbreviations Description Advanced Telecommunications Computing Architecture Charged-Device Model compact Peripheral Component Interface Electrostatic Discharge Human Body Model Inter-Integrated Circuit bus Machine Model Peripheral Component Interface PCI Industrial Computer Manufacturers Group System Management Bus VERSAModule Eurocard PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 20 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 16. Revision history Table 9. Revision history Release date 20090819 Data sheet status Product data sheet Change notice 2nd 1st Supersedes PCA9512A_3 Document ID PCA9512A_4 Modifications: • Section 8.7 “Resistor pull-up value selection”, paragraph, sentence changed from “... always choose RPU ≤ 16 kΩ for VCC = 5.5 V maximum, RPU ≤ 24 kΩ for VCC = 3.6 V maximum.” to “... always choose RPU ≤ 65.7 kΩ for VCC = 5.5 V maximum, RPU ≤ 45 kΩ for VCC = 3.6 V maximum.” Figure 5 “Bus requirements for 3.3 V systems” updated: – changed from “rise time > 300 ns” to “rise time = 300 ns” – changed from “rise time < 20 ns” to “rise time = 20 ns” • • Figure 6 “Bus requirements for 5 V systems” updated: – changed from “rise time > 300 ns” to “rise time = 300 ns” – changed from “rise time < 20 ns” to “rise time = 20 ns” PCA9512A_3 PCA9512A_2 PCA9512A_1 20090720 20090528 20051007 Product data sheet Product data sheet Product data sheet - PCA9512A_2 PCA9512A_1 - PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 21 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9512A_4 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 — 19 August 2009 22 of 23 NXP Semiconductors PCA9512A Level shifting hot swappable I2C-bus and SMBus bus buffer 19. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Feature selection . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Start-up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connect circuitry. . . . . . . . . . . . . . . . . . . . . . . . 5 Maximum number of devices in series . . . . . . . 5 Propagation delays . . . . . . . . . . . . . . . . . . . . . . 6 Rise time accelerators . . . . . . . . . . . . . . . . . . . 7 ACC boost current enable. . . . . . . . . . . . . . . . . 7 Resistor pull-up value selection . . . . . . . . . . . . 7 Hot swapping and capacitance buffering application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application design-in information . . . . . . . . . 11 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 11 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 12 Typical performance characteristics . . . . . . . . 14 Test information . . . . . . . . . . . . . . . . . . . . . . . . 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Soldering of SMD packages . . . . . . . . . . . . . . 18 Introduction to soldering . . . . . . . . . . . . . . . . . 18 Wave and reflow soldering . . . . . . . . . . . . . . . 18 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 18 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 19 August 2009 Document identifier: PCA9512A_4