PCA9515ADP

PCA9515A I2C-bus repeater Rev. 04 — 11 April 2008 Product data sheet 1. General description The PCA9515A is a CMOS integrated circuit intended for application in I2C-bus and SMBus systems. While retaining all the operating modes and features of the I2C-bus system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9515A enables the system designer to isolate two halves of a bus, thus more devices or longer length can be accommodated. It can also be used to run two buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz bus is isolated when 400 kHz operation of the other is required. Two or more PCA9515As cannot be put in series. The PCA9515A design does not allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage levels are used to avoid lock-up conditions between the input and the output. A ‘regular LOW’ applied at the input of a PCA9515A will be propagated as a ‘buffered LOW’ with a slightly higher value. When this ‘buffered LOW’ is applied to another PCA9515A, PCA9516A or PCA9518/A in series, the second PCA9515A, PCA9516A or PCA9518/A will not recognize it as a ‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again. The PCA9510/A, PCA9511/A, PCA9512/A, PCA9513/A, PCA9514/A cannot be used in series with the PCA9515A, PCA9516A or PCA9518/A, but can be used in series with themselves since they use shifting instead of static offsets to avoid lock-up conditions. The output pull-down of each internal buffer is set for approximately 0.5 V, while the input threshold of each internal buffer is set about 0.07 V lower, when the output is internally driven LOW. This prevents a lock-up condition from occurring. 2. Features I I I I I I I I I I 2-channel, bidirectional buffer I2C-bus and SMBus compatible Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters Powered-off high-impedance I2C-bus pins Operating supply voltage range of 2.3 V to 3.6 V 5.5 V tolerant I2C-bus and enable pins NXP Semiconductors PCA9515A I2C-bus repeater I 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater) I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO8 and TSSOP8 (MSOP8) 3. Ordering information Table 1. Ordering information Tamb = −40 °C to +85 °C. Type number PCA9515AD PCA9515ADP Topside mark PA9515A 9515A Package Name SO8 TSSOP8[1] Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm Version SOT96-1 SOT505-1 [1] Also known as MSOP8. 4. Functional diagram VCC PCA9515A SDA0 SDA1 SCL0 SCL1 pull-up resistor EN 002aad738 GND Fig 1. Functional diagram of PCA9515A PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 2 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 5. Pinning information 5.1 Pinning n.c. SCL0 SDA0 GND 1 2 8 7 VCC SCL1 SDA1 EN n.c. SCL0 SDA0 GND 1 2 3 4 002aad737 8 7 VCC SCL1 SDA1 EN PCA9515AD 3 4 002aad736 6 5 PCA9515ADP 6 5 Fig 2. Pin configuration for SO8 Fig 3. Pin configuration for TSSOP8 (MSOP8) 5.2 Pin description Table 2. Symbol n.c. SCL0 SDA0 GND EN SDA1 SCL1 VCC Pin description Pin 1 2 3 4 5 6 7 8 Description not connected serial clock bus 0; open-drain 5 V tolerant I/O serial data bus 0; open-drain 5 V tolerant I/O supply ground (0 V) active HIGH repeater enable input (internal pull-up with 100 kΩ) serial data bus 1; open-drain 5 V tolerant I/O serial clock bus 1; open-drain 5 V tolerant I/O supply voltage PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 3 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 6. Functional description Refer to Figure 1 “Functional diagram of PCA9515A”. The PCA9515A integrated circuit contains two identical buffer circuits which enable I2C-bus and similar bus systems to be extended without degradation of system performance. The PCA9515A contains two bidirectional, open-drain buffers specifically designed to support the standard LOW-level contention arbitration of the I2C-bus. Except during arbitration or clock stretching, the PCA9515A acts like a pair of non-inverting, open-drain buffers, one for SDA and one for SCL. 6.1 Enable The EN pin is active HIGH with an internal pull-up and allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up until after the system power-up reset. It should never change state during an I2C-bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus parts being enabled. The enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures. 6.2 I2C-bus systems As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus). The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. This part designed to work with Standard-mode and Fast-mode I2C-bus devices in addition to SMBus devices. Standard-mode I2C-bus devices only specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus system where Standard-mode devices and multiple masters are possible. Under certain conditions higher termination currents can be used. Please see Application Note AN255, I2C/SMBus Repeaters, Hubs and Expanders for additional information on sizing resistors and precautions when using more than one PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction with the P82B96. PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 4 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 7. Application design-in information A typical application is shown in Figure 4. In this example, the system master is running on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. Both buses run at 100 kHz unless the slave bus is isolated and then the master bus can run at 400 kHz. Master devices can be placed on either bus. 3.3 V 5V 10 kΩ 10 kΩ 10 kΩ 10 kΩ VCC SDA SCL BUS MASTER 400 kHz SDA0 SCL0 SDA1 SCL1 SDA SCL SLAVE 100 kHz PCA9515A EN bus 0 bus 1 002aad739 Fig 4. Typical application The PCA9515A is 5 V tolerant, so it does not require any additional circuitry to translate between the different bus voltages. When one side of the PCA9515A is pulled LOW by a device on the I2C-bus, a CMOS hysteresis type input detects the falling edge and causes the internal driver on the other side to turn on, thus causing the other side to also go LOW. The side driven LOW by the PCA9515A will typically be at VOL = 0.5 V. In order to illustrate what would be seen in a typical application, refer to Figure 5 and Figure 6. If the bus master in Figure 4 were to write to the slave through the PCA9515A, we would see the waveform shown in Figure 5 on bus 0. This looks like a normal I2C-bus transmission until the falling edge of the 8th clock pulse. At that point, the master releases the data line (SDA) while the slave pulls it LOW through the PCA9515A. Because the VOL of the PCA9515A is typically round 0.5 V, a step in the SDA will be seen. After the master has transmitted the 9th clock pulse, the slave releases the data line. On the bus 1 side of the PCA9515A, the clock and data lines would have a positive offset from ground equal to the VOL of the PCA9515A. After the 8th clock pulse the data line will be pulled to the VOL of the slave device, which is very close to ground in this example. It is important to note that any arbitration or clock stretching events on bus 1 require that the VOL of the PCA9515A (see VOL−VILc in Section 9 “Static characteristics”) to be recognized by the PCA9515A and then transmitted to bus 0. PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 5 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 9th clock pulse SCL VOL of PCA9515A SDA VOL of master 002aad740 Fig 5. Bus 0 waveform 9th clock pulse SCL SDA VOL of PCA9515A VOL of slave 002aad741 Fig 6. Bus 1 waveform 8. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to pin GND. Symbol VCC Vbus I Ptot Tstg Tamb Parameter supply voltage voltage on DC current total power dissipation storage temperature ambient temperature operating in free air I2C-bus, SCL or SDA any pin Conditions Min −0.5 −0.5 −55 −40 Max +7 +7 50 100 +125 +85 Unit V V mA mW °C °C PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 6 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 9. Static characteristics Table 4. Static characteristics (VCC = 3.0 V to 3.6 V) VCC = 3.0 V to 3.6 V[1]; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Supplies VCC ICCH supply voltage HIGH-level supply current both channels HIGH; VCC = 3.6 V; SDAn = SCLn = VCC both channels LOW; VCC = 3.6 V; one SDA and one SCL = GND; other SDA and SCL open VCC = 3.6 V; SDAn = SCLn = GND 3.0 0.8 3.6 5 V mA Parameter Conditions Min Typ[2] Max Unit ICCL LOW-level supply current - 1.7 5 mA ICCLc contention LOW-level supply current - 1.6 5 mA Input SCLn; input/output SDAn VIH VIL VILc VIK ILI IIL VOL VOL−VILc HIGH-level input voltage LOW-level input voltage contention LOW-level input voltage input clamping voltage input leakage current LOW-level input current LOW-level output voltage II = −18 mA VI = 3.6 V SDAn, SCLn; VI = 0.2 V IOL = 20 µA or 6 mA [3] [3] 0.7VCC −0.5 −0.5 −1 0.47 - 0.52 - 5.5 +0.3VCC +0.4 −1.2 +1 5 0.6 70 V V V V µA µA V mV difference between LOW-level output guaranteed by design and LOW-level input voltage contention input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current on pin EN input leakage current input capacitance VI = 3.0 V or 0 V VI = 0.2 V VI = 3 V or 0 V Ci Enable VIL VIH IIL(EN) ILI Ci [1] [2] [3] −0.5 2.0 −1 - 6 −10 6 7 +0.8 5.5 −30 +1 7 pF V V µA µA pF For operation between published voltage ranges, refer to worst-case parameter in both ranges. Typical value taken at VCC = 3.3 V and Tamb = 25 °C. VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the SDAn/SCLn lines. PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 7 of 18 NXP Semiconductors PCA9515A I2C-bus repeater Table 5. Static characteristics (VCC = 2.3 V to 2.7 V) VCC = 2.3 V to 2.7 V[1]; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol Supplies VCC ICCH supply voltage HIGH-level supply current both channels HIGH; VCC = 2.7 V; SDAn = SCLn = VCC both channels LOW; VCC = 2.7 V; one SDA and one SCL = GND; other SDA and SCL open VCC = 2.7 V; SDAn = SCLn = GND 2.3 0.8 2.7 5 V mA Parameter Conditions Min Typ[2] Max Unit ICCL LOW-level supply current - 1.6 5 mA ICCLc contention LOW-level supply current - 1.6 5 mA Input SCLn; input/output SDAn VIH VIL VILc VIK ILI IIL VOL VOL−VILc HIGH-level input voltage LOW-level input voltage contention LOW-level input voltage input clamping voltage input leakage current LOW-level input current LOW-level output voltage II = −18 mA VI = 2.7 V SDAn, SCLn; VI = 0.2 V IOL = 20 µA or 6 mA [3] [3] 0.7VCC −0.5 −0.5 −1 0.47 - 0.52 - 5.5 +0.3VCC +0.4 −1.2 +1 10 0.6 70 V V V V µA µA V mV difference between LOW-level output guaranteed by design and LOW-level input voltage contention input capacitance LOW-level input voltage HIGH-level input voltage LOW-level input current on pin EN input leakage current input capacitance VI = 3.0 V or 0 V VI = 0.2 V VI = 3 V or 0 V Ci Enable VIL VIH IIL(EN) ILI Ci [1] [2] [3] −0.5 2.0 −1 - 6 −10 6 7 +0.8 5.5 −30 +1 7 pF V V µA µA pF For operation between published voltage ranges, refer to worst-case parameter in both ranges. Typical value taken at VCC = 2.5 V and Tamb = 25 °C. VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the SDAn/SCLn lines. PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 8 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 10. Dynamic characteristics Table 6. Dynamic characteristics (VCC = 2.3 V to 2.7 V) VCC = 2.3 V to 2.7 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol tPHL tPLH tTHL tTLH tsu th [1] [2] Parameter HIGH-to-LOW propagation delay LOW-to-HIGH propagation delay HIGH to LOW output transition time LOW to HIGH output transition time set-up time hold time Conditions Figure 7 Figure 7 Figure 7 Figure 7 EN HIGH before START condition EN HIGH after STOP condition [2] [2] Min 45 33 100 130 Typ[1] 82 113 57 148 - Max 130 190 - Unit ns ns ns ns ns ns Typical values taken at VCC = 2.5 V and Tamb = 25 °C. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. Table 7. Dynamic characteristics (VCC = 3.0 V to 3.6 V) VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. Symbol tPHL tPLH tTHL tTLH tsu th [1] [2] Parameter HIGH-to-LOW propagation delay LOW-to-HIGH propagation delay HIGH to LOW output transition time LOW to HIGH output transition time set-up time hold time Conditions Figure 7 Figure 7 Figure 7 Figure 7 EN HIGH before START condition EN HIGH after STOP condition [2] [2] Min 45 33 100 100 Typ[1] 68 102 58 147 - Max 120 180 - Unit ns ns ns ns ns ns Typical values taken at VCC = 3.3 V and Tamb = 25 °C. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. 10.1 AC waveforms 3.3 V input 1.5 V tPHL 80 % output 1.5 V tPLH 80 % 0.1 V 3.3 V 1.5 V 20 % tTHL 1.5 V 20 % tTLH VOL 002aad478 Fig 7. Propagation delay and transition times PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 9 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 11. Test information VCC VCC RL PULSE GENERATOR VI DUT RT VO CL 002aad479 RL = load resistor; 1.35 kΩ CL = load capacitance includes jig and probe capacitance; 50 pF RT = termination resistance should be equal to Zo of pulse generators Fig 8. Test circuit for open-drain outputs PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 10 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 12. Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE vMA Z 8 5 Q A2 A1 pin 1 index θ Lp 1 e bp 4 wM L detail X (A 3) A 0 2.5 scale 5 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012 θ 0.010 0.057 0.004 0.049 0.019 0.0100 0.014 0.0075 0.244 0.039 0.028 0.041 0.228 0.016 0.024 8o o 0 ISSUE DATE 99-12-27 03-02-18 Fig 9. PCA9515A_4 Package outline SOT96-1 (SO8) © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 11 of 18 NXP Semiconductors PCA9515A I2C-bus repeater TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 D E A X c y HE vMA Z 8 5 A2 pin 1 index A1 (A3) A θ Lp L 1 e bp 4 detail X wM 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 θ 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 Fig 10. Package outline SOT505-1 (TSSOP8) PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 12 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 13.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 13 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 11) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 8 and 9 Table 8. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 9. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 11. PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 14 of 18 NXP Semiconductors PCA9515A I2C-bus repeater temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 11. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 14. Abbreviations Table 10. Acronym CDM CMOS ESD HBM I2C-bus MM SMBus Abbreviations Description Charged-Device Model Complementary Metal-Oxide Semiconductor ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Machine Model System Management Bus PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 15 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 15. Revision history Table 11. Revision history Release date 20080411 Data sheet status Product data sheet Change notice Supersedes PCA9515A_3 Document ID PCA9515A_4 Modifications: • • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 1 “General description”, 4th paragraph: 5th and 6th sentences re-written Table 2 “Pin description”: – appended “open-drain 5 V tolerant I/O” to the descriptions of SCL0 (pin 2), SDA0 (pin 3), SDA1 (pin 6), and SCL1 (pin 7) – appended “(internal pull-up with 100 kΩ)” to the description of EN (pin 5) • Table 4 “Static characteristics (VCC = 3.0 V to 3.6 V)” and Table 5 “Static characteristics (VCC = 2.3 V to 2.7 V)”: – changed parameter description for ICCH from “quiescent supply current, both channels HIGH” to “HIGH-level supply current” (moved “both channels HIGH” to Conditions column) – changed parameter description for ICCL from “quiescent supply current, both channels LOW” to “LOW-level supply current” (moved “both channels LOW” to Conditions column) – sub-section “Enable”: changed symbol/parameter from “IIL, input current LOW, EN” to “IIL(EN), LOW-level input current on pin EN” • Table 6 “Dynamic characteristics (VCC = 2.3 V to 2.7 V)” and Table 7 “Dynamic characteristics (VCC = 3.0 V to 3.6 V)”: – changed symbol/parameter from “tSET, Enable to Start condition” to “tsu, set-up time”; added “EN HIGH before START condition” to Conditions column – changed symbol/parameter from “tHOLD, Enable after Stop condition” to “th, hold time”; added “EN HIGH after STOP condition” to Conditions column • • PCA9515A_3 (9397 750 14098) PCA9515A_2 (9397 750 13709) PCA9515A_1 (9397 98 13237) Added SMD package soldering information Added Section 14 “Abbreviations” Product data sheet Product data sheet Objective data sheet PCA9515A_2 PCA9515A_1 - 20040929 20040709 20040617 PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 16 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 16. Legal information 16.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9515A_4 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 04 — 11 April 2008 17 of 18 NXP Semiconductors PCA9515A I2C-bus repeater 18. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 10.1 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4 Application design-in information . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 9 Test information . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11 Soldering of SMD packages . . . . . . . . . . . . . . 13 Introduction to soldering . . . . . . . . . . . . . . . . . 13 Wave and reflow soldering . . . . . . . . . . . . . . . 13 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 13 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 April 2008 Document identifier: PCA9515A_4