PCA9541BS/02,118

厂商：
NXP(恩智浦)
封装：
VQFN16
描述：
IC I2C 2:1 SELECTOR 16-HVQFN

数据手册：

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数据手册
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PCA9541BS/02,118 数据手册

PCA9541 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 7.1 — 24 June 2015 Product data sheet 1. General description The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual master I2C-bus applications where system operation is required, even when one master fails or the controller card is removed for maintenance. The two masters (for example, primary and back-up) are located on separate I2C-buses that connect to the same downstream I2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are used to select one master at a time. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices on the downstream I2C-bus. Two versions are offered for different architectures. PCA9541/01 with channel 0 selected at start-up and PCA9541/03 with no channel selected after start-up. The interrupt outputs are used to provide an indication of which master has control of the bus. One interrupt input (INT_IN) collects downstream information and propagates it to the 2 upstream I2C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used to let the previous bus master know that it is not in control of the bus anymore and to indicate the completion of the bus recovery/initialization sequence. Those interrupts can be disabled and will not generate an interrupt if the masking option is set. A bus recovery/initialization if enabled sends nine clock pulses, a not acknowledge, and a STOP condition in order to set the downstream I2C-bus devices to an initialized state before actually switching the channel to the selected master. An interrupt is sent to the upstream channel when the recovery/initialization procedure is completed. An internal bus sensor senses the downstream I2C-bus traffic and generates an interrupt if a channel switch occurs during a non-idle bus condition. This function is enabled when the PCA9541 recovery/initialization is not used. The interrupt signal informs the master that an external I2C-bus recovery/initialization needs to be performed. It can be disabled and an interrupt will not be generated. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage, which will be passed by the PCA9541. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V devices can communicate with 5 V devices without any additional protection. The PCA9541 does not isolate the capacitive loading on either side of the device, so the designer must take into account all trace and device capacitances on both sides of the device, and pull-up resistors must be used on all channels. External pull-up resistors pull the bus to the desired voltage level for each channel. All I/O pins are 6.0 V tolerant. PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset An active LOW reset input allows the PCA9541 to be initialized. Pulling the RESET pin LOW resets the I2C-bus state machine and configures the device to its default state as does the internal Power-On Reset (POR) function. 2. Features and benefits                        2-to-1 bidirectional master selector I2C-bus interface logic; compatible with SMBus standards PCA9541/01 powers up with Channel 0 selected PCA9541/03 powers up with no channel selected and either master can take control of the bus Active LOW interrupt input 2 active LOW interrupt outputs Active LOW reset input 4 address pins allowing up to 16 devices on the I2C-bus Channel selection via I2C-bus Bus initialization/recovery function Bus traffic sensor Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Software identical for both masters Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 6.0 V tolerant inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA Packages offered: SO16, TSSOP16, HVQFN16 3. Applications     PCA9541_7 Product data sheet High reliability systems with dual masters Gatekeeper multiplexer on long single bus Bus initialization/recovery for slave devices without hardware reset Allows masters without arbitration logic to share resources All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 2 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 4. Ordering information Table 1. Ordering information Tamb = 40 C to +85 C Type number Package Name Description Version PCA9541D/01 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PCA9541PW/01 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PCA9541BS/01 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1 body 4  4  0.85 mm PCA9541D/03 SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PCA9541PW/03 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 PCA9541BS/03 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; SOT629-1 body 4  4  0.85 mm 5. Marking Table 2. Marking codes Type number PCA9541_7 Product data sheet Topside mark PCA9541D/01 PCA9541D/01 PCA9541PW/01 9541/01 PCA9541BS/01 41/1 PCA9541D/03 PCA9541D/03 PCA9541PW/03 9541/03 PCA9541BS/03 41/3 All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 3 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 6. Block diagram PCA9541 SCL_MST0 SDA_MST0 INPUT FILTER A3 A2 A1 A0 RESET VDD SCL_MST1 SDA_MST1 STOP DETECTION BUS SENSOR SLAVE CHANNEL SWITCH CONTROL LOGIC I2C-BUS CONTROL AND REGISTER BANK SCL_SLAVE SDA_SLAVE POWER-ON RESET INPUT FILTER STOP DETECTION BUS RECOVERY/ INITIALIZATION OSCILLATOR INT0 INT1 INTERRUPT LOGIC INT_IN 002aab382 VSS Fig 1. Block diagram of PCA9541 PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 4 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 7. Pinning information 7.1 Pinning INT0 1 16 VDD SDA_MST0 2 15 INT_IN SCL_MST0 3 14 SDA_SLAVE RESET 4 13 SCL_SLAVE SCL_MST1 5 PCA9541D/01 PCA9541D/03 12 A3 SDA_MST1 6 11 A2 INT1 7 VSS 8 10 A1 9 INT0 1 16 VDD SDA_MST0 2 15 INT_IN SCL_MST0 3 14 SDA_SLAVE RESET 4 SCL_MST1 5 SDA_MST1 6 11 A2 INT1 7 10 A1 VSS 8 A0 PCA9541PW/01 PCA9541PW/03 002aab379 12 A3 9 A0 002aab380 SDA_MST1 4 14 VDD 13 INT_IN 11 SCL_SLAVE 10 A3 9 8 3 A1 SCL_MST1 PCA9541BS/01 PCA9541BS/03 7 2 A0 RESET Pin configuration for TSSOP16 12 SDA_SLAVE 6 1 VSS SCL_MST0 5 terminal 1 index area 15 INT0 Fig 3. 16 SDA_MST0 Pin configuration for SO16 INT1 Fig 2. 13 SCL_SLAVE A2 002aab381 Transparent top view Fig 4. Pin configuration for HVQFN16 PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 5 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 7.2 Pin description Table 3. Pin description Symbol Pin Description SO16, TSSOP16 INT0 1 15 active LOW interrupt output 0 (external pull-up required) SDA_MST0 2 16 serial data master 0 (external pull-up required) SCL_MST0 3 1 serial clock master 0 (external pull-up required) RESET 4 2 active LOW reset input (external pull-up required) SCL_MST1 5 3 serial clock master 1 (external pull-up required) SDA_MST1 6 4 serial data master 1 (external pull-up required) INT1 7 5 active LOW interrupt output 1 (external pull-up required) 8 6[1] supply ground VSS A0 9 7 address input 0 (externally held to VSS or VDD) A1 10 8 address input 1 (externally held to VSS or VDD) A2 11 9 address input 2 (externally held to VSS or VDD) A3 12 10 address input 3 (externally held to VSS or VDD) SCL_SLAVE 13 11 serial clock slave (external pull-up required) SDA_SLAVE 14 12 serial data slave (external pull-up required) INT_IN 15 13 active LOW interrupt input (external pull-up required) VDD 16 14 supply voltage [1] PCA9541_7 Product data sheet HVQFN16 HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the printed-circuit board in the thermal pad region. All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 6 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 8. Functional description Refer to Figure 1 “Block diagram of PCA9541”. 8.1 Device address Following a START condition, the upstream master that wants to control the I2C-bus or make a status check must send the address of the slave it is accessing. The slave address of the PCA9541 is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable pins and they must be pulled HIGH or LOW. 1 1 1 A3 fixed A2 A1 A0 R/W hardware selectable 002aab390 Fig 5. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while logic 0 selects a write operation. Remark: Reserved I2C-bus addresses must be used with caution since they can interfere with: • ‘reserved for future use’ I2C-bus addresses (1111 1XX) • slave devices that use the 10-bit addressing scheme (1111 0XX) 8.2 Command Code Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9541, which will be stored in the Command Code register. 0 0 0 AI 0 auto-increment 0 B1 B0 register number 002aab391 Fig 6. Command Code The 2 LSBs are used as a pointer to determine which register will be accessed. If the auto-increment flag is set (AI = 1), the two least significant bits of the Command Code are automatically incremented after a byte has been read or written. This allows the user to program the registers sequentially or to read them sequentially. • During a read operation, the contents of these bits will roll over to 00b after the last allowed register is accessed (10b). PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 7 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset • During a write operation, the PCA9541 will acknowledge bytes sent to the IE and CONTROL registers, but will not acknowledge a byte sent to the Interrupt Status Register since it is a read-only register. The 2 LSBs of the Command Code do not roll over to 00b but stay at 10b. Only the 2 least significant bits are affected by the AI flag. Unused bits must be programmed with zeros. Any command code (write operation) different from ‘000AI 0000’, ‘000AI 0001’, and ‘000AI 0010’ will not be acknowledged. At power-up, this register defaults to all zeros. Table 4. Command Code register B1 B0 Register name Type Register function 0 0 IE R/W interrupt enable 0 1 CONTROL R/W control switch 1 0 ISTAT R only interrupt status 1 1 not allowed Each system master controls its own set of registers, however they can also read specific bits from the other system master. PCA9541 IE REG#00 IE 0 IE 1 REG#00 IE CONTROL REG#01 CONTROL 0 CONTROL 1 REG#01 CONTROL ISTAT REG#10 ISTAT 0 ISTAT 1 REG#10 ISTAT MASTER 0 SCL_MST0 SDA_MST0 Fig 7. 002aab392 MASTER 1 SCL_MST1 SDA_MST1 Internal register map 8.3 Interrupt Enable and Control registers description When a master seeks control of the bus by connecting its I2C-bus channel to the PCA9541 downstream channel, it has to write to the CONTROL register (Reg#01). Bits MYBUS and BUSON allow the master to take control of the bus. The MYBUS and the NMYBUS bits determine which master has control of the bus. Table 9 explains which master gets control of the bus and how. There is no arbitration. Any master can take control of the bus when it wants regardless of whether the other master is using it or not. The BUSON and the NBUSON bits determine whether the upstream bus is connected or disconnected to/from the downstream bus. Table 10 explains when the upstream bus is connected or disconnected. Internally, the state machine does the following: • If the combination of the BUSON and the NBUSON bits causes the upstream to be disconnected from the downstream bus, then that is done. So in this case, the values of the MYBUS and the NMYBUS do not matter. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 8 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset • If a master was connected to the downstream bus prior to the disconnect, then an interrupt is sent on the respective interrupt output in an attempt to let that master know that it is no longer connected to the downstream bus. This is indicated by setting the BUSLOST bit in the Interrupt Status Register. • If the combination of the BUSON and the NBUSON bits causes a master to be connected to the downstream bus and if there is no change in the BUSON bits since when the disconnect took effect, then the master requesting the bus is connected to the downstream bus. If it requests a bus initialization sequence, then it is performed. • If there is no change in the combination of the BUSON and the NBUSON bits and a new master wants the bus, then the downstream bus is disconnected from the old master that was using it and the new master gets control of it. Again, the bus initialization if requested is done. The appropriate interrupt signals are generated. After a master has sent the bus control request: 1. The previous master is disconnected from the I2C-bus. An interrupt to the previous master is sent through its INT line to let it know that it lost control of the bus. BUSLOST bit in the Interrupt Status Register is set. This interrupt can be masked by setting the BUSLOSTMSK bit to logic 1. 2. A built-in bus initialization/recovery function can take temporary control of the downstream channel to initialize the bus before making the actual switch to the new bus master. This function is activated by setting the BUSINIT to logic 1 by the master during the same write sequence as the one programming MYBUS and BUSON bits. When activated and whether the bus was previously idle or not: a. 9 clock pulses are sent on the SCL_SLAVE. b. SDA_SLAVE line is released (HIGH) when the clock pulses are sent to SCL_SLAVE. This is equivalent to sending 8 data bits and a not acknowledge. c. Finally a STOP condition is sent to the downstream slave channel. This sequence will complete any read transaction which was previously in process and the downstream slave configured as a slave-transmitter should release the SDA line because the PCA9541 did not acknowledge the last byte. 3. When the initialization has been requested and completed, the PCA9541 sends an interrupt to the new master through its INT line and connects the new master to the downstream channel. BUSINIT bit in the Interrupt Status Register is set. The switch operation occurs after the master asking the bus control has sent a STOP command. This interrupt can be masked by setting the BUSINITMSK bit to logic 1. 4. When the bus initialization/recovery function has not been requested (BUSINIT = 0), the PCA9541 connects the new master to the slave downstream channel. The switch operation occurs after the master asking the bus control has sent a STOP command. PCA9541 sends an interrupt to the new master through its INT line if the built-in bus sensor function detects a non-idle condition in the downstream slave channel at the switching time. BUSOK bit in the Interrupt Status Register is set. This means that a STOP condition has not been detected in the previous bus communication and that an external bus recovery/initialization must be performed. If an idle condition has been detected at the switching time, no interrupt will be sent. This interrupt can be masked by setting the BUSOKMSK bit to logic 1. Interrupt status can be read. See Section 8.4 “Interrupt Status registers” for more information. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 9 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset The MYTEST and the NMYTEST bits cause the interrupt pins of the respective masters to be activated for a ‘functional interrupt test’. Remark: The regular way to proceed is that a master asks to take the control of the bus by programming MYBUS and BUSON bits based on NMUYBUS and NBUSON values. Nevertheless, the same master can also decide to give up the control of the bus and give it to the other master. This is also done by programming the MYBUS and BUSON bits based on NMYBUS and NBUSON values. Remark: Any writes either to the Interrupt Enable Register or the Control Register cause the respective register to be updated on the 9th clock cycle, that is, on the rising edge of the acknowledge clock cycle. Remark: The actual switch from one channel to another or the switching off of both the channels happens on a STOP command that is sent by the master requesting the switch. 8.3.1 Register 0: Interrupt Enable (IE) register (B1:B0 = 00b) This register allows a master to read and/or write (if needed) Mask options for its own channel. The Interrupt Enable register described below is identical for both the masters. Nevertheless, there are physically 2 internal Interrupt Enable registers, one for each upstream channel. When Master 0 reads/writes in this register, the internal Interrupt Enable Register 0 will be accessed. When Master 1 reads/writes in this register, the internal Interrupt Enable Register 1 will be accessed. Table 5. Register 0 - Interrupt Enable (IE) register (B1:B0 = 00b) bit allocation 7 6 5 4 3 2 1 0 0 0 0 0 BUSLOSTMSK BUSOKMSK BUSINITMSK INTINMSK Table 6. Register 0 - Interrupt Enable (IE) register bit description Legend: * default value Bit Symbol Access Value[1] Description 7:4 - R only 0* not used 3 BUSLOSTMSK R/W 0* An interrupt on INT will be generated after the other master has been disconnected. 1 An interrupt on INT will not be generated after the other master has been disconnected. 0* After connection is requested and Bus Initialization not requested (BUSINIT = 0), an interrupt on INT will be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment. 2 BUSOKMSK R/W Remark: Channel switching is done automatically after the STOP command. 1 After connection is requested and Bus Initialization not requested (BUSINIT = 0), an interrupt on INT will not be generated when a non-idle situation has been detected on the downstream slave channel by the bus sensor at the switching moment (masked). Remark: Channel switching is done automatically after the STOP command. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 10 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset Table 6. Register 0 - Interrupt Enable (IE) register bit description …continued Legend: * default value Bit Symbol Access Value[1] Description 1 BUSINITMSK R/W 0* After connection is requested and Bus Initialization requested (BUSINIT = 1), an interrupt on INT will be generated when the bus initialization is done. Remark: Channel switching is done after bus initialization completed. 1 After connection is requested and Bus Initialization requested (BUSINIT = 1), an interrupt on INT will not be generated when the bus initialization is done (masked). Remark: Channel switching is done after bus initialization completed. 0 INTINMSK [1] R/W 0* Interrupt on INT_IN will generate an interrupt on INT. 1 Interrupt on INT_IN will not generate an interrupt on INT (masked) Default values are the same for PCA9541/01 and PCA9541/03. 8.3.2 Register 1: Control Register (B1:B0 = 01b) The Control Register described below is identical for both the masters. Nevertheless, there are physically 2 internal Control Registers, one for each upstream channel. When master 0 reads/writes in this register, the internal Control Register 0 will be accessed. When master 1 reads/writes in this register, the internal Control Register 1 will be accessed. Table 7. Register 1 - Control Register (B1:B0 = 01b) bit allocation 7 6 5 4 3 2 1 0 NTESTON TESTON 0 BUSINIT NBUSON BUSON NMYBUS MYBUS Table 8. Register 1 - Control Register (B1:B0 = 01b) bit description Legend: * default value Bit Symbol Access Value[1] Description 7 NTESTON R/W 0* A logic level HIGH to the INT line of the other channel is sent (interrupt cleared). 1 A logic level LOW to the INT line of the other channel is sent (interrupt generated). A logic level HIGH to the INT line is sent (interrupt cleared). 6 TESTON R/W 0* 1 A logic level LOW to the INT line is sent (interrupt generated). 5 - R only 0* not used 4 BUSINIT R/W 0* Bus initialization is not requested. 1 Bus initialization is requested. 3 NBUSON R only see Table 11 NBUSON bit along with BUSON bit decides whether any upstream channel is connected to the downstream channel or not. See Table 10, Table 11, and Table 12. 2 BUSON R/W see Table 11 BUSON bit along with the NBUSON bit decides whether any upstream channel is connected to the downstream channel or not. See Table 10, Table 11, and Table 12. 1 NMYBUS R only see Table 11 NMYBUS bit along with MYBUS bit decides which upstream channel is connected to the downstream channel. See Table 9, Table 11, and Table 12. 0 MYBUS R/W see Table 11 MYBUS bit along with the NMYBUS bit decides which upstream channel is connected to the downstream channel. See Table 9, Table 11, and Table 12. [1] Default values are the same for PCA9541/01 and PCA9541/03. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 11 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset Table 9. MYBUS and NMYBUS truth table As a master reads its Control Register NMYBUS[1] MYBUS[1] Slave channel 0 0 The master reading this combination has control of the bus. 1 0 The master reading this combination does not have control of the bus. 0 1 The master reading this combination does not have control of the bus. 1 1 The master reading this combination has control of the bus. [1] MYBUS and NMYBUS is an exclusive-OR type function where: Equal values (00b or 11b) means that the master reading its Control Register has control of the bus. Different values (01b or 10b) means that the master reading its Control Register does not have control of the bus. Table 10. BUSON and NBUSON truth table NBUSON[1] BUSON[1] Slave channel 0 0 off 1 0 on 0 1 on 1 1 off [1] BUSON and NBUSON is an exclusive-OR type function where: Equal values (00b or 11b) means that the connection between the upstream and the downstream channels is off. Different values (01b or 10b) means that the connection between the upstream and the downstream channels is on. Switch to the new channel is done when the master initiating the switch request sends a STOP command to the PCA9541. If either master wants to change the connection of the downstream channel, it needs to write to its Control Register (Reg#01), and then send a STOP command because an update of the connection to the downstream according to the values in the two internal Control Registers happens only on a STOP command. Writing to one control register followed by a STOP condition on the other master's channel will not cause an update to the downstream connection. When both masters request a switch to their own channel at the same time, the master who last wrote to its Control Register before the PCA9541 receives a STOP command wins the switching sequence. There is no arbitration performed. The Auto Increment feature (AI = 1) allows to program the PCA9541 in 4 bytes: Start 111A3A2A1A0 + 0 00010000 Data Reg#00 Data Reg#01 Stop PCA9541_7 Product data sheet PCA9541 Address + Write Select Reg#00 with AI = 1 Interrupt Enable Register data Control Register data All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 12 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset Table 11. Default Control Register values Type version Master Bit 7 Bit 6 NTESTON TESTON PCA9541/01 PCA9541/03 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used BUSINIT NBUSON BUSON NMYBUS MYBUS MST_0 0 0 0 0 0 1 0 0 MST_1 0 0 0 0 1 0 1 0 MST_0 0 0 0 0 0 0 0 0 MST_1 0 0 0 0 0 0 1 0 Table 12 describes which command needs to be written to the Control Register when a master device wants to take control of the I2C-bus. Byte written to the Control Register is a function of the current I2C-bus control status performed after an initial reading of the Control Register. Current status of the I2C-bus is determined by the bits MYBUS, NMYBUS, BUSON and NBUSON is one of the following: • • • • The master reading its Control Register does not have control and the I2C-bus is off. The master reading its Control Register does not have control and the I2C-bus is on. The master reading its Control Register has control and the I2C-bus is off. The master reading its Control Register has control and the I2C-bus is on. ‘I2C-bus off’ means that upstream and downstream channels are not connected together. ‘I2C-bus on’ means that upstream and downstream channels are connected together. Remark: Only the 4 LSBs of the Control Register are described in Table 12 since only those bits control the I2C-bus control. The logic value for the 4 MSBs is specific to the application and are not discussed in the table. The read sequence is performed by the master as: S - 111xxxx0 - 000x0001 - Sr - 111xxxx1 - DataRead - P The write sequence is performed by the master as: S - 111xxxx0 - 000x0001 - DataWritten - P PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 13 of 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Bus control sequence Read Control Register performed by the master Byte read[1] Status NBUSON BUSON Write Control Register performed by the master NMYBUS MYBUS Hex Byte written[1][2] Action performed to take mastership NBUSON[3] BUSON NMYBUS[3] MYBUS Hex bus off has control 0 0 0 0 4 bus on x 1 x 0 1 bus off no control 0 0 0 1 4 bus on, take control x 1 x 0 2 bus off no control 0 0 1 0 5 bus on, take control x 1 x 1 3 bus off has control 0 0 1 1 5 bus on x 1 x 1 4 bus on has control 0 1 0 0 - no change 5 bus on no control 0 1 0 1 4 take control x 1 x 0 6 bus on no control 0 1 1 0 5 take control x 1 x 1 7 bus on has control 0 1 1 1 - no change no write required 8 bus on has control 1 0 0 0 - no change no write required no write required 9 bus on no control 1 0 0 1 0 take control x 0 x 0 A bus on no control 1 0 1 0 1 take control x 0 x 1 B bus on has control 1 0 1 1 - no change C bus off has control 1 1 0 0 0 bus on x 0 x 0 D bus off no control 1 1 0 1 0 bus on, take control x 0 x 0 E bus off no control 1 1 1 0 1 bus on, take control x 0 x 1 F bus off has control 1 1 1 1 1 bus on x 0 x 1 Only the 4 LSBs are shown. [2] x0x0 in binary = 0, 2, 8 or A in hexadecimal x0x1 in binary = 1, 3, 9 or B in hexadecimal x1x0 in binary = 4, 6, C or E in hexadecimal PCA9541 14 of 42 © NXP Semiconductors N.V. 2015. All rights reserved. x1x1 in binary = 5, 7, D or F in hexadecimal x can be either ‘0’ or ‘1’ since those bits are read-only bits. no write required 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 7.1 — 24 June 2015 All information provided in this document is subject to legal disclaimers. 0 [1] [3] NXP Semiconductors PCA9541_7 Product data sheet Table 12. PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 8.4 Interrupt Status registers The PCA9541 provides 4 different types of interrupt: • To indicate to the former I2C-bus master that it is not in control of the bus anymore • To indicate to the new I2C-bus master that: – The bus recovery/initialization has been performed and that the downstream channel connection has been done (built-in bus recovery/initialization active). – A ‘bus not well initialized’ condition has been detected by the PCA9541 when the switch has been done (built-in bus recovery/initialization not active). This information can be used by the new master to initiate its own bus recovery/initialization sequence. • Indicate to both I2C-bus upstream masters that a downstream interrupt has been generated through the INT_IN pin. • Functionality wiring test. 8.4.1 Bus control lost interrupt When an upstream master takes control of the I2C-bus while the other channel was using the downstream channel, an interrupt is generated to the master losing control of the bus (INT line goes LOW to let the master know that it lost the control of the bus) immediately after disconnection from the downstream channel. By setting the BUSLOSTMSK bit to ‘1’, the interrupt is masked and the upstream master that lost the I2C-bus control does not receive an interrupt (INT line does not go LOW). 8.4.2 Recovery/initialization interrupt Before switching to a new upstream channel, an automatic bus recovery/initialization can be performed by the PCA9541. This function is requested by setting the BUSINIT bit to ‘1’. When the downstream bus has been initialized, an interrupt to the new master is generated (INT line goes LOW). By setting the BUSINITMSK bit to ‘1’, the interrupt is masked and the new master does not receive an interrupt (INT line does not go LOW). When the automatic bus recovery/initialization is not requested, if the built-in bus sensor function (sensing permanently the downstream I2C-bus traffic) detects a non-idle condition (previous bus channel connected to the downstream slave channel, was between a START and STOP condition), then an interrupt to the new master is sent (INT line goes LOW). This interrupt tells the new master that an external bus recovery/initialization must be performed. By setting the BUSOKMSK bit to ‘1’, the interrupt is masked and the new master does not receive an interrupt (INT line does not go LOW). Remark: In this particular situation, after the switch to the new master is performed, a read of the Interrupt Status Register is not possible if the switch happened in the middle of a read sequence because the new master does not have control of the SDA line. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 15 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 8.4.3 Downstream interrupt An interrupt can also be generated by a downstream device by asserting the INT_IN pin LOW. When INT_IN is asserted LOW and if both INTINMSK bits are not set to ‘1’ by either master, INT0 and INT1 both go LOW. By setting the INTINMSK bit to ‘1’ by a master and/or the INTINMSK bit to ‘1’ by the other master, the interrupt(s) is (are) masked and the corresponding masked channel(s) does (do) not receive an interrupt (INT0 and/or INT1 line does (do) not go LOW). 8.4.4 Functional test interrupt A master can send an interrupt to itself to test its own INT wire or send an interrupt to the other master to test its INT line. This is done by: • setting the TESTON bit to ‘1’ to test its own INT line • setting the NTESTON bit to ‘1’ to test the other master INT line Setting the TESTON and/or NTESTON bits to ‘0’ by a master will clear the interrupt(s). Remark: Interrupt outputs have an open-drain structure. Interrupt input does not have any internal pull-up resistor and must not be left floating (that is, pulled HIGH to VDD through resistor) in order to avoid any undesired interrupt conditions. 8.4.5 Register 2: Interrupt Status Register (B1:B0 = 10b) The Interrupt Status Register for both the masters is identical and is described below. Nevertheless, there are physically 2 internal Interrupt Registers, one for each upstream channel. When Master 0 reads this register, the internal Interrupt Register 0 will be accessed. When Master 1 reads this register, the internal Interrupt Register 1 will be accessed. Table 13. Register 2 - Interrupt Status register (B1:B0 = 10b) bit allocation 7 6 5 4 3 2 1 0 NMYTEST MYTEST 0 0 BUSLOST BUSOK BUSINIT INTIN Table 14. Register 2 - Interrupt Status (ISTAT) register bit description Legend: * default value Bit Symbol Access Value[1] Description 7 NMYTEST[2] R only 6 MYTEST[2] R only 0* no interrupt generated due to NTESTON bit from the other master (NTESTON = 0 from the other master)[3] 1 interrupt generated due to TESTON bit from the other master (NTESTON = 1 from the other master)[3] 0* no interrupt generated by TESTON bit (TESTON = 0)[3] 1 interrupt generated by TESTON bit (TESTON = 1)[3] 5 - R only 0* not used 4 - R only 0* not used 3 BUSLOST[4] R only 0* no interrupt generated to the previous master when switching to the new one is initiated 1 interrupt generated to the previous master when switching to the new one is initiated PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 16 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset Table 14. Register 2 - Interrupt Status (ISTAT) register bit description …continued Legend: * default value Bit Symbol Access Value[1] Description 2 BUSOK[4] R only BUSINIT[4] 1 INTIN[2] 0 R only R only 0* no interrupt generated by bus sensor function 1 interrupt generated by bus sensor function (masked when bus recovery/initialization requested) - Bus was not idle when the switch occurred 0* no interrupt generated by the bus recovery/initialization function 1 interrupt generated by the bus recovery/initialization function; recovery/initialization done 0* no interrupt on interrupt input (INT_IN)[5] 1 interrupt on interrupt input (INT_IN)[5] [1] Default values are the same for PCA9541/01 and PCA9541/03. [2] Reading the Interrupt Status Register does not clear the MYTEST, NMYTEST or the INTIN bits. They are cleared if: INT_IN lines goes HIGH for INTIN bit TESTON bit is cleared for MYTEST bit NTESTON bit is cleared for NMYTEST bit [3] Interrupt on a master is cleared after TESTON bit is cleared by the same master or NTESTON bit is cleared by the other master. [4] BUSINIT, BUSOK and BUSLOST bits in the Interrupt Status Register get cleared after a read of the same register is done. Precisely, the register gets cleared on the second clock pulse during the read operation. [5] If the interrupt condition remains on INT_IN after the read sequence, another interrupt will be generated (if the interrupt has not been masked). 8.5 Power-on reset When power is applied to VDD, an internal power-on reset holds the PCA9541 in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the internal registers are initialized to their default states, with: • PCA9541/01: default Channel 0 (no STOP detect) After power-up and/or insertion of the device in the main I2C-bus, the upstream Channel 0 and the downstream slave channel are connected together. • PCA9541/03: default ‘no channel’ (no STOP detect) After power-up and/or insertion of the device in the main I2C-bus, no channel will be connected to the downstream channel. The device is ready to receive a START condition and its address by a master. If either register writes to its Control Register, then the connection between the upstream and the downstream channels is determined by the values on the Control Registers. Thereafter, VDD must be lowered below 0.2 V to reset the device. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 17 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 8.6 External reset A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst)L. The PCA9541 registers and I2C-bus state machine will be held in their default states until the RESET input is once again HIGH. This input typically requires a pull-up resistor to VDD. Default states are: • I2C-bus upstream Channel 0 connected to the I2C-bus downstream channel for the PCA9541/01 • no I2C-bus upstream channel connected to the I2C-bus downstream channel for the PCA9541/03. 8.7 Voltage translation The pass gate transistors of the PCA9541 are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another. 002aaa964 5.0 Vo(sw) (V) 4.0 (1) (2) 3.0 (3) 2.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) (1) maximum (2) typical (3) minimum Fig 8. Pass gate voltage as a function of supply voltage Figure 8 shows the voltage characteristics of the pass gate transistors (note that the graph was generated using the data specified in Section 12 “Static characteristics” of this data sheet). In order for the PCA9541 to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main buses were running at 5 V, and the downstream bus was 3.3 V, then Vo(sw) should be equal to or below 3.3 V to effectively clamp the downstream bus voltages. Looking at Figure 8, we see that Vo(sw)(max) will be at 3.3 V when the PCA9541 supply voltage is 3.5 V or lower so the PCA9541 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 17). More Information on voltage translation can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 18 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 9. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 9). 6'$ 6&/ GDWDOLQH VWDEOH GDWDYDOLG Fig 9. FKDQJH RIGDWD DOORZHG PED Bit transfer 9.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 10). 6'$ 6&/ 6 3 67$57FRQGLWLRQ 6723FRQGLWLRQ PED Fig 10. Definition of START and STOP conditions PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 19 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 9.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 11). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 11. System configuration 9.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 S START condition 8 9 clock pulse for acknowledgement 002aaa987 Fig 12. Acknowledgement on the I2C-bus PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 20 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 9.5 Bus transactions slave address data Interrupt Enable (IE) register command code register data control register (CONTROL) S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 1 0 0 0 0 A A START condition acknowledge from slave R/W auto increment acknowledge from slave acknowledge from slave A P acknowledge from slave STOP condition 002aab607 Fig 13. Write to the Interrupt Enable and Control registers using the Auto-Increment (AI) bit Remark: If a third data byte is sent, it will not be acknowledged by the PCA9541. command code register access to register xx = 00, 01, or 10 slave address S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 1 0 0 START condition R/W auto increment acknowledge from slave (1) x slave address x A Sr 1 1 1 A3 A2 A1 A0 1 A acknowledge from slave re-START condition R/W acknowledge from slave (3) (2) A A acknowledge from master acknowledge from master A P no acknowledge from master STOP condition 002aab608 (1) xx = 00: Interrupt Enable register xx = 01: Control register xx = 10: INT register (2) xx = 00: Control register xx = 01: INT register xx = 10: Interrupt Enable register (3) xx = 00: INT register xx = 01: Interrupt Enable register xx = 10: Control register Fig 14. Read the 3 registers using the Auto-Increment (AI) bit Remark: If a fourth data byte is read, the first register will be accessed. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 21 of 42 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx slave address command code register NXP Semiconductors PCA9541_7 Product data sheet After the STOP condition MASTER 1 is disconnected from the downstream channel. SDA_MST0(1) data Control register S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 AI 0 0 0 1 A 0 0 0 1 0 1 0 0 A P START condition R/W acknowledge from slave auto increment acknowledge from slave BUSINIT BUSON MYBUS acknowledge from slave SCL_MST0 STOP condition if the interrupt is not masked (BUSLOSTMSK = 0) SCL_SLAVE 1 2 3 4 5 6 7 8 9 SDA_SLAVE A STOP command INT0 if the interrupt is not masked (BUSINITMSK = 0) MASTER 1 has control of the bus PCA9541 has control of the bus MASTER 0 has control of the bus MASTER 0 must wait for the 'bus free time' value (between STOP and START) defined in the I2C-bus specification before sending commands to the downstream devices. (1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus). Fig 15. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization requested) PCA9541 22 of 42 © NXP Semiconductors N.V. 2015. All rights reserved. 002aab609 2-to-1 I2C-bus master selector with interrupt logic and reset Rev. 7.1 — 24 June 2015 All information provided in this document is subject to legal disclaimers. INT1 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset SDA_MST0(1) slave address command code register After the STOP condition MASTER 1 is disconnected from the downstream channel, and MASTER 0 is connected to the downstream channel. data Control register S 1 1 1 A3 A2 A1 A0 0 A 0 0 0 AI 0 0 0 1 A 0 0 0 0 0 1 0 0 A P START condition R/W acknowledge from slave auto increment acknowledge from slave BUSINIT BUSON MYBUS STOP condition acknowledge from slave SCL_MST0 INT1 if the interrupt is not masked (BUSLOSTMSK = 0) INT0 if MASTER 1 was not idle at the switching moment and the interrupt is not masked (BUSINITMSK = 0) MASTER 1 has control of the bus MASTER 0 must wait for the 'bus free time' value (between STOP and START) defined in the I2C-bus specification before sending commands to the downstream devices. MASTER 0 has control of the bus 002aab610 (1) We assume that a read of the Control register was done by MASTER 0 before this sequence and that 000x 0101 was read (MASTER 1 controlling the bus). Fig 16. Write to the Control register and switch from Channel 1 to Channel 0 (bus recovery/initialization not requested) PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 23 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 10. Application design-in information SLAVE CARD 3.3 V VDD VDD MASTER 0 SCL0 SCL_MST0 SDA0 SDA_MST0 RESET0 PCA9541 INT0 INT0 SLAVE 2 INT SDA INT_IN VSS SCL SDA_SLAVE SCL_SLAVE RESET SDA SCL SLAVE 1 SDA SCL SLAVE 3 3.3 V VDD MASTER 1 SCL1 SCL_MST1 SDA1 SDA_MST1 RESET1 INT1 INT1 VSS A3 A2 A1 A0 VSS 002aab611 Fig 17. Typical application 10.1 Specific applications The PCA9541 is a 2-to-1 I2C-bus master selector designed for dual master, high reliability I2C-bus applications, where continuous maintenance and control monitoring is required even if one master fails or its controller card is removed for maintenance. The PCA9541 can also be used in other applications, such as where masters share the same resource but cannot share the same bus, as a gatekeeper multiplexer in long single bus applications or as a bus initialization/recovery device. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 24 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 10.2 High reliability systems SCL1 SDA1 MASTER 1 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 SCL0 SDA0 PCA9541 MASTER 0 In a typical multipoint application, shown in Figure 18, the two masters (for example, primary and back-up) are located on separate I2C-buses that connect to multiple downstream I2C-bus slave cards/devices via a PCA9541/01 for non-hot swap applications to provide high reliability of the I2C-bus. 002aab612 Fig 18. High reliability backplane application I2C-bus commands are sent via the primary or back-up master and either master can take command of the I2C-bus. Either master at any time can gain control of the slave devices if the other master is disabled or removed from the system. The failed master is isolated from the system and will not affect communication between the on-line master and the slave devices located on the cards. SCL1 SDA1 MASTER 1 MASTER 1 MASTER 1 MASTER 1 SCL1 SDA1 PCA9541 SCL0 SDA0 SCL1 SDA1 PCA9541 MASTER 0 SCL0 SDA0 SCL1 SDA1 PCA9541 MASTER 0 SCL0 SDA0 PCA9541 MASTER 0 SCL0 SDA0 MASTER 0 For even higher reliability in multipoint backplane applications, two dedicated masters can be used for every card as shown in Figure 19. 002aab613 Fig 19. Very high reliability backplane application PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 25 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 10.3 Masters with shared resources Some masters may not be multi-master capable or some masters may not work well together and continually lock up the bus. The PCA9541 can be used to separate the masters, as shown in Figure 20, but still allow shared access to slave devices, such as Field Replaceable Unit (FRU) EEPROMs or temperature sensors. ASSEMBLY A SDA/SCL SLAVE A1 SLAVE A2 ASSEMBLY B SDA/SCL SLAVE B1 SLAVE B2 PCA9541 MASTER A SLAVE A0 MAIN MASTER PCA9541 MASTER B SLAVE B0 002aab614 Fig 20. Masters with shared resources application 10.4 Gatekeeper multiplexer The PCA9541/03 can act as a gatekeeper multiplexer in applications where there are multiple I2C-bus devices with the same fixed address (for example, EEPROMs with address of ‘Z’ as shown in Figure 21) connected in a multipoint arrangement to the same I2C-bus. Up to 16 hot swappable cards/devices can be multiplexed to the same bus master by using one PCA9541/03 per card/device. Since each PCA9541/03 has its own unique address (for example, ‘A’, ‘B’, ‘C’, and so on), the EEPROMs can be connected to the master, one at a time, by connecting one PCA9541/03 (Master 0 position) while keeping the rest of the cards/devices isolated (off position). The alternative, shown with dashed lines, is to use a PCA9548 1-to-8 channel switch on the master card and run 8 I2C-bus devices, one to each EEPROM card, to multiplex the master to each card. The number of card pins used is the same in either case, but there are 7 less pairs of SDA/SCL traces on the printed-circuit board if the PCA9541/03 is used. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 26 of 42 PCA9541 NXP Semiconductors PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 PCA9541 A B C D E F G H EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM EEPROM PCA9548 MASTER 0 2-to-1 I2C-bus master selector with interrupt logic and reset Z Z Z Z Z Z Z Z 002aab615 Fig 21. Gatekeeper multiplexer application 10.5 Bus initialization/recovery to initialize slaves without hardware reset If the I2C-bus is hung, I2C-bus devices without a hardware reset pin (for example, Slave 1 and Slave 2 in Figure 22) can be isolated from the master by the PCA9541/03. The PCA9541/03 disconnects the bus when it is reset via the hardware reset line, restoring the master's control of the rest of the bus (for example, Slave 0). The bus master can then command the PCA9541/03 to send 9 clock pulses/STOP condition to reset the downstream I2C-bus devices before they are reconnected to the master or leave the downstream devices isolated. SDA/SCL MASTER SLAVE 1 PCA9541/03 SDA slave I2C-bus SCL SLAVE 0 SLAVE 2 RESET 002aab616 Fig 22. Bus initialization/recovery application PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 27 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 11. Limiting values Table 15. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V).[1] Symbol Parameter VDD VI Min Max Unit supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V II input current 20 +20 mA IO output current 25 +25 mA IDD supply current 100 +100 mA ISS ground supply current 100 +100 mA Ptot total power dissipation - 400 mW Tstg storage temperature 60 +150 C Tamb ambient temperature 40 +85 C [1] Conditions operating in free air The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C. 12. Static characteristics Table 16. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 2.3 - 5.5 V VDD = 3.6 V - 152 200 A VDD = 5.5 V - 349 600 A VDD = 3.6 V - 30 80 A VDD = 5.5 V - 40 100 A - 1.5 2.1 V Supply VDD supply voltage IDD supply current Istb VPOR standby current power-on reset voltage Operating mode; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; no load; VI = VDD or VSS; fSCL = 0 kHz no load; VI = VDD or VSS [1] Input SCL_MSTn; input/output SDA_MSTn (upstream and downstream channels) VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA 1 - +1 A VDD = 2.3 V to 3.6 V - 4 5 pF VDD = 3.6 V to 5.5 V - 4 6 pF IL leakage current VI = VDD or VSS Ci input capacitance VI = VSS PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 28 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset Table 16. Static characteristics …continued VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 0.5 - +0.3VDD V 0.7VDD - 6 V 1 - +1 A VDD = 2.3 V to 3.6 V - 2 3 pF VDD = 3.6 V to 5.5 V - 2 5 pF VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA 4 12 24  VDD = 3.0 V to 3.6 V; VO = 0.4 V; IO = 15 mA 5 14 30  VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA 7 17 55  Select inputs A0 to A3, INT_IN, RESET VIL LOW-level input voltage VIH HIGH-level input voltage ILI input leakage current VI = VDD or VSS Ci input capacitance VI = VSS Pass gate ON-state resistance Ron Vo(sw) switch output voltage leakage current IL Vi(sw) = VDD = 5.0 V; Io(sw) = 100 A - 3.6 - V Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = 100 A 2.6 - 4.5 V Vi(sw) = VDD = 3.3 V; Io(sw) = 100 A - 2.2 - V Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = 100 A 1.6 - 2.8 V Vi(sw) = VDD = 2.5 V; Io(sw) = 100 A - 1.5 - V Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = 100 A 1.1 - 2.0 V VI = VDD or VSS 1 - +1 A 3 - - mA INT0 and INT1 outputs LOW-level output current VOL = 0.4 V IOL [1] VDD must be lowered to 0.2 V in order to reset part. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 29 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 13. Dynamic characteristics Table 17. Symbol Dynamic characteristics Parameter Standard-mode Fast-mode I2C-bus Unit I2C-bus Conditions [1] (SDA_MSTn to SDA_SLAVE) or (SCL_MSTn to SCL_SLAVE) Min Max Min Max - 0.3 - 0.3 ns tPD propagation delay fSCL SCL clock frequency 0 100 0 400 kHz fSCL(init/rec) SCL clock frequency (bus initialization/bus recovery) 50 150 50 150 kHz tBUF bus free time between a STOP and START condition 4.7 - 1.3 - s tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;DAT data hold time 0[3] 3.45 0[3] 0.9 s tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[4] 300 ns [4] 300 ns [2] tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb Cb capacitive load for each bus line - 400 - 400 pF tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW [5] - 1 - 1 s LOW-to-HIGH [5] - 0.6 - 0.6 s - 1 - 1 s tv(INT_IN-INTn) valid time from pin INT_IN to pin INTn signal - 4 - 4 s td(INT_IN-INTn) delay time from pin INT_IN to pin INTn inactive - 2 - 2 s tVD;ACK data valid acknowledge time INT tw(rej)L LOW-level rejection time INT_IN input 1 - 1 - s tw(rej)H HIGH-level rejection time INT_IN input 0.5 - 0.5 - s 4 - 4 - ns 500 - 500 - ns 0 - 0 - ns RESET tw(rst)L LOW-level reset time trst reset time tREC;STA SDA clear recovery time to START condition [6][7] [1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 30 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset [4] Cb = total capacitance of one bus line in pF. [5] Measurements taken with 1 k pull-up resistor and 50 pF load. [6] Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions. [7] Upon reset, the full delay will be the sum of trst and the RC time constant of the SDA bus. 0.7 × VDD SDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 23. Definition of timing on the I2C-bus protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1 / fSCL 0.7 × VDD SCL 0.3 × VDD tBUF tf tr 0.7 × VDD SDA 0.3 × VDD tSU;DAT tHD;STA tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Rise and fall times, refer to VIL and VIH. Fig 24. I2C-bus timing diagram PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 31 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % tREC;STA 50 % tw(rst)L trst 50 % INTn 002aae735 Fig 25. Definition of RESET timing 14. Test information VDD PULSE GENERATOR VI RL 500 Ω VO 6.0 V open VSS DUT RT CL 50 pF 002aab393 Definitions test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 26. Test circuitry for switching times PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 32 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 15. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ ș /S / H Z 0 ES GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP LQFKHV ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Fig 27. Package outline SOT109-1 (SO16) PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 33 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ SLQLQGH[ $ $ $ ș /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7( 02 Fig 28. Package outline SOT403-1 (TSSOP16) PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 34 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset +94)1SODVWLFWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP % ' 627 $ WHUPLQDO LQGH[DUHD $ $ ( F GHWDLO; H & H H \ \ & Y 0 & $ % Z 0 & E / H H (K H WHUPLQDO LQGH[DUHD ; 'K PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 PP $ PD[ $ E F ' 'K ( (K H H H / Y Z \ \ 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627 02 (8523($1 352-(&7,21 ,668('$7( Fig 29. Package outline SOT629-1 (HVQFN16) PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 35 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 16.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 16.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 36 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 16.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 30) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 18 and 19 Table 18. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 19. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 30. PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 37 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 30. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 17. Abbreviations Table 20. PCA9541_7 Product data sheet Abbreviations Acronym Description AI Auto Increment CDM Charged Device Model DUT Device Under Test EEPROM Electrically Erasable Programmable Read-Only Memory ESD ElectroStatic Discharge FRU Field Replaceable Unit HBM Human Body Model I2C-bus Inter Integrated Circuit bus IC Integrated Circuit MM Machine Model POR Power-On Reset RC Resistor-Capacitor network SMBus System Management Bus All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 38 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 18. Revision history Table 21. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9541_7.1 20150624 Product data sheet - PCA9541_7 - PCA9541_6 Modifications: PCA9541_7 Modifications: • Updated Figure 17 20090702 • Product data sheet Type numbers PCA9541D//02, PCA9541PW/02 and PCA9541BS/02 are withdrawn; this affects: – Section 1 “General description”, 2nd paragraph modified; (old) 11th paragraph deleted – Section 2 “Features and benefits”, (old) 4th bullet item deleted – Table 1 “Ordering information” modified – Table 2 “Marking codes” modified – Figure 2, Figure 3 and Figure 4 modified – Table 6 “Register 0 - Interrupt Enable (IE) register bit description”, Table note [1] modified – Table 8 “Register 1 - Control Register (B1:B0 = 01b) bit description”, Table note [1] modified – Table 11 “Default Control Register values” modified – Table 14 “Register 2 - Interrupt Status (ISTAT) register bit description”, Table note [1] modified – Section 8.5 “Power-on reset”, (old) 2nd bullet item deleted – Section 8.6 “External reset”, (old) 2nd bullet item deleted – Section 10.2 “High reliability systems”, 1st paragraph modified • (Old) Table 16 “Static characteristics (2.3 V to 3.6 V)” and (old) Table 17 “Static characteristics (3.6 V to 5.5 V)” are merged. • Table 16 “Static characteristics”, sub-section “Supply”: – Istb (Typ) at condition VDD = 2.3 V to 3.6 V changed from “10 A” to “30 A” – Istb (Max) at condition VDD = 2.3 V to 3.6 V changed from “100 A” to “80 A” – Istb (Typ) at condition VDD = 3.6 V to 5.5 V changed from “10 A” to “40 A” – Istb (Max) at condition VDD = 3.6 V to 5.5 V changed from “200 A” to “100 A” • Table 16 “Static characteristics”, sub-section “Input SCL_MSTn; input/output SDA_MSTn (upstream and downstream channels): • Table 16 “Static characteristics”, sub-section “Select inputs A0 to A3, INT_IN, RESET”: – for condition VDD = 3.6 V to 5.5 V, deleted IIL and IIH specifications (was in old Table 17) – for condition VDD = 3.6 V to 5.5 V, ILI (Max) changed from “+50 A” to “+1 A” (from old Table 17) • Table 16 “Static characteristics”, sub-section “Pass gate”: – for condition VDD = 3.6 V to 5.5 V, IL (Max) changed from +100 A to +1 A (was in old Table 17) • Figure 25 “Definition of RESET timing” modified: – changed signal name from “LEDx” to “INTn” – deleted “LED off” PCA9541_6 20080911 Product data sheet - PCA9541_5 PCA9541_5 20071001 Product data sheet - PCA9541_4 PCA9541_4 20060104 Product data sheet - PCA9541_3 PCA9541_3 (9397 750 14746) 20050713 Product data sheet - PCA9541_2 PCA9541_2 (9397 750 13629) 20041001 Product data sheet - PCA9541_1 PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 39 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset Table 21. Revision history …continued Document ID Release date Data sheet status Change notice Supersedes PCA9541_1 (9397 750 12453) 20031202 Product data sheet 853-2436 01-A14594 - PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 40 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 19.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9541_7 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7.1 — 24 June 2015 © NXP Semiconductors N.V. 2015. All rights reserved. 41 of 42 PCA9541 NXP Semiconductors 2-to-1 I2C-bus master selector with interrupt logic and reset 21. Contents 1 2 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.5 8.5 8.6 8.7 9 9.1 9.2 9.3 9.4 9.5 10 10.1 10.2 10.3 10.4 10.5 11 12 13 14 15 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 Command Code . . . . . . . . . . . . . . . . . . . . . . . . 7 Interrupt Enable and Control registers description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Register 0: Interrupt Enable (IE) register (B1:B0 = 00b) . . . . . . . . . . . . . . . . . . . . . . . . . 10 Register 1: Control Register (B1:B0 = 01b) . . 11 Interrupt Status registers. . . . . . . . . . . . . . . . . 15 Bus control lost interrupt . . . . . . . . . . . . . . . . . 15 Recovery/initialization interrupt. . . . . . . . . . . . 15 Downstream interrupt . . . . . . . . . . . . . . . . . . . 16 Functional test interrupt . . . . . . . . . . . . . . . . . 16 Register 2: Interrupt Status Register (B1:B0 = 10b) . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 17 External reset . . . . . . . . . . . . . . . . . . . . . . . . . 18 Voltage translation . . . . . . . . . . . . . . . . . . . . . 18 Characteristics of the I2C-bus . . . . . . . . . . . . 19 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 START and STOP conditions . . . . . . . . . . . . . 19 System configuration . . . . . . . . . . . . . . . . . . . 20 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 21 Application design-in information . . . . . . . . . 24 Specific applications . . . . . . . . . . . . . . . . . . . . 24 High reliability systems . . . . . . . . . . . . . . . . . . 25 Masters with shared resources. . . . . . . . . . . . 26 Gatekeeper multiplexer . . . . . . . . . . . . . . . . . 26 Bus initialization/recovery to initialize slaves without hardware reset . . . . . . . . . . . . . . . . . . 27 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 28 Static characteristics. . . . . . . . . . . . . . . . . . . . 28 Dynamic characteristics . . . . . . . . . . . . . . . . . 30 Test information . . . . . . . . . . . . . . . . . . . . . . . . 32 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 33 16 16.1 16.2 16.3 16.4 17 18 19 19.1 19.2 19.3 19.4 20 21 Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 36 36 37 38 39 41 41 41 41 41 41 42 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 24 June 2015 Document identifier: PCA9541_7

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