PCA9548AD,112

PCA9548A 8-channel I2C-bus switch with reset Rev. 5.1 — 1 October 2015 Product data sheet 1. General description The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individual SCx/SDx channel or combination of channels can be selected, determined by the contents of the programmable control register. An active LOW reset input allows the PCA9548A to recover from a situation where one of the downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the channels to be deselected as does the internal Power-on reset function. The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9548A. This allows the use of different bus voltages on each pair, so that 1.8 V or 2.5 V or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 6 V tolerant. 2. Features and benefits                1-of-8 bidirectional translating switches I2C-bus interface logic; compatible with SMBus standards Active LOW reset input Three address pins allowing up to eight devices on the I2C-bus Channel selection via I2C-bus, in any combination Power-up with all switch channels deselected Low Ron switches Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 6 V tolerant inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Three packages offered: SO24, TSSOP24, and HVQFN24 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 3. Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9548ABS 548A HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4  4  0.85 mm SOT616-1 PCA9548AD PCA9548AD SO24 plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 PCA9548APW PCA9548A TSSOP24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum order quantity Temperature PCA9548ABS PCA9548ABS,118 HVQFN24 Reel 13” Q1/T1 *Standard mark SMD 6000 Tamb = 40 C to +85 C PCA9548ABSHP HVQFN24 Reel 13” Q2/T3 *Standard mark SMD 6000 Tamb = 40 C to +85 C PCA9548AD,112 SO24 Standard marking IC’s tube - DSC bulk pack 1200 Tamb = 40 C to +85 C PCA9548AD,118 SO24 Reel 13” Q1/T1 *Standard mark SMD 1000 Tamb = 40 C to +85 C PCA9548APW,112 TSSOP24 Standard marking IC’s tube - DSC bulk pack 1575 Tamb = 40 C to +85 C PCA9548APW,118 TSSOP24 Reel 13” Q1/T1 *Standard mark SMD 2500 Tamb = 40 C to +85 C PCA9548AD PCA9548APW PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 2 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 4. Block diagram PCA9548A SC0 SC1 SC2 SC3 SC4 SC5 SC6 SC7 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 VSS VDD RESET SCL SDA SWITCH CONTROL LOGIC RESET CIRCUIT INPUT FILTER A0 I2C-BUS CONTROL A1 A2 002aab202 Fig 1. Block diagram of PCA9548A PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 3 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 5. Pinning information 5.1 Pinning A0 1 24 VDD A0 1 A1 2 23 SDA A1 2 24 VDD 23 SDA RESET 3 22 SCL RESET 3 22 SCL SD0 4 21 A2 SD0 4 21 A2 SC0 5 20 SC7 SC0 5 20 SC7 SD1 6 19 SD7 SD1 6 SC1 7 18 SC6 SC1 7 SD2 8 17 SD6 SD2 8 17 SD6 SC2 9 16 SC5 SC2 9 16 SC5 SD3 10 15 SD5 SD3 10 15 SD5 SC3 11 14 SC4 SC3 11 14 SC4 VSS 12 13 SD4 VSS 12 13 SD4 PCA9548AD PCA9548APW 002aab199 18 SC6 002aab200 Pin configuration for TSSOP24 19 SCL 20 SDA 21 VDD 22 A0 terminal 1 index area 23 A1 Fig 3. 24 RESET Pin configuration for SO24 SD0 1 18 A2 SC0 2 17 SC7 SD1 3 SC1 4 SD2 5 14 SD6 SC2 6 13 SC5 16 SD7 15 SC6 SD5 12 9 VSS SC4 11 8 SD4 10 7 SC3 PCA9548ABS SD3 Fig 2. 19 SD7 002aab201 Transparent top view Fig 4. PCA9548A Product data sheet Pin configuration for HVQFN24 (transparent top view) All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 4 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 5.2 Pin description Table 3. Symbol Product data sheet Pin Description SO24, TSSOP24 HVQFN24 A0 1 22 address input 0 A1 2 23 address input 1 RESET 3 24 active LOW reset input SD0 4 1 serial data 0 SC0 5 2 serial clock 0 SD1 6 3 serial data 1 SC1 7 4 serial clock 1 SD2 8 5 serial data 2 SC2 9 6 serial clock 2 SD3 10 7 serial data 3 SC3 11 8 serial clock 3 VSS 12 9[1] supply ground SD4 13 10 serial data 4 SC4 14 11 serial clock 4 SD5 15 12 serial data 5 SC5 16 13 serial clock 5 SD6 17 14 serial data 6 SC6 18 15 serial clock 6 SD7 19 16 serial data 7 SC7 20 17 serial clock 7 A2 21 18 address input 2 SCL 22 19 serial clock line SDA 23 20 serial data line VDD 24 21 supply voltage [1] PCA9548A Pin description HVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 5 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 6. Functional description Refer to Figure 1 “Block diagram of PCA9548A”. 6.1 Device address Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9548A is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. 1 1 1 0 A2 fixed A1 A0 R/W hardware selectable 002aab189 Fig 5. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9548A, which will be stored in the control register. If multiple bytes are received by the PCA9548A, it will save the last byte received. This register can be written and read via the I2C-bus. channel selection bits (read/write) 7 6 5 4 3 2 1 0 B7 B6 B5 B4 B3 B2 B1 B0 channel 0 channel 1 channel 2 channel 3 channel 4 channel 5 channel 6 channel 7 002aab204 Fig 6. PCA9548A Product data sheet Control register All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 6 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 6.2.1 Control register definition One or several SCx/SDx downstream pair, or channel, is selected by the contents of the control register. This register is written after the PCA9548A has been addressed. The contents of the control byte are used to determine which channel is to be selected. When a channel is selected, the channel will become active after a STOP condition has been placed on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is made active, so that no false conditions are generated at the time of connection. Table 4. Control register: Write—channel selection; Read—channel status B7 B6 B5 B4 B3 B2 B1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 X 0 0 1 B0 Command 0 channel 0 disabled 1 channel 0 enabled X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 1 channel 1 disabled channel 1 enabled channel 2 disabled channel 2 enabled channel 3 disabled channel 3 enabled channel 4 disabled channel 4 enabled channel 5 disabled channel 5 enabled channel 6 disabled channel 6 enabled channel 7 disabled channel 7 enabled Remark: Multiple channels can be enabled at the same time. Example: B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0, means that channels 7, 5, 4, 1 and 0 are disabled and channels 6, 3, and 2 are enabled. Care should be taken not to exceed the maximum bus capacitance. Default condition is all zeroes. 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9548A will reset its register and I2C-bus state machine and will deselect all channels. The RESET input must be connected to VDD through a pull-up resistor. 6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9548A in a reset condition until VDD has reached VPOR. At this point, the reset condition is released and the PCA9548A register and I2C-bus state machine are initialized to their default states (all zeroes) causing all the channels to be deselected. Thereafter, VDD must be lowered below 0.2 V for at least 5 s in order to reset the device. PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 7 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 6.5 Voltage translation The pass gate transistors of the PCA9548A are constructed such that the VDD voltage can be used to limit the maximum voltage that will be passed from one I2C-bus to another. 002aaa964 5.0 Vo(sw) (V) 4.0 (1) (2) 3.0 (3) 2.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) (1) maximum (2) typical (3) minimum Fig 7. Pass gate voltage versus supply voltage Figure 7 shows the voltage characteristics of the pass gate transistors (note that the PCA9548A is only tested at the points specified in Section 11 “Static characteristics” of this data sheet). In order for the PCA9548A to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw)(max) will be at 2.7 V when the PCA9548A supply voltage is 3.5 V or lower, so the PCA9548A supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 14). More Information can be found in Application Note AN262: PCA954X family of I2C/SMBus multiplexers and switches. PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 8 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8). SDA SCL data line stable; data valid Fig 8. change of data allowed mba607 Bit transfer 7.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9). SDA SCL S P START condition STOP condition mba608 Fig 9. Definition of START and STOP conditions 7.3 System configuration A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 10). PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 9 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 10. System configuration 7.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 S START condition 8 9 clock pulse for acknowledgement 002aaa987 Fig 11. Acknowledgement on the I2C-bus PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 10 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 7.5 Bus transactions Data is transmitted to the PCA9548A control register using the Write mode as shown in Figure 12. slave address SDA S 1 1 1 0 A2 control register A1 A0 START condition 0 R/W A B7 B6 B5 B4 B3 B2 acknowledge from slave B1 B0 A P acknowledge from slave STOP condition 002aab205 Fig 12. Write control register Data is read from PCA9548A using the Read mode as shown in Figure 13. slave address SDA S 1 1 1 0 A2 START condition last byte control register A1 A0 1 R/W A B7 B6 acknowledge from slave B5 B4 B3 B2 B1 B0 NA P no acknowledge from master STOP condition 002aab206 Fig 13. Read control register PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 11 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 8. Application design-in information VDD = 2.7 V to 5.5 V VDD = 3.3 V V = 2.7 V to 5.5 V SDA SDA SD0 SCL SCL SC0 channel 0 V = 2.7 V to 5.5 V RESET I2C/SMBus master SD1 channel 1 SC1 V = 2.7 V to 5.5 V SD2 channel 2 SC2 V = 2.7 V to 5.5 V SD3 channel 3 SC3 PCA9548A SD4 V = 2.7 V to 5.5 V channel 4 SC4 V = 2.7 V to 5.5 V SD5 channel 5 SC5 V = 2.7 V to 5.5 V SD6 channel 6 SC6 V = 2.7 V to 5.5 V A2 A1 A0 SD7 VSS SC7 channel 7 002aab203 Fig 14. Typical application PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 12 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS (ground = 0 V). Symbol Parameter VDD VI Conditions Min Max Unit supply voltage 0.5 +7.0 V input voltage 0.5 +7.0 V II input current - 20 mA IO output current - 25 mA IDD supply current - 100 mA ISS ground supply current - 100 mA Ptot total power dissipation - 400 mW - 125 C 60 +150 C 40 +85 C Tj(max) maximum junction temperature Tstg storage temperature Tamb ambient temperature [1] [1] operating The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C. 10. Thermal characteristics Table 6. PCA9548A Product data sheet Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient HVQFN24 package 40 C/W SO24 package 77 C/W TSSOP24 package 128 C/W All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 13 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 11. Static characteristics Table 7. Static characteristics at VDD = 2.3 V to 3.6 V VSS = 0 V; Tamb = –40 C to +85 C; unless otherwise specified. See Table 8 on page 15 for VDD = 4.5 V to 5.5 V.[1] Symbol Parameter Conditions Min Typ Max Unit Supply VDD supply voltage 2.3 - 3.6 V IDD supply current operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 30 50 A Istb standby current standby mode; VDD = 3.6 V; no load; VI = VDD or VSS - 0.1 1 A VPOR power-on reset voltage no load; VI = VDD or VSS - 1.6 2.1 V 0.5 - +0.3VDD V [2] Input SCL; input/output SDA VIL LOW-level input voltage VIH HIGH-level input voltage IOL LOW-level output current 0.7VDD - 6 V VOL = 0.4 V 3 6 - mA VOL = 0.6 V 6 9 - mA IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 15 21 pF Select inputs A0 to A2, RESET VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V ILI input leakage current pin at VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 2 5 pF ON-state resistance VDD = 3.0 V to 3.6 V; VO = 0.4 V; IO = 15 mA 5 11 30  VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA 7 16 55  Vi(sw) = VDD = 3.3 V; Io(sw) = 100 A - 1.9 - V Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = 100 A 1.6 - 2.8 V Vi(sw) = VDD = 2.5 V; Io(sw) = 100 A - 1.5 - V Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = 100 A 1.1 - 2.0 V Pass gate Ron Vo(sw) switch output voltage IL leakage current VI = VDD or VSS 1 - +1 A Cio input/output capacitance VI = VSS - 3 5 pF [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 14 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset Table 8. Static characteristics at VDD = 4.5 V to 5.5 V VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. See Table 7 on page 14 for VDD = 2.3 V to 3.6 V.[1] Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V Supply VDD supply voltage IDD supply current operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz - 65 100 A Istb standby current standby mode; VDD = 5.5 V; no load; VI = VDD or VSS - 0.2 1 A VPOR power-on reset voltage no load; VI = VDD or VSS - 1.7 2.1 V [2] Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V IOL LOW-level output current 3 - - mA VOL = 0.6 V 6 - - mA IIL LOW-level input current VI = VSS 1 - +1 A IIH HIGH-level input current VI = VDD 1 - +1 A Ci input capacitance VI = VSS - 15 21 pF VOL = 0.4 V Select inputs A0 to A2, RESET VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 6 V ILI input leakage current pin at VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 2 5 pF Ron ON-state resistance VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA 4 9 24  Vo(sw) switch output voltage Vi(sw) = VDD = 5.0 V; Io(sw) = 100 A - 3.6 - V Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = 100 A 2.6 - 4.5 V Pass gate IL leakage current VI = VDD or VSS 1 - +1 A Cio input/output capacitance VI = VSS - 3 5 pF [1] For operation between published voltage ranges, refer to the worst-case parameter in both ranges. [2] VDD must be lowered to 0.2 V for at least 5 s in order to reset part. PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 15 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 12. Dynamic characteristics Table 9. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus from SDA to SDx, or SCL to SCx Fast-mode I2C-bus Unit Min Max Min Max - 0.3[1] - 0.3[1] ns 0 100 0 400 kHz 4.7 - 1.3 - s 4.0 - 0.6 - s tPD propagation delay fSCL SCL clock frequency tBUF bus free time between a STOP and START condition tHD;STA hold time (repeated) START condition tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;DAT data hold time 0[3] [4] 0[3] [4] s tSU;DAT data set-up time 250 - 100 - ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[5] 300 ns 0.1Cb[5] 300 ns [2] tf fall time of both SDA and SCL signals - 300 20 + Cb capacitive load for each bus line - 400 - 400 pF tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns tVD;DAT data valid time HIGH-to-LOW [6] - 1 - 1 s LOW-to-HIGH [6] - 0.6 - 0.6 s data valid acknowledge time - 1 - 1 s tw(rst)L LOW-level reset time 4 - 4 - ns trst reset time - 500 - 500 ns tREC;STA recovery time to START condition 0 - 0 - ns tVD;ACK RESET SDA clear [1] Pass gate propagation delay is calculated from the 20  typical Ron and the 15 pF load capacitance. [2] After this period, the first clock pulse is generated. [3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. [4] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. [5] Cb = total capacitance of one bus line in pF. [6] Measurements taken with 1 k pull-up resistor and 50 pF load. PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 16 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 0.7 × VDD SDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 15. Definition of timing on the I2C-bus ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % 50 % tREC;STA tw(rst)L 002aac549 Fig 16. Definition of RESET timing protocol START condition (S) tSU;STA bit 7 MSB (A7) tLOW bit 6 (A6) tHIGH bit 0 (R/W) acknowledge (A) STOP condition (P) 1 / fSCL 0.7 × VDD SCL 0.3 × VDD tBUF tr tf 0.7 × VDD SDA 0.3 × VDD tHD;STA tSU;DAT tHD;DAT tVD;DAT tVD;ACK tSU;STO 002aab175 Fig 17. I2C-bus timing diagram PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 17 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 13. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F +( \ Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S /   H ES GHWDLO; Z 0   PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ PP                                                    LQFKHV   =   ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 18. Package outline SOT137-1 (SO24) PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 18 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F +( \ Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   ES H GHWDLO; Z 0   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ (8523($1 352-(&7,21 ,668('$7(   02 Fig 19. Package outline SOT355-1 (TSSOP24) PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 19 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset +94)1SODVWLFWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP % ' 627 $ WHUPLQDO LQGH[DUHD $ $ ( F GHWDLO; H & H H  \ & Y 0 & $ % Z 0 & E  \ /   H H (K H  WHUPLQDO LQGH[DUHD    ; 'K   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV $ 81,7 $ F E 'K ' PD[ PP           ( (K H H H / Y Z \ \              1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627  02  (8523($1 352-(&7,21 ,668('$7(    Fig 20. Package outline SOT616-1 (HVQFN24) PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 20 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 21 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 21) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 10 and 11 Table 10. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 11. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 21. PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 22 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 21. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 23 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 15. Soldering: PCB footprints )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI62SDFNDJH 627 +[ *[ 3  +\ *\  %\ $\ & '[ ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3  3 $\   %\ & ' '    *[   *\ +[ +\    VRWBIU Fig 22. PCB footprint for SOT137-1 (SO24); reflow soldering PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 24 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH 627 +[ *[ 3  +\ *\  %\ $\ & '[ ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3 3 $\ %\ & ' ' *[ *\ +[ +\            VRWBIU Fig 23. PCB footprint for SOT355-1 (TSSOP24); reflow soldering PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 25 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH 627 +[ *[ ' 3   &  63[ Q63[ +\ 63\WRW 63\ *\ 6/\ Q63\ %\ $\ 63[WRW 6/[ %[ $[ *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG VROGHUSDVWHGHSRVLW VROGHUODQGSOXVVROGHUSDVWH RFFXSLHGDUHD Q63[ Q63\   'LPHQVLRQVLQPP 3 $[ $\ %[ %\ & ' 6/[ 6/\ 63[WRW 63\WRW 63[ 63\ *[ *\ +[ +\                  ,VVXHGDWH   VRWBIU Fig 24. PCB footprint for SOT616-1 (HVQFN24); reflow soldering PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 26 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 16. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model ESD ElectroStatic Discharge HBM Human Body Model IC Integrated Circuit I2C-bus Inter-Integrated Circuit bus I/O Input/Output LSB Least Significant Bit MSB Most Significant Bit PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus 17. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9548A v.5.1 20151001 Product data sheet - PCA9548A v.5 Modifications: • Section 6.2.1 “Control register definition”, first paragraph, third sentence: corrected from “The 2 LSBs of the control byte...” to “The contents of the control byte...”. PCA9548A v.5 20140331 Product data sheet - PCA9548A v.4 PCA9548A v.4 20130215 Product data sheet - PCA9548A v.3 PCA9548A v.3 20090707 Product data sheet - PCA9548A v.2 PCA9548A v.2 20060925 Product data sheet - PCA9548A v.1 PCA9548A v.1 20050415 Product data sheet - - PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 27 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA9548A Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 28 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP Semiconductors N.V. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9548A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.1 — 1 October 2015 © NXP B.V. 2015. All rights reserved. 29 of 30 PCA9548A NXP Semiconductors 8-channel I2C-bus switch with reset 20. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.3 6.4 6.5 7 7.1 7.2 7.3 7.4 7.5 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 6 Control register definition . . . . . . . . . . . . . . . . . 7 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage translation . . . . . . . . . . . . . . . . . . . . . . 8 Characteristics of the I2C-bus . . . . . . . . . . . . . 9 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 START and STOP conditions . . . . . . . . . . . . . . 9 System configuration . . . . . . . . . . . . . . . . . . . . 9 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 Application design-in information . . . . . . . . . 12 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 13 Thermal characteristics . . . . . . . . . . . . . . . . . 13 Static characteristics. . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Soldering of SMD packages . . . . . . . . . . . . . . 21 Introduction to soldering . . . . . . . . . . . . . . . . . 21 Wave and reflow soldering . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Soldering: PCB footprints. . . . . . . . . . . . . . . . 24 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Contact information. . . . . . . . . . . . . . . . . . . . . 29 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 1 October 2015 Document identifier: PCA9548A