PCA9549

PCA9549 Octal bus switch with individually I2C-bus controlled enables Rev. 02 — 13 July 2009 Product data sheet 1. General description The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlled by the I2C-bus. The low ON-state resistance of the switch allows connections to be made with minimal propagation delay. Any individual A to B channel or combination of channels can be selected via the I2C-bus, determined by the contents of the programmable Control register. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow from Port A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open, creating a high-impedance state between the two ports, which stops the data flow. An active LOW reset input (RESET) allows the PCA9549 to recover from a situation where the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-bus state machine and causes all the bits to be open, as does the internal power-on reset function. Three address pins allow up to eight devices on the same bus. 2. Features I I I I I I I I I I I I I I I 8-bit bus switch (CBT) 5 Ω switch connection between two ports I2C-bus interface logic; compatible with SMBus standards Active LOW RESET input 3 address pins allowing up to 8 devices on the I2C-bus Bit selection via I2C-bus, in any combination Power-up with all bits deselected Low Ron switches No glitch on power-up Supports hot insertion Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO24, TSSOP24, HVQFN24 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 3. Ordering information Table 1. Ordering information Package Name PCA9549D PCA9549PW PCA9549BS SO24 TSSOP24 HVQFN24 Description plastic small outline package; 24 leads; body width 7.5 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 × 4 × 0.85 mm Version SOT137-1 SOT355-1 SOT616-1 Type number 3.1 Ordering options Table 2. PCA9549D PCA9549PW PCA9549BS Ordering options Topside mark PCA9549D PCA9549 9549 Temperature range −40 °C to +85 °C −40 °C to +85 °C −40 °C to +85 °C Type number 4. Block diagram PCA9549 1A 2A 3A 4A 5A 6A 7A 8A 1B 2B 3B 4B 5B 6B 7B 8B VSS VDD RESET SWITCH CONTROL LOGIC RESET CIRCUIT SCL SDA INPUT FILTER I2C-BUS CONTROL A0 A1 A2 002aaa991 Fig 1. PCA9549_2 Block diagram © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 2 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 5. Pinning information 5.1 Pinning A0 A1 RESET 1A 1B 2A 2B 3A 3B 1 2 3 4 5 6 7 8 9 24 VDD 23 SDA 22 SCL 21 A2 20 8A 19 8B 18 7A 17 7B 16 6A 15 6B 14 5A 13 5B 002aaa992 A0 A1 RESET 1A 1B 2A 2B 3A 3B 1 2 3 4 5 6 7 8 9 24 VDD 23 SDA 22 SCL 21 A2 20 8A 19 8B 18 7A 17 7B 16 6A 15 6B 14 5A 13 5B 002aaa993 PCA9549D PCA9549PW 4A 10 4B 11 VSS 12 4A 10 4B 11 VSS 12 Fig 2. Pin configuration of SO24 24 RESET Fig 3. Pin configuration of TSSOP24 20 SDA 23 A1 1A 1B 2A 2B 3A 3B 1 2 3 4 5 6 5B 10 5A 11 6B 12 7 8 9 22 A0 terminal 1 index area 19 SCL 18 A2 17 8A 16 8B 15 7A 14 7B 13 6A 002aaa994 PCA9549BS 4A 4B Transparent top view Fig 4. Pin configuration of HVQFN24 (transparent top view) PCA9549_2 VSS 21 VDD © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 3 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 5.2 Pin description Table 3. Symbol A0 A1 RESET 1A 1B 2A 2B 3A 3B 4A 4B VSS 5B 5A 6B 6A 7B 7A 8B 8A A2 SCL SDA VDD [1] Pin description Pin SO24, TSSOP24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 HVQFN24 22 23 24 1 2 3 4 5 6 7 8 9[1] 10 11 12 13 14 15 16 17 18 19 20 21 address input 0 address input 1 active LOW reset input input output input output input output input output supply ground output input output input output input output input address input 2 serial clock line serial data line supply voltage Description HVQFN24 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 4 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 6. Functional description 6.1 Device addressing Following a START condition, the bus master must output the address of the slave it is accessing. The address of the PCA9549 is shown in Figure 5. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. 1 1 1 0 A2 A1 A0 R/W fixed hardware selectable 002aaa962 Fig 5. Slave address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 6.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9549, which will be stored in the Control register. If multiple bytes are received by the PCA9549, it will save the last byte received. This register can be written and read via the I2C-bus. channel selection bits (read/write) 7 B7 6 B6 5 B5 4 B4 3 B3 2 B2 1 B1 0 B0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 002aab254 Fig 6. Control register 6.2.1 Control register definition One or several bits are selected by the contents of the Control register. This register is written after the PCA9549 has been addressed. The entire control byte is used to determine which bit is to be selected. When a bit is selected to close, the bit will close after the Acknowledge has been placed on the I2C-bus. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 5 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables Table 4. Control register Write = channel selection; read = channel status. B7 X X X X X X X 0 1 [1] B6 X X X X X X 0 1 X B5 X X X X X 0 1 X X B4 X X X X 0 1 X X X B3 X X X 0 1 X X X X B2 X X 0 1 X X X X X B1 X 0 1 X X X X X X B0 0 1 X X X X X X X Command bit 1 disabled bit 1 enabled bit 2 disabled bit 2 enabled bit 3 disabled bit 3 enabled bit 4 disabled bit 4 enabled bit 5 disabled bit 5 enabled bit 6 disabled bit 6 enabled bit 7 disabled bit 7 enabled bit 8 disabled bit 8 enabled Several bits can be enabled at the same time. For example, B7 = 0, B6 = 1, B5 = 0, B4 = 0, B3 = 1, B2 = 1, B1 = 0, B0 = 0, means that bit 8, bit 6, bit 5, bit 2, and bit 1 are disabled and bit 7, bit 4, and bit 3 are enabled. 6.3 RESET input The RESET input is an active LOW signal which may be used to recover from a bus fault condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9549 will reset its registers and I2C-bus state machine and will open all bits. The RESET input must be connected to VDD through a pull-up resistor. 6.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9549 in a reset state until VDD has reached VPOR. At this point, the reset condition is released and the PCA9549 registers and I2C-bus state machine are initialized to their default states, all zeroes causing all the bits to be open (high-impedance state). 6.5 CBT characteristic over VDD range The bus switch is optimized at 5.0 V but can operate over the entire supply range with lower Vo(sw) voltage and higher gate resistance. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 6 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 5.0 Vo(sw) (V) 4.0 (1) 002aaa964 3.0 (2) (3) 2.0 1.0 2.0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 VDD (V) (1) maximum. (2) typical. (3) minimum. Fig 7. Vo(sw) voltage versus VDD Figure 7 shows the voltage characteristics of the pass gate transistors (note that the PCA9549 is only tested at the points specified in Section 9 “Static characteristics”). In order for the PCA9549 to act as a voltage translator, the Vo(sw) voltage should be equal to, or lower than the lowest bus voltage. For example, if the main bus was running at 5 V, and the downstream buses were 3.3 V and 2.7 V, then Vo(sw) should be equal to or below 2.7 V to effectively clamp the downstream bus voltages. Looking at Figure 7, we see that Vo(sw) (maximum) will be at 2.7 V when the PCA9549 supply voltage is 3.5 V or lower so the PCA9549 supply voltage could be set to 3.3 V. Pull-up resistors can then be used to bring the bus voltages to their appropriate levels (see Figure 16). PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 7 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 7. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. 7.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 8). SDA SCL data line stable; data valid change of data allowed mba607 Fig 8. Bit transfer 7.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 9). SDA SCL S START condition P STOP condition mba608 Fig 9. Definition of START and STOP conditions 7.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 10). PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 8 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 10. System configuration 7.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement 002aaa987 9 Fig 11. Acknowledgement on the I2C-bus PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 9 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 7.4 Bus transactions Data is transmitted to the PCA9549 control register using the Write mode as shown in Figure 12. slave address SDA S 1 1 1 0 A2 A1 A0 0 A B7 B6 control register B5 B4 B3 B2 B1 B0 A P START condition R/W acknowledge from slave acknowledge from slave STOP condition 002aac430 Fig 12. Write control register Data is read from the PCA9549 using the Read mode as shown in Figure 13. slave address SDA S 1 1 1 0 A2 A1 A0 1 A B7 B6 control register B5 B4 B3 B2 B1 last byte B0 A P START condition R/W acknowledge from slave no acknowledge from master STOP condition 002aac431 Fig 13. Read control register 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD VI II IO IDD ISS Ptot Tstg Tamb [1] Parameter supply voltage input voltage input current output current supply current ground supply current total power dissipation storage temperature ambient temperature Conditions Min −0.5 −0.5 −20 −25 −100 −100 −60 Max +7.0 +7.0 +20 +25 +100 +100 400 +150 +85 Unit V V mA mA mA mA mW °C °C operating −40 The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 °C. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 10 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 9. Static characteristics Table 6. Static characteristics at VDD = 2.3 V to 3.6 V VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 7 on page 12 for VDD = 4.5 V to 5.5 V[1]. Symbol Supply VDD IDD Istb VPOR VIL VIH IOL IL Ci VIL VIH ILI Ci Pass gate Ron ON-state resistance VDD = 3.0 V to 3.6 V; VO = 0.4 V; IO = 15 mA VDD = 2.3 V to 2.7 V; VO = 0.4 V; IO = 10 mA Vo(sw) switch output voltage Vi(sw) = VDD = 3.3 V; Io(sw) = −100 µA Vi(sw) = VDD = 3.0 V to 3.6 V; Io(sw) = −100 µA Vi(sw) = VDD = 2.5 V; Io(sw) = −100 µA Vi(sw) = VDD = 2.3 V to 2.7 V; Io(sw) = −100 µA IL Cio [1] [2] Parameter supply voltage supply current standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance Conditions Min 2.3 Typ 20 0.1 1.6 6 2 7 8 1.9 1.5 3 Max 3.6 50 1 2.1 +0.3VDD 6 +1 21 +0.3VDD VDD + 0.5 +1 5 12 15 2.8 2.0 +1 5 Unit V µA µA V V V mA mA µA pF V V µA pF Ω Ω V V V V µA pF Operating mode; VDD = 3.6 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 3.6 V; no load; VI = VDD or VSS no load; VI = VDD or VSS [2] −0.5 0.7VDD Input SCL; input/output SDA VOL = 0.4 V VOL = 0.6 V VI = VDD or VSS VI = VSS 3 6 −1 −0.5 0.7VDD Select inputs A0 to A2, RESET pin at VDD or VSS VI = VSS −1 1.6 1.0 −1 - leakage current input/output capacitance VI = VDD or VSS VI = VSS For operation between published voltage ranges, refer to the worst-case parameters in both ranges. VDD must be lowered to 0.2 V in order to reset part. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 11 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables Table 7. Static characteristics at VDD = 4.5 V to 5.5 V VSS = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified. See Table 6 on page 11 for VDD = 2.3 V to 3.6 V[1]. Symbol Supply VDD IDD supply voltage supply current Operating mode; VDD = 5.5 V; no load; VI = VDD or VSS; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VDD or VSS no load; VI = VDD or VSS [2] Parameter Conditions Min 4.5 - Typ 65 Max 5.5 100 Unit V µA Istb VPOR VIL VIH IOL IIL IIH Ci VIL VIH ILI Ci Pass gate Ron Vo(sw) standby current power-on reset voltage LOW-level input voltage HIGH-level input voltage LOW-level output current LOW-level input current HIGH-level input current input capacitance LOW-level input voltage HIGH-level input voltage input leakage current input capacitance ON-state resistance switch output voltage −0.5 0.7VDD 0.6 1.7 6 2 5 3.6 3 2 2.1 +0.3VDD 6 1 1 21 +0.3VDD VDD + 0.5 +50 5 8 4.5 +10 5 µA V V V mA mA µA µA pF V V µA pF Ω V V µA pF Input SCL; input/output SDA VOL = 0.4 V VOL = 0.6 V VI = VSS VI = VSS VI = VSS 3 6 1 1 −0.5 0.7VDD Select inputs A0 to A2, RESET pin at VDD or VSS VI = VSS VDD = 4.5 V to 5.5 V; VO = 0.4 V; IO = 15 mA Vi(sw) = VDD = 5.0 V; Io(sw) = −100 µA Vi(sw) = VDD = 4.5 V to 5.5 V; Io(sw) = −100 µA −1 2.6 −10 - IL Cio [1] [2] leakage current input/output capacitance VI = VDD or VSS VI = VSS For operation between published voltage ranges, refer to the worst-case parameters in both ranges. VDD must be lowered to 0.2 V in order to reset part. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 12 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 10. Dynamic characteristics Table 8. Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min tPD fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tSU;STO tHD;DAT tSU;DAT tr tf Cb tSP tVD;DAT tVD;ACK RESET tw(rst)L trst tREC;STA [1] [2] [3] [4] Fast-mode I2C-bus Unit Min 0 1.3 0.6 1.3 0.6 0.6 0.6 0[3] 100 20 + 0.1Cb[4] 20 + 0.1Cb[4] 4 500 0 Max 0.25[1] ns 400 0.9 300 300 400 50 1 0.6 1 kHz µs µs µs µs µs µs µs ns ns ns pF ns µs µs µs ns ns ns Max 0.25[1] 100 3.45 1000 300 400 50 1 0.6 1 - propagation delay SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition LOW period of the SCL clock HIGH period of the SCL clock set-up time for a repeated START condition set-up time for STOP condition data hold time data set-up time rise time of both SDA and SCL signals fall time of both SDA and SCL signals capacitive load for each bus line pulse width of spikes that must be suppressed by the input filter data valid time data valid acknowledge time LOW-level reset time reset time recovery time to START condition A to B; VDD = 4.5 V to 5.5 V 0 4.7 [2] 4.0 4.7 4.0 4.7 4.0 0[3] 250 - HIGH-to-LOW LOW-to-HIGH 4 SDA clear 500 0 Pass gate propagation delay is calculated from the 6 Ω typical Ron and the 50 pF load capacitance. After this period, the first clock pulse is generated. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 13 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables SDA tBUF tLOW SCL tr tf tHD;STA tSP tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P 002aaa986 Fig 14. Definition of timing on the I2C-bus START SCL ACK or read cycle SDA 70 % trst RESET 50 % trec(rst) 50 % tw(rst)L 50 % 002aac314 Fig 15. Definition of RESET timing PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 14 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 11. Application information VDD = 5.0 V VDD = 5.0 V I2C-bus/SMBus MASTER SDA SCL SDA SCL RESET 1A 1B bit 1 2A 2B bit 2 3A 3B bit 3 PCA9549 4A 4B bit 4 5A 5B bit 5 6A 6B bit 6 7A A2 A1 A0 VSS 8A 8B 7B bit 7 bit 8 002aaa995 Remark: B can also be input and A can also be output as shown in bit 8. Fig 16. Typical application A B C D E SCL SDA RESET A B C D E 002aac279 Fig 17. Custom multiplexer or demultiplexer application PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 15 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables AA AB AC AD BA BB BC BD SCL SDA RESET A B 002aac280 Fig 18. 2 channel 4-to-1 multiplexer or demultiplexer 12. Test information 2VDD VDD PULSE GENERATOR RT RL VO DUT CL 50 pF 002aac315 CL = load capacitance includes jig and probe capacitance. RL = load resistance. RT = termination resistance; should be equal to Zo of pulse generator. Fig 19. Test circuit PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 16 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 13. Package outline SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1 D E A X c y HE vMA Z 24 13 Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) θ A 0 5 scale 10 mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) θ 0.9 0.4 0.012 0.096 0.004 0.089 0.019 0.013 0.014 0.009 0.419 0.043 0.055 0.394 0.016 0.035 0.004 0.016 8 o 0 o Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 20. SO24 package outline (SOT137-1) PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 17 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1 D E A X c y HE vMA Z 24 13 Q A2 pin 1 index A1 (A 3) A θ Lp L 1 e bp 12 wM detail X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 θ 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 21. TSSOP24 package outline (SOT355-1) PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 18 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm SOT616-1 D B A terminal 1 index area A A1 E c detail X e1 1/2 e C b 12 vMCAB wMC 13 e y1 C y e 7 L 6 Eh 1/2 e e2 1 18 terminal 1 index area 24 Dh 0 19 X 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22 Fig 22. HVQFN24 package outline (SOT616-1) PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 19 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 14.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 20 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 9 and 10 Table 9. SnPb eutectic process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 2.5 ≥ 2.5 Table 10. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (°C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 ≥ 350 220 220 Package thickness (mm) Package thickness (mm) Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23. PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 21 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 15. Abbreviations Table 11. Acronym CBT CDM DUT ESD HBM I2C-bus MM PCB SMBus TTL Abbreviations Description Cross Bar Technology Charged-Device Model Device Under Test ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Machine Model Printed-Circuit Board System Management Bus Transistor-Transistor Logic PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 22 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 16. Revision history Table 12. Revision history Release date 20090713 Data sheet status Product data sheet Change notice Supersedes PCA9549_1 Document ID PCA9549_2 Modifications: • • • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 8 “Dynamic characteristics”: – Symbol tf: changed Unit from “µs” to “ns”. – Symbol Cb: changed Unit from “µs” to “pF”. • PCA9549_1 Updated soldering information. Product data sheet - 20060711 PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 23 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 17. Legal information 17.1 Data sheet status Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Please consult the most recently issued document before initiating or completing a design. The term ‘short data sheet’ is explained in section “Definitions”. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9549_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 13 July 2009 24 of 25 NXP Semiconductors PCA9549 Octal bus switch with individually I2C-bus controlled enables 19. Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.3 6.4 6.5 7 7.1 7.1.1 7.2 7.3 7.4 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Device addressing . . . . . . . . . . . . . . . . . . . . . . 5 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 5 Control register definition . . . . . . . . . . . . . . . . . 5 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6 CBT characteristic over VDD range . . . . . . . . . . 6 Characteristics of the I2C-bus. . . . . . . . . . . . . . 8 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 START and STOP conditions . . . . . . . . . . . . . . 8 System configuration . . . . . . . . . . . . . . . . . . . . 8 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Static characteristics. . . . . . . . . . . . . . . . . . . . 11 Dynamic characteristics . . . . . . . . . . . . . . . . . 13 Application information. . . . . . . . . . . . . . . . . . 15 Test information . . . . . . . . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering of SMD packages . . . . . . . . . . . . . . 20 Introduction to soldering . . . . . . . . . . . . . . . . . 20 Wave and reflow soldering . . . . . . . . . . . . . . . 20 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 20 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 23 Legal information. . . . . . . . . . . . . . . . . . . . . . . 24 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Contact information. . . . . . . . . . . . . . . . . . . . . 24 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 July 2009 Document identifier: PCA9549_2