PCA9555A
Low-voltage 16-bit I2C-bus I/O port with interrupt and
weak pull-up
Rev. 1.1 — 6 October 2015
Product data sheet
1. General description
The PCA9555A is a low-voltage 16-bit General Purpose Input/Output (GPIO) expander
with interrupt and weak pull-up resistors for I2C-bus/SMBus applications. NXP I/O
expanders provide a simple solution when additional I/Os are needed while keeping
interconnections to a minimum, for example, in ACPI power switches, sensors, push
buttons, LEDs, fan control, etc.
In addition to providing a flexible set of GPIOs, the wide VDD range of 1.65 V to 5.5 V
allows the PCA9555A to interface with next-generation microprocessors and
microcontrollers where supply levels are dropping down to conserve power.
The PCA9555A contains the PCA9555 register set of four pairs of 8-bit Configuration,
Input, Output, and Polarity Inversion registers.
The PCA9555A is a pin-to-pin replacement to the PCA9555 and other industry-standard
devices. A more fully featured device, the PCAL9555A, is available with Agile I/O
features. See the respective data sheet for more details.
The PCA9555A open-drain interrupt (INT) output is activated when any input state differs
from its corresponding Input Port register state and is used to indicate to the system
master that an input state has changed.
INT can be connected to the interrupt input of a microcontroller. By sending an interrupt
signal on this line, the remote I/O can inform the microcontroller if there is incoming data
on its ports without having to communicate via the I2C-bus. Thus, the PCA9555A can
remain a simple slave device.
The device outputs have 25 mA sink capabilities for directly driving LEDs while consuming
low device current.
The power-on reset sets the registers to their default values and initializes the device state
machine.
All input/output pins have weak pull-up resistors connected to them to eliminate external
components.
Three hardware pins (A0, A1, A2) select the fixed I2C-bus address and allow up to eight
devices to share the same I2C-bus/SMBus.
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
2. Features and benefits
I2C-bus to parallel port expander
Operating power supply voltage range of 1.65 V to 5.5 V
Low standby current consumption:
1.5 A (typical at 5 V VDD)
1.0 A (typical at 3.3 V VDD)
Schmitt-trigger action allows slow input transition and better switching noise immunity
at the SCL and SDA inputs
Vhys = 0.10 VDD (typical)
5 V tolerant I/Os
Open-drain active LOW interrupt output (INT)
400 kHz Fast-mode I2C-bus
Internal power-on reset
Power-up with all channels configured as inputs with weak pull-up resistors
No glitch on power-up
Latched outputs with 25 mA drive maximum capability for directly driving LEDs
Latch-up performance exceeds 100 mA per JESD78, Class II
ESD protection exceeds JESD22
2000 V Human Body Model (A114-A)
1000 V Charged-Device Model (C101)
Packages offered: TSSOP24, HWQFN24
3. Ordering information
Table 1.
Ordering information
Type number
Topside
marking
Package
Name
Description
Version
PCA9555APW
PCA9555A
TSSOP24
plastic thin shrink small outline package; 24 leads;
body width 4.4 mm
SOT355-1
PCA9555AHF
555A
HWQFN24
plastic thermal enhanced very very thin quad flat package;
no leads; 24 terminals; body 4 4 0.75 mm
SOT994-1
3.1 Ordering options
Table 2.
Ordering options
Type number
Orderable
part number
Package
Packing method
PCA9555APW
PCA9555APW,118
TSSOP24
REEL 13" Q1/T1
2500
*STANDARD MARK
SMD
Tamb = 40 C to +85 C
PCA9555AHF
PCA9555AHF,128
HWQFN24
REEL 13" Q2/T3
6000
*STANDARD MARK
SMD
Tamb = 40 C to +85 C
PCA9555A
Product data sheet
Minimum
order quantity
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Rev. 1.1 — 6 October 2015
Temperature
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
4. Block diagram
PCA9555A
P1_0
P1_1
8-bit
A0
P1_2
A1
A2
write pulse
INPUT/
OUTPUT
PORTS
P1_3
P1_4
P1_5
P1_6
read pulse
P1_7
I2C-BUS/SMBus
CONTROL
SCL
P0_0
INPUT
FILTER
SDA
P0_1
8-bit
P0_2
write pulse
INPUT/
OUTPUT
PORTS
P0_3
P0_4
P0_5
P0_6
read pulse
VDD
P0_7
POWER-ON
RESET
VDD
VSS
INT
LP
FILTER
002aaf807
Remark: All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9555A
5. Pinning information
5.1 Pinning
terminal 1
index area
6
19 P1_6
P0_2
3
16 P1_6
P0_3
7
18 P1_5
P0_3
4
15 P1_5
P0_4
8
17 P1_4
P0_4
5
14 P1_4
P0_5
9
16 P1_3
P0_5
6
13 P1_3
P0_6 10
15 P1_2
P0_7 11
14 P1_1
VSS 12
13 P1_0
PCA9555APW
Fig 2.
Product data sheet
Pin configuration for TSSOP24
002aaf806
Transparent top view
Fig 3.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 6 October 2015
P1_2 12
17 P1_7
P0_2
P1_1 11
2
P1_0 10
18 A0
P0_1
9
1
20 P1_7
VSS
P0_0
5
8
21 A0
P0_1
7
22 SCL
4
P0_7
3
P0_6
A2
P0_0
002aaf805
PCA9555A
19 SCL
23 SDA
20 SDA
2
21 VDD
A1
22 INT
24 VDD
24 A2
1
23 A1
PCA9555AHF
INT
Pin configuration for HWQFN24
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
5.2 Pin description
PCA9555A
Product data sheet
Table 3.
Pin description
Symbol
Pin
Type
Description
TSSOP24
HWQFN24
INT
1
22
O
Interrupt output. Connect to VDD through a
pull-up resistor.
A1
2
23
I
Address input 1. Connect directly to VDD or VSS.
A2
3
24
I
Address input 2. Connect directly to VDD or VSS.
P0_0[2]
4
1
I/O
Port 0 input/output 0.
P0_1[2]
5
2
I/O
Port 0 input/output 1.
P0_2[2]
6
3
I/O
Port 0 input/output 2.
P0_3[2]
7
4
I/O
Port 0 input/output 3.
P0_4[2]
8
5
I/O
Port 0 input/output 4.
P0_5[2]
9
6
I/O
Port 0 input/output 5.
P0_6[2]
10
7
I/O
Port 0 input/output 6.
P0_7[2]
11
8
I/O
Port 0 input/output 7.
VSS
12
9[1]
power
Ground.
P1_0[3]
13
10
I/O
Port 1 input/output 0.
P1_1[3]
14
11
I/O
Port 1 input/output 1.
P1_2[3]
15
12
I/O
Port 1 input/output 2.
P1_3[3]
16
13
I/O
Port 1 input/output 3.
P1_4[3]
17
14
I/O
Port 1 input/output 4.
P1_5[3]
18
15
I/O
Port 1 input/output 5.
P1_6[3]
19
16
I/O
Port 1 input/output 6.
P1_7[3]
20
17
I/O
Port 1 input/output 7.
A0
21
18
I
Address input 0. Connect directly to VDD or VSS.
SCL
22
19
I
Serial clock bus. Connect to VDD through a
pull-up resistor.
SDA
23
20
I/O
Serial data bus. Connect to VDD through a
pull-up resistor.
VDD
24
21
power
Supply voltage.
[1]
HWQFN24 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
[2]
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
[3]
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
6. Functional description
Refer to Figure 1 “Block diagram of PCA9555A”.
6.1 Device address
slave address
0
1
0
0
fixed
A2
A1
A0 R/W
hardware
selectable
002aaf819
Fig 4.
PCA9555A device address
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
6.2 Registers
6.2.1 Pointer register and command byte
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCA9555A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. This register is
write only.
B7
B6
B5
B4
B3
B2
B1
B0
002aaf540
Fig 5.
Table 4.
Pointer register bits
Command byte
Pointer register bits
Command byte Register
(hexadecimal)
Protocol
Power-up
default
Input port 0
read byte
xxxx xxxx[1]
01h
Input port 1
read byte
xxxx xxxx
0
02h
Output port 0
read/write byte
1111 1111
1
03h
Output port 1
read/write byte
1111 1111
0
0
04h
Polarity Inversion port 0
read/write byte
0000 0000
1
0
1
05h
Polarity Inversion port 1
read/write byte
0000 0000
0
1
1
0
06h
Configuration port 0
read/write byte
1111 1111
0
1
1
1
07h
Configuration port 1
read/write byte
1111 1111
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
0
0
0
0
00h
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
[1]
Undefined.
PCA9555A
Product data sheet
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
6.2.2 Input port register pair (00h, 01h)
The Input port registers (registers 0 and 1) reflect the incoming logic levels of the pins,
regardless of whether the pin is defined as an input or an output by the Configuration
register. The Input port registers are read only; writes to these registers have no effect.
The default value ‘X’ is determined by the externally applied logic level. An Input port
register read operation is performed as described in Section 7.2 “Reading the port
registers”.
Table 5.
Bit
Input port 0 register (address 00h)
7
6
5
4
3
2
1
0
Symbol
I0.7
I0.6
I0.5
I0.4
I0.3
I0.2
I0.1
I0.0
Default
X
X
X
X
X
X
X
X
Table 6.
Bit
Input port 1 register (address 01h)
7
6
5
4
3
2
1
0
Symbol
I1.7
I1.6
I1.5
I1.4
I1.3
I1.2
I1.1
I1.0
Default
X
X
X
X
X
X
X
X
6.2.3 Output port register pair (02h, 03h)
The Output port registers (registers 2 and 3) show the outgoing logic levels of the pins
defined as outputs by the Configuration register. Bit values in these registers have no
effect on pins defined as inputs. In turn, reads from these registers reflect the value that
was written to these registers, not the actual pin value. A register pair write is described in
Section 7.1 and a register pair read is described in Section 7.2.
Table 7.
Bit
7
6
5
4
3
2
1
0
Symbol
O0.7
O0.6
O0.5
O0.4
O0.3
O0.2
O0.1
O0.0
Default
1
1
1
1
1
1
1
1
Table 8.
Bit
PCA9555A
Product data sheet
Output port 0 register (address 02h)
Output port 1 register (address 03h)
7
6
5
4
3
2
1
0
Symbol
O1.7
O1.6
O1.5
O1.4
O1.3
O1.2
O1.1
O1.0
Default
1
1
1
1
1
1
1
1
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
6.2.4 Polarity inversion register pair (04h, 05h)
The Polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined
as inputs by the Configuration register. If a bit in these registers is set (written with ‘1’), the
corresponding port pin’s polarity is inverted in the Input register. If a bit in this register is
cleared (written with a ‘0’), the corresponding port pin’s polarity is retained. A register pair
write is described in Section 7.1 and a register pair read is described in Section 7.2.
Table 9.
Bit
Polarity inversion port 0 register (address 04h)
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 10.
Bit
Polarity inversion port 1 register (address 05h)
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
6.2.5 Configuration register pair (06h, 07h)
The Configuration registers (registers 6 and 7) configure the direction of the I/O pins. If a
bit in these registers is set to 1, the corresponding port pin is enabled as a
high-impedance input. If a bit in these registers is cleared to 0, the corresponding port pin
is enabled as an output. A register pair write is described in Section 7.1 and a register pair
read is described in Section 7.2.
Table 11.
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 12.
Bit
PCA9555A
Product data sheet
Configuration port 0 register (address 06h)
Configuration port 1 register (address 07h)
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
6.3 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above VDD to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either VDD or VSS. The external voltage applied to this I/O pin should not exceed the
recommended levels for proper operation.
data from
shift register
output port
register data
configuration
register
data from
shift register
D
VDD
Q1
Q
FF
write configuration
pulse
CK
100 kΩ
Q
D
Q
FF
write pulse
P0_0 to P0_7
P1_0 to P1_7
CK
Q2
output port
register
input port
register
D
Q
FF
read pulse
CK
VSS
input port
register data
to INT
polarity inversion
register
data from
shift register
D
Q
polarity inversion
register data
FF
write polarity
pulse
CK
002aah328
At power-on reset, all registers return to default values.
Fig 6.
Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
PCA9555A
Product data sheet
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
6.4 Power-on reset
When power (from 0 V) is applied to VDD, an internal power-on reset holds the PCA9555A
in a reset condition until VDD has reached VPOR. At that time, the reset condition is
released and the PCA9555A registers and I2C-bus/SMBus state machine initializes to
their default states. After that, VDD must be lowered to below VPORF and back up to the
operating voltage for a power-reset cycle. See Section 8.2 “Power-on reset requirements”.
6.5 Interrupt output
An interrupt is generated by any rising or falling edge of the port inputs in the Input mode.
After time tv(INT), the signal INT is valid. The interrupt is reset when data on the port
changes back to the original value or when data is read form the port that generated the
interrupt (see Figure 10 and Figure 11). Resetting occurs in the Read mode at the
acknowledge (ACK) or not acknowledge (NACK) bit after the rising edge of the SCL
signal. Interrupts that occur during the ACK or NACK clock pulse can be lost (or be very
short) due to the resetting of the interrupt during this pulse. Any change of the I/Os after
resetting is detected and is transmitted as INT.
A pin configured as an output cannot cause an interrupt. Changing an I/O from an output
to an input may cause a false interrupt to occur, if the state of the pin does not match the
contents of the Input Port register.
7. Bus transactions
The PCA9555A is an I2C-bus slave device. Data is exchanged between the master and
PCA9555A through write and read commands using I2C-bus. The two communication
lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Writing to the port registers
Data is transmitted to the PCA9555A by sending the device address and setting the least
significant bit to a logic 0 (see Figure 4 “PCA9555A device address”). The command byte
is sent after the address and determines which register will receive the data following the
command byte.
Eight registers within the PCA9555A are configured to operate as four register pairs. The
four pairs are input port, output port, polarity inversion, configuration registers. After
sending data to one register, the next data byte is sent to the other register in the pair (see
Figure 7 and Figure 8). For example, if the first byte is sent to Output Port 1 (register 3),
the next byte is stored in Output Port 0 (register 2).
There is no limitation on the number of data bytes sent in one write transmission. In this
way, the host can continuously update a register pair independently of the other registers,
or the host can simply update a single register.
PCA9555A
Product data sheet
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Rev. 1.1 — 6 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
2
3
4
5
6
7
8
9
slave address
SDA S
0
1
0
data to port 0
command byte
0 A2 A1 A0 0
START condition
R/W
NXP Semiconductors
PCA9555A
Product data sheet
1
SCL
A
0
0
0
0
0
0
1
0
acknowledge
from slave
A 0.7
data to port 1
0.0 A 1.7
DATA 0
acknowledge
from slave
DATA 1
1.0 A
P
STOP
condition
acknowledge
from slave
write to port
tv(Q)
data out
from port 1
DATA VALID
002aah344
Fig 7.
Write to output port registers
SCL
1
2
3
4
5
6
7
8
9
slave address
0
1
0
0 A2 A1 A0 0
START condition
R/W
A
0 0/1 0
acknowledge
from slave
0 0/1 0/1 0/1 0/1 A
MSB
acknowledge
from slave
STOP
condition
data to register
DATA 0
A
LSB
MSB
acknowledge
from slave
DATA 1
A
P
LSB
acknowledge
from slave
002aah345
Fig 8.
Write to Control registers
PCA9555A
10 of 39
© NXP Semiconductors N.V. 2015. All rights reserved.
SDA S
data to register
command byte
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Rev. 1.1 — 6 October 2015
All information provided in this document is subject to legal disclaimers.
tv(Q)
data out
from port 0
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
7.2 Reading the port registers
In order to read data from the PCA9555A, the bus master must first send the PCA9555A
address with the least significant bit set to a logic 0 (see Figure 4 “PCA9555A device
address”). The command byte is sent after the address and determines which register will
be accessed. After a restart, the device address is sent again, but this time the least
significant bit is set to a logic 1. Data from the register defined by the command byte is
sent by the PCA9555A (see Figure 9, Figure 10 and Figure 11). Data is clocked into the
register on the falling edge of the acknowledge clock pulse. After the first byte is read,
additional bytes may be read but the data now reflects the information in the other register
in the pair. For example, if Input Port 1 is read, the next byte read is Input Port 0. There is
no limit on the number of data bytes received in one read transmission, but on the final
byte received the bus master must not acknowledge the data.
After a subsequent restart, the command byte contains the value of the next register to be
read in the pair. For example, if Input Port 1 was read last before the restart, the register
that is read after the restart is the Input Port 0.
command byte
slave address
SDA S
0
1
0
0 A2 A1 A0 0
START condition
A
0 0/1 0
R/W
data from lower or
upper byte of register
slave address
0
1
0
MSB
0 A2 A1 A0 1
(repeated)
START condition
(cont.)
acknowledge
from slave
acknowledge
from slave
(cont.) S
0 0/1 0/1 0/1 0/1 A
A
data from upper or
lower byte of register
LSB
DATA (first byte)
R/W
acknowledge
from slave
MSB
A
acknowledge
from master
LSB
DATA (last byte)
NA P
no acknowledge
from master
at this moment master-transmitter becomes master-receiver
and slave-receiver becomes slave-transmitter
STOP
condition
002aah346
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 9.
Read from register
PCA9555A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 6 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 39
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NXP Semiconductors
PCA9555A
Product data sheet
data into port 0
data into port 1
tv(INT)
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
0
1
0
7
8
0 A2 A1 A0 1
START condition
9
R/W
I0.x
A
7
6
5
acknowledge
from slave
4
3
I1.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
I0.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
STOP condition
I1.x
2
1
0
A
acknowledge
from master
7
6
5
4
3
2
1
0
1
P
non acknowledge
from master
read from port 0
read from port 1
002aah347
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Figure 9).
Fig 10. Read input port register, scenario 1
PCA9555A
12 of 39
© NXP Semiconductors N.V. 2015. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Rev. 1.1 — 6 October 2015
All information provided in this document is subject to legal disclaimers.
INT
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DATA 00
DATA 01
DATA 02
DATA 03
tsu(D)
th(D)
data into port 1
NXP Semiconductors
PCA9555A
Product data sheet
data into port 0
DATA 10
DATA 11
DATA 12
tsu(D)
th(D)
INT
SCL
1
2
3
4
trst(INT)
5
6
slave address
SDA S
0
1
0
7
8
R/W
0 A2 A1 A0 1
START condition
9
I0.x
A
acknowledge
from slave
DATA 00
I1.x
A
acknowledge
from master
DATA 10
I0.x
A
acknowledge
from master
DATA 03
I1.x
A
acknowledge
from master
STOP condition
DATA 12
1
P
non acknowledge
from master
read from port 0
read from port 1
002aah348
This figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data transfer from P port (see Figure 9).
Fig 11. Read input port register, scenario 2
PCA9555A
13 of 39
© NXP Semiconductors N.V. 2015. All rights reserved.
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It
is assumed that the command byte has previously been set to ‘00’ (read input port register).
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Rev. 1.1 — 6 October 2015
All information provided in this document is subject to legal disclaimers.
tv(INT)
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
8. Application design-in information
VDD
(3.3 V)
10 kΩ
10 kΩ
10 kΩ
2 kΩ
VDD
VDD
MASTER
CONTROLLER
PCA9555A
SUB-SYSTEM 1(1)
(e.g., temp sensor)
100 kΩ
(×3)
INT
SCL
SCL
P0_0
SDA
SDA
P0_1
INT
INT
SUB-SYSTEM 2
(e.g., counter)
P0_2
RESET
P0_3
VSS
A
P0_4
controlled
switch
(e.g., CBT device)
enable
P0_5
B
P0_6
P0_7
P1_0
P1_1
P1_2
P1_3
P1_4
P1_5
P1_6
P1_7
A2
A1
A0
SUB-SYSTEM 3(1)
(e.g., alarm system)
10 DIGIT
NUMERIC
KEYPAD
ALARM
VDD
VSS
002aaf847
Device address configured as 0100 000X for this example.
P0_0, P0_2, P0_3 configured as outputs.
P0_1, P0_4, P0_5 configured as inputs.
P0_6, P0_7 and (P1_0 to P1_7) configured as inputs.
(1) Internal pull-up may be used to eliminate external components.
Fig 12. Typical application
8.1 Minimizing IDD when the I/Os are used to control LEDs
When the I/Os are used to control LEDs, they are normally connected to VDD through a
resistor as shown in Figure 12. Since the LED acts as a diode, when the LED is off the I/O
VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower
than VDD.
Designs needing to minimize current consumption, such as battery power applications,
should consider maintaining the I/O pins greater than or equal to VDD when the LED is off.
Figure 13 shows a high value resistor in parallel with the LED. Figure 14 shows VDD less
than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI
at or above VDD and prevents additional supply current consumption when the LED is off.
PCA9555A
Product data sheet
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Rev. 1.1 — 6 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
3.3 V
VDD
VDD
LED
5V
VDD
100 kΩ
LED
Pn
Pn
002aag164
002aag165
Fig 13. High value resistor in parallel with
the LED
Fig 14. Device supplied by a lower voltage
8.2 Power-on reset requirements
In the event of a glitch or data corruption, PCA9555A can be reset to its default conditions
by using the power-on reset feature. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
The two types of power-on reset are shown in Figure 15 and Figure 16.
VDD
ramp-up
ramp-down
re-ramp-up
td(rst)
time
(dV/dt)r
(dV/dt)f
time to re-ramp
when VDD drops
below 0.2 V or to VSS
(dV/dt)r
002aah329
Fig 15. VDD is lowered below 0.2 V or to 0 V and then ramped up to VDD
VDD
ramp-down
ramp-up
td(rst)
VI drops below POR levels
(dV/dt)f
time to re-ramp
when VDD drops
to VPOR(min) − 50 mV
time
(dV/dt)r
002aah330
Fig 16. VDD is lowered below the POR threshold, then ramped back up to VDD
Table 13 specifies the performance of the power-on reset feature for PCA9555A for both
types of power-on reset.
PCA9555A
Product data sheet
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Rev. 1.1 — 6 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 39
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Table 13. Recommended supply sequencing and ramp rates
Tamb = 25 C (unless otherwise noted). Not tested; specified by design.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
(dV/dt)f
fall rate of change of voltage
Figure 15
0.1
-
2000
ms
(dV/dt)r
rise rate of change of voltage
Figure 15
0.1
-
2000
ms
td(rst)
reset delay time
Figure 15; re-ramp time when
VDD drops below 0.2 V or to VSS
1
-
-
s
Figure 16; re-ramp time when
VDD drops to VPOR(min) 50 mV
1
-
-
s
VDD(gl)
glitch supply voltage difference
Figure 17
[1]
-
-
1
V
[2]
-
-
10
s
tw(gl)VDD
supply voltage glitch pulse width
Figure 17
VPOR(trip)
power-on reset trip voltage
falling VDD
0.7
-
-
V
rising VDD
-
-
1.4
V
[1]
Level that VDD can glitch down to with a ramp rate of 0.4 s/V, but not cause a functional disruption when tw(gl)VDD < 1 s.
[2]
Glitch width that will not cause a functional disruption when VDD(gl) = 0.5 VDD.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other. The bypass capacitance, source impedance, and device impedance are factors that
affect power-on reset performance. Figure 17 and Table 13 provide more information on
how to measure these specifications.
VDD
∆VDD(gl)
tw(gl)VDD
time
002aah331
Fig 17. Glitch width and glitch height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition
is released and all the registers and the I2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD being lowered to or from
0 V. Figure 18 and Table 13 provide more details on this specification.
VDD
VPOR (rising VDD)
VPOR (falling VDD)
time
POR
time
002aah332
Fig 18. Power-on reset voltage (VPOR)
PCA9555A
Product data sheet
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16 of 39
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
8.3 Device current consumption with internal pull-up and pull-down
resistors
The PCA9555A integrates pull-up resistors to eliminate external components when pins
are configured as inputs and pull-up resistors are required (for example, nothing is driving
the inputs to the power supply rails. Since these pull-up resistors are internal to the device
itself, they contribute to the current consumption of the device and must be considered in
the overall system design.
If the resistor is configured as a pull-up, that is, connected to VDD, a current will flow from
the VDD pin through the resistor to ground when the pin is held LOW. This current will
appear as additional IDD upsetting any current consumption measurements.
The pull-up resistors are simple resistors and the current is linear with voltage. The
resistance specification for these devices spans from 50 k with a nominal 100 k value.
Any current flow through these resistors is additive by the number of pins held LOW and
the current can be calculated by Ohm’s law. See Figure 22 for a graph of supply current
versus the number of pull-up resistors.
PCA9555A
Product data sheet
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Rev. 1.1 — 6 October 2015
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
9. Limiting values
Table 14. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
VDD
supply voltage
Conditions
Min
Max
Unit
0.5
+6.5
V
0.5
+6.5
V
0.5
+6.5
V
VI
input voltage
[1]
VO
output voltage
[1]
IIK
input clamping current
A0, A1, A2, SCL; VI < 0 V
-
20
mA
IOK
output clamping current
INT; VO < 0 V
-
20
mA
IIOK
input/output clamping current
P port; VO < 0 V or VO > VDD
-
20
mA
SDA; VO < 0 V or VO > VDD
-
20
mA
continuous; I/O port
-
50
mA
continuous; SDA, INT
-
25
mA
continuous; P port
LOW-level output current
IOL
IOH
HIGH-level output current
-
25
mA
IDD
supply current
-
160
mA
ISS
ground supply current
-
200
mA
Ptot
total power dissipation
-
200
mW
Tstg
storage temperature
65
+150
C
Tj(max)
maximum junction temperature
-
125
C
[1]
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
10. Recommended operating conditions
Table 15.
Operating conditions
Symbol
Parameter
VDD
supply voltage
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
Conditions
Min
Max
Unit
1.65
5.5
V
SCL, SDA
0.7 VDD
5.5
V
A0, A1, A2, P1_7 to P0_0
0.7 VDD
5.5
V
SCL, SDA
0.5
0.3 VDD
V
A0, A1, A2, P1_7 to P0_0
0.5
0.3 VDD
V
P1_7 to P0_0
-
10
mA
IOH
HIGH-level output current
IOL
LOW-level output current
P1_7 to P0_0
-
25
mA
Tamb
ambient temperature
operating in free air
40
+85
C
11. Thermal characteristics
Table 16.
Symbol
Zth(j-a)
[1]
Thermal characteristics
Parameter
Conditions
transient thermal impedance from junction to ambient
Max
Unit
TSSOP24 package
[1]
88
K/W
HWQFN24 package
[1]
66
K/W
The package thermal impedance is calculated in accordance with JESD 51-7.
PCA9555A
Product data sheet
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Rev. 1.1 — 6 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
12. Static characteristics
Table 17. Static characteristics
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ[1]
Max
Unit
VIK
input clamping voltage
II = 18 mA
1.2
-
-
V
VPOR
power-on reset voltage
VI = VDD or VSS; IO = 0 mA
-
1.1
1.4
V
IOL
LOW-level output current
VOL = 0.4 V; VDD = 1.65 V to 5.5 V
3
-
-
mA
3
15[2]
-
mA
SDA
INT
P port
VOH
VOL
II
HIGH-level output voltage
LOW-level output voltage
input current
VOL = 0.5 V; VDD = 1.65 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD = 1.65 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD = 2.3 V
[3]
8
10
-
mA
VOL = 0.7 V; VDD = 2.3 V
[3]
10
13
-
mA
VOL = 0.5 V; VDD = 3.0 V
[3]
8
14
-
mA
VOL = 0.7 V; VDD = 3.0 V
[3]
10
19
-
mA
VOL = 0.5 V; VDD = 4.5 V
[3]
8
17
-
mA
VOL = 0.7 V; VDD = 4.5 V
[3]
10
24
-
mA
IOH = 8 mA; VDD = 1.65 V
[4]
1.2
-
-
V
IOH = 10 mA; VDD = 1.65 V
[4]
1.1
-
-
V
IOH = 8 mA; VDD = 2.3 V
[4]
1.8
-
-
V
IOH = 10 mA; VDD = 2.3 V
[4]
1.7
-
-
V
IOH = 8 mA; VDD = 3.0 V
[4]
2.6
-
-
V
IOH = 10 mA; VDD = 3.0 V
[4]
2.5
-
-
V
IOH = 8 mA; VDD = 4.5 V
[4]
4.1
-
-
V
IOH = 10 mA; VDD = 4.5 V
[4]
4.0
-
-
V
VDD = 1.65 V
-
-
0.45
V
VDD = 2.3 V
-
-
0.25
V
VDD = 3.0 V
-
-
0.25
V
VDD = 4.5 V
-
-
0.2
V
SCL, SDA, RESET; VI = VDD or VSS
-
-
1
A
A0, A1, A2; VI = VDD or VSS
-
-
1
A
P port
P port; IOL = 8 mA
VDD = 1.65 V to 5.5 V
IIH
HIGH-level input current
P port; VI = VDD; VDD = 1.65 V to 5.5 V
-
-
1
A
IIL
LOW-level input current
P port; VI = VSS; VDD = 1.65 V to 5.5 V
-
-
100
A
PCA9555A
Product data sheet
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Table 17. Static characteristics …continued
Tamb = 40 C to +85 C; VDD = 1.65 V to 5.5 V; unless otherwise specified.
Min
Typ[1]
Max
Unit
VDD = 3.6 V to 5.5 V
-
10
25
A
VDD = 2.3 V to 3.6 V
-
6.5
15
A
VDD = 1.65 V to 2.3 V
-
4
9
A
VDD = 3.6 V to 5.5 V
-
1.5
7
A
VDD = 2.3 V to 3.6 V
-
1
3.2
A
VDD = 1.65 V to 2.3 V
-
0.5
1.7
A
Symbol
Parameter
Conditions
IDD
supply current
SDA, P port, A0, A1, A2;
VI on SDA = VDD or VSS;
VI on P port and A0, A1, A2 = VDD;
IO = 0 mA; I/O = inputs; fSCL = 400 kHz
SCL, SDA, P port, A0, A1, A2;
VI on SCL, SDA = VDD or VSS;
VI on P port and A0, A1, A2 = VDD;
IO = 0 mA; I/O = inputs; fSCL = 0 kHz
Active mode; P port, A0, A1, A2;
VI on P port, A0, A1, A2 = VDD;
IO = 0 mA; I/O = inputs;
fSCL = 400 kHz, continuous register read
VDD = 3.6 V to 5.5 V
-
60
125
A
VDD = 2.3 V to 3.6 V
-
40
75
A
VDD = 1.65 V to 2.3 V
-
20
45
A
-
1.1
1.5
mA
SCL, SDA; one input at VDD 0.6 V, other
inputs at VDD or VSS; VDD = 1.65 V to 5.5 V
-
-
25
A
P port, A0, A1, A2; one input at VDD 0.6 V,
other inputs at VDD or VSS;
VDD = 1.65 V to 5.5 V
-
-
80
A
-
6
7
pF
with pull-ups enabled; P port, A0, A1, A2;
VI on SCL and SDA = VDD or VSS;
VI on P port = VSS;
VI on A0, A1, A2 = VDD or VSS;
IO = 0 mA; I/O = inputs with pull-up enabled;
fSCL = 0 kHz
VDD = 1.65 V to 5.5 V
IDD
additional quiescent
supply current
Ci
input capacitance
VI = VDD or VSS; VDD = 1.65 V to 5.5 V
Cio
input/output capacitance
VI/O = VDD or VSS; VD = 1.65 V to 5.5 V
-
7
8
pF
VI/O = VDD or VSS; VDD = 1.65 V to 5.5 V
-
7.5
8.5
pF
[1]
For IDD, all typical values are at nominal supply voltage (1.8 V, 2.5 V, 3.3 V, 3.6 V or 5 V VDD) and Tamb = 25 C. Except for IDD, the
typical values are at VDD = 3.3 V and Tamb = 25 C.
[2]
Typical value for Tamb = 25 C. VOL = 0.4 V and VDD = 3.3 V. Typical value for VDD < 2.5 V, VOL = 0.6 V.
[3]
Each I/O must be externally limited to a maximum of 25 mA and the device must be limited to a maximum current of 200 mA.
[4]
The total current sourced by all I/Os must be limited to 160 mA.
PCA9555A
Product data sheet
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
12.1 Typical characteristics
002aah333
20
IDD
(μA)
16
12
002aah334
1400
IDD(stb)
(nA)
VDD = 5.5 V
5.0 V
3.6 V
3.3 V
2.5 V
2.3 V
VDD = 5.5 V
5.0 V
3.6 V
3.3 V
1000
800
600
8
400
2.5 V
2.3 V
1.8 V
1.65 V
4
0
−40
200
VDD = 1.8 V
1.65 V
−15
10
35
0
−40
60
85
Tamb (°C)
Fig 19. Supply current versus ambient temperature
002aah335
20
IDD
(μA)
16
−15
10
35
60
85
Tamb (°C)
Fig 20. Standby supply current versus
ambient temperature
002aah336
1.2
Tamb = −40 °C
25 °C
85 °C
IDD
(mA)
0.8
12
8
0.4
4
0
1.5
0
2.5
3.5
4.5
5.5
0
VDD (V)
4
8
12
16
number of I/O held LOW
Tamb = 25 C
Fig 21. Supply current versus supply voltage
PCA9555A
Product data sheet
Fig 22. Supply current versus number of I/O held LOW
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Isink
(mA)
002aaf578
35
Isink
(mA)
30
Tamb = −40 °C
25 °C
85 °C
25
002aaf579
35
30
Tamb = −40 °C
25 °C
85 °C
25
20
20
15
15
10
10
5
5
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
a. VDD = 1.65 V
Isink
(mA)
b. VDD = 1.8 V
002aaf580
50
002aaf581
60
Isink
(mA)
40
Tamb = −40 °C
25 °C
85 °C
30
0.3
VOL (V)
Tamb = −40 °C
25 °C
85 °C
40
20
20
10
0
0
0
0.1
0.2
0.3
0
0.1
0.2
VOL (V)
c. VDD = 2.5 V
Isink
(mA)
0.3
VOL (V)
d. VDD = 3.3 V
002aaf582
70
Isink
(mA)
Tamb = −40 °C
25 °C
85 °C
60
50
002aaf583
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
40
30
30
20
20
10
10
0
0
0
0.1
0.2
0.3
0
VOL (V)
0.1
0.2
0.3
VOL (V)
e. VDD = 5.0 V
f. VDD = 5.5 V
Fig 23. I/O sink current versus LOW-level output voltage
PCA9555A
Product data sheet
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© NXP Semiconductors N.V. 2015. All rights reserved.
22 of 39
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
002aah337
30
Isource
(mA)
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
20
002aah338
35
Tamb = −40 °C
25 °C
85 °C
30
25
20
15
10
10
5
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
0
a. VDD = 1.65 V
002aah339
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
40
0.4
0.6
VDD − VOH (V)
b. VDD = 1.8 V
60
Isource
(mA)
0.2
002aah340
70
Tamb = −40 °C
25 °C
85 °C
60
50
40
30
20
20
10
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
c. VDD = 2.5 V
002aah341
0.4
0.6
VDD − VOH (V)
002aah342
90
Isource
(mA)
Tamb = −40 °C
25 °C
85 °C
60
0.2
d. VDD = 3.3 V
90
Isource
(mA)
0
Tamb = −40 °C
25 °C
85 °C
60
30
30
0
0
0
0.2
0.4
0.6
VDD − VOH (V)
e. VDD = 5.0 V
0
0.2
0.4
0.6
VDD − VOH (V)
f. VDD = 5.5 V
Fig 24. I/O source current versus HIGH-level output voltage
PCA9555A
Product data sheet
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
VOL
(mV)
002aah056
120
100
002aah343
200
VDD − VOH (mV)
160
(1)
80
120
VDD = 1.8 V
5V
60
(2)
80
40
(4)
20
0
−40
40
(3)
−15
10
35
60
85
Tamb (°C)
0
−40
−15
10
35
60
85
Tamb (°C)
Isource = 10 mA
(1) VDD = 1.8 V; Isink = 10 mA
(2) VDD = 5 V; Isink = 10 mA
(3) VDD = 1.8 V; Isink = 1 mA
(4) VDD = 5 V; Isink = 1 mA
Fig 25. LOW-level output voltage versus temperature
PCA9555A
Product data sheet
Fig 26. I/O high voltage versus temperature
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
13. Dynamic characteristics
Table 18. I2C-bus interface timing requirements
Over recommended operating free air temperature range, unless otherwise specified. See Figure 27.
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
tHIGH
HIGH period of the SCL clock
4
-
0.6
-
s
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tSP
pulse width of spikes that must
be suppressed by the input filter
0
50
0
50
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
-
ns
kHz
tr
rise time of both SDA and SCL signals
-
1000
20
300
ns
tf
fall time of both SDA and SCL signals
-
300
20
(VDD / 5.5 V)
300
ns
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tHD;STA
hold time (repeated) START condition
4
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4
-
0.6
-
s
tVD;DAT
data valid time
SCL LOW to SDA
output valid
-
3.45
-
0.9
s
tVD;ACK
data valid acknowledge time
ACK signal from
SCL LOW to SDA
(out) LOW
-
3.45
-
0.9
s
Table 19. Switching characteristics
Over recommended operating free air temperature range; CL 100 pF; unless otherwise specified. See Figure 28.
Symbol
Parameter
Conditions
Fast-mode
I2C-bus
Min
Max
Min
Max
-
1
-
1
Unit
s
tv(INT)
valid time on pin INT
trst(INT)
reset time on pin INT
from SCL to INT
-
1
-
1
s
tv(Q)
data output valid time
from SCL to P port
-
400
-
400
ns
tsu(D)
data input set-up time
from P port to SCL
0
-
0
-
ns
th(D)
data input hold time
from P port to SCL
300
-
300
-
ns
PCA9555A
Product data sheet
from P port to INT
Standard-mode
I2C-bus
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
14. Parameter measurement information
VDD
RL = 1 kΩ
DUT
SDA
CL = 50 pF
002aaf848
a. SDA load configuration
two bytes for read Input port register(1)
STOP
START
condition condition
(P)
(S)
Address
Bit 7
(MSB)
Address
Bit 1
R/W
Bit 0
(LSB)
Data
Bit 7
(MSB)
ACK
(A)
Data
Bit 0
(LSB)
STOP
condition
(P)
002aag952
b. Transaction format
tHIGH
tLOW
tSP
0.7 × VDD
0.3 × VDD
SCL
tBUF
tVD;DAT
tr
tf
tf(o)
tVD;ACK
tSU;STA
0.7 × VDD
SDA
tf
tHD;STA
tr
0.3 × VDD
tVD;ACK
tSU;DAT
tSU;STO
tHD;DAT
repeat START condition
STOP condition
002aag804
c. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Byte 1 = I2C-bus address; Byte 2, byte 3 = P port data.
(1) See Figure 9.
Fig 27. I2C-bus interface load circuit and voltage waveforms
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
VDD
RL = 4.7 kΩ
INT
DUT
CL = 100 pF
002aah069
a. Interrupt load configuration
acknowledge
from slave
START condition
R/W
8 bits (one data byte)
from port
slave address
SDA S
SCL
0
1
0
1
2
3
0 A2 A1 A0 1
4
5
6
7
8
acknowledge
from slave
DATA 1
A
no acknowledge
from master
STOP
condition
data from port
A
DATA 2
1
P
9
B
trst(INT) B
trst(INT)
INT
tv(INT)
data into
port
A
A
tsu(D)
ADDRESS
INT
DATA 1
SCL
0.5 × VDD
DATA 2
R/W
0.3 × VDD
tv(INT)
trst(INT)
0.5 × VDD
Pn
0.7 × VDD
A
0.5 × VDD
INT
View A - A
View B - B
002aah256
b. Voltage waveforms
CL includes probe and jig capacitance.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
All parameters and waveforms are not applicable to all devices.
Fig 28. Interrupt load circuit and voltage waveforms
PCA9555A
Product data sheet
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
500 Ω
Pn
DUT
2 × VDD
CL = 50 pF
500 Ω
002aag805
a. P port load configuration
SCL
P0
A
P7
0.7 × VDD
0.3 × VDD
SDA
tv(Q)
Pn
unstable
data
last stable bit
A
P7
002aag806
b. Write mode (R/W = 0)
SCL
P0
0.7 × VDD
0.3 × VDD
tsu(D)
th(D)
Pn
002aag807
c. Read mode (R/W = 1)
CL includes probe and jig capacitance.
tv(Q) is measured from 0.7 VDD on SCL to 50 % I/O (Pn) output.
All inputs are supplied by generators having the following characteristics: PRR 10 MHz; Zo = 50 ; tr/tf 30 ns.
The outputs are measured one at a time, with one transition per measurement.
All parameters and waveforms are not applicable to all devices.
Fig 29. P port load circuit and voltage waveforms
PCA9555A
Product data sheet
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
15. Package outline
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
D
SOT355-1
E
A
X
c
HE
y
v M A
Z
13
24
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT355-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Fig 30. Package outline SOT355-1 (TSSOP24)
PCA9555A
Product data sheet
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PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.75 mm
B
D
SOT994-1
A
terminal 1
index area
E
A
A1
c
detail X
e1
1/2 e
∅v
∅w
b
e
7
12
M
M
C
C A B
C
y1 C
y
L
13
6
e
e2
Eh
1/2 e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
b
c
D(1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
0.8
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.25
1.95
4.1
3.9
2.25
1.95
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT994-1
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
07-02-07
07-03-03
Fig 31. Package outline SOT994-1 (HWQFN24)
PCA9555A
Product data sheet
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
16. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling ensure that the appropriate precautions are taken as
described in JESD625-A or equivalent standards.
17. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
PCA9555A
Product data sheet
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 20 and 21
Table 20.
SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350
< 2.5
235
220
2.5
220
220
Table 21.
Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 32.
PCA9555A
Product data sheet
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PCA9555A
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
PCA9555A
Product data sheet
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
18. Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP24 package
SOT355-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
8.200
5.300
8.600
7.450
sot355-1_fr
Fig 33. PCB footprint for SOT355-1 (TSSOP24); reflow soldering
PCA9555A
Product data sheet
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Footprint information for reflow soldering of HVQFN24 package
SOT994-1
Hx
Gx
D
P
0.025
0.025
C
(0.105)
SPx
nSPx
Hy
SPy tot
SPy
Gy
SLy
nSPy
By
Ay
SPx tot
SLx
Bx
Ax
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
solder paste deposit
solder land plus solder paste
occupied area
nSPx
nSPy
2
2
Dimensions in mm
P
Ax
Ay
Bx
By
C
D
SLx
SLy
SPx tot
SPy tot
SPx
SPy
Gx
Gy
Hx
Hy
0.500
5.000
5.000
3.200
3.200
0.900
0.240
2.100
2.100
1.200
1.200
0.450
0.450
4.300
4.300
5.250
5.250
Issue date
07-09-24
09-06-15
sot994-1_fr
Fig 34. PCB footprint for SOT994-1 (HWQFN24); reflow soldering
PCA9555A
Product data sheet
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
19. Abbreviations
Table 22.
Abbreviations
Acronym
Description
ACPI
Advanced Configuration and Power Interface
CBT
Cross-Bar Technology
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
ESD
ElectroStatic Discharge
FET
Field-Effect Transistor
FF
Flip-Flop
GPIO
General Purpose Input/Output
HBM
Human Body Model
I2C-bus
Inter-Integrated Circuit bus
I/O
Input/Output
LED
Light Emitting Diode
SMBus
System Management Bus
20. Revision history
Table 23.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9555A v.1.1
20151006
Product data sheet
-
PCA9555A v.1
Modifications:
PCA9555A v.1
PCA9555A
Product data sheet
•
•
Figure 12; Corrected Figure note 1; this device does not have open-drain output option.
Updated Section 3 “Ordering information” to new standard.
20120911
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 6 October 2015
-
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Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
21. Legal information
21.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
21.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
21.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9555A
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 6 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
37 of 39
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
21.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP Semiconductors N.V.
22. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9555A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 6 October 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
38 of 39
PCA9555A
NXP Semiconductors
Low-voltage 16-bit I2C-bus I/O port with interrupt and weak pull-up
23. Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.3
6.4
6.5
7
7.1
7.2
8
8.1
8.2
8.3
9
10
11
12
12.1
13
14
15
16
17
17.1
17.2
17.3
17.4
18
19
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Device address . . . . . . . . . . . . . . . . . . . . . . . . . 5
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pointer register and command byte . . . . . . . . . 5
Input port register pair (00h, 01h) . . . . . . . . . . . 6
Output port register pair (02h, 03h) . . . . . . . . . 6
Polarity inversion register pair (04h, 05h) . . . . . 7
Configuration register pair (06h, 07h) . . . . . . . . 7
I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9
Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 9
Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9
Writing to the port registers. . . . . . . . . . . . . . . . 9
Reading the port registers . . . . . . . . . . . . . . . 11
Application design-in information . . . . . . . . . 14
Minimizing IDD when the I/Os are used to
control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Power-on reset requirements . . . . . . . . . . . . . 15
Device current consumption with internal
pull-up and pull-down resistors . . . . . . . . . . . . 17
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 18
Recommended operating conditions. . . . . . . 18
Thermal characteristics . . . . . . . . . . . . . . . . . 18
Static characteristics. . . . . . . . . . . . . . . . . . . . 19
Typical characteristics . . . . . . . . . . . . . . . . . . 21
Dynamic characteristics . . . . . . . . . . . . . . . . . 25
Parameter measurement information . . . . . . 26
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 29
Handling information. . . . . . . . . . . . . . . . . . . . 31
Soldering of SMD packages . . . . . . . . . . . . . . 31
Introduction to soldering . . . . . . . . . . . . . . . . . 31
Wave and reflow soldering . . . . . . . . . . . . . . . 31
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 31
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 32
Soldering: PCB footprints. . . . . . . . . . . . . . . . 34
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 36
20
21
21.1
21.2
21.3
21.4
22
23
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
37
37
37
37
38
38
39
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 6 October 2015
Document identifier: PCA9555A
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