PCA9557BSHP

PCA9557 8-bit I2C-bus and SMBus I/O port with reset Rev. 7 — 10 December 2013 Product data sheet 1. General description The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part. 2. Features and benefits                  Lower voltage, higher performance migration path for the PCA9556 8 general purpose input/output expander/collector Input/output configuration register Active HIGH polarity inversion register I2C-bus and SMBus interface logic Internal power-on reset Noise filter on SCL/SDA inputs Active LOW reset input 3 address pins allowing up to 8 devices on the I2C-bus/SMBus High-impedance open-drain on IO0 No glitch on power-up Power-up with all channels configured as inputs Low standby current Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant inputs/outputs 0 kHz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101  Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA  Three packages offered: SO16, TSSOP16, HVQFN16 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 3. Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9557BS 9557 HVQFN16 plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4  4  0.85 mm SOT629-1 PCA9557D PCA9557D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 PCA9557PW PCA9557 TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 3.1 Ordering options Table 2. Ordering options Type number Orderable part number Package Packing method Minimum Temperature range order quantity PCA9557BS PCA9557BS,118 HVQFN16 Reel 13” Q1/T1 *Standard mark SMD 6000 Tamb = 40 C to +85 C PCA9557D PCA9557D,112 SO16 Standard marking * IC’s tube - DSC bulk pack 1000 Tamb = 40 C to +85 C PCA9557D,118 SO16 Reel 13” Q1/T1 *Standard mark SMD 2500 Tamb = 40 C to +85 C PCA9557PW,112 TSSOP16 Standard marking * IC’s tube - DSC bulk pack 2400 Tamb = 40 C to +85 C PCA9557PW,118 TSSOP16 Reel 13” Q1/T1 *Standard mark SMD 2500 Tamb = 40 C to +85 C PCA9557PW 4. Block diagram PCA9557 A0 A1 A2 8-bit SCL SDA INPUT FILTER I2C-BUS/SMBus CONTROL write pulse read pulse VDD VSS INPUT/ OUTPUT PORTS IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 POWER-ON RESET RESET 002aad275 Fig 1. PCA9557 Product data sheet Block diagram of PCA9557 All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 2 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset data from shift register configuration register data from shift register D Q output port register data FF write configuration pulse CK Q D Q FF IO0 write pulse CK ESD protection diode output port register VSS input port register D Q input port register data FF CK read pulse polarity inversion register data from shift register D Q polarity inversion register data FF write polarity pulse CK 002aad277 On power-up or reset, all registers return to default values. Fig 2. PCA9557 Product data sheet Simplified schematic of IO0 All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 3 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset data from shift register output port register data configuration register data from shift register D VDD Q ESD protection diode FF write configuration pulse CK Q D Q FF IO1 to IO7 write pulse CK ESD protection diode output port register VSS input port register D Q input port register data FF CK read pulse polarity inversion register data from shift register D Q polarity inversion register data FF write polarity pulse CK 002aad278 On power-up or reset, all registers return to default values. Fig 3. PCA9557 Product data sheet Simplified schematic of IO1 to IO7 All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 4 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 5. Pinning information 5.1 Pinning SCL 1 16 VDD SDA 2 15 RESET A0 3 14 IO7 A1 4 13 IO6 PCA9557D A2 5 12 IO5 IO0 6 11 IO4 IO1 7 VSS 8 10 IO3 9 IO2 SCL 1 16 VDD SDA 2 15 RESET A0 3 14 IO7 A1 4 A2 5 IO0 6 11 IO4 IO1 7 10 IO3 VSS 8 PCA9557PW 12 IO5 9 002aad272 IO2 002aad273 A0 1 A1 2 Pin configuration for TSSOP16 13 RESET terminal 1 index area 14 VDD Fig 5. 15 SCL Pin configuration for SO16 16 SDA Fig 4. 13 IO6 12 IO7 11 IO6 PCA9557BS 7 8 IO3 9 IO2 4 6 IO0 VSS 10 IO5 5 3 IO1 A2 IO4 002aad274 Transparent top view Fig 6. Pin configuration for HVQFN16 5.2 Pin description Table 3. Symbol PCA9557 Product data sheet Pin description Pin Description SO16, TSSOP16 HVQFN16 SCL 1 15 serial clock line SDA 2 16 serial data line A0 3 1 address input 0 A1 4 2 address input 1 A2 5 3 address input 2 IO0 6 4 input/output 0 (open-drain) IO1 7 5 input/output 1 All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 5 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset Table 3. Pin description …continued Symbol Pin Description SO16, TSSOP16 HVQFN16 VSS 8 6[1] supply ground IO2 9 7 input/output 2 IO3 10 8 input/output 3 IO4 11 9 input/output 4 IO5 12 10 input/output 5 IO6 13 11 input/output 6 IO7 14 12 input/output 7 RESET 15 13 active LOW reset input VDD 16 14 supply voltage [1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to the supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region. 6. System diagram INPUT PORT 1.1 kΩ POLARITY INVERSION CONFIG. OUTPUT PORT 1.1 kΩ Q7 Q7 Q7 Q7 IO0 Q6 Q6 Q6 Q6 IO1 Q5 Q5 Q5 Q5 IO2 Q4 Q4 Q4 Q4 IO3 Q3 Q3 Q3 Q3 IO4 Q2 Q2 Q2 Q2 IO5 Q1 Q1 Q1 Q1 IO6 Q0 Q0 Q0 Q0 IO7 RESET 1.6 kΩ SCL 1.6 kΩ INTERFACE LOGIC SDA 1.1 kΩ A2 I2C-BUS/SMBus or 1.1 kΩ A1 or 1.1 kΩ A0 or 002aad276 Fig 7. System diagram PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 6 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 7. Functional description Refer to Figure 1 “Block diagram of PCA9557”. 7.1 Device address Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9557 is shown in Figure 8. To conserve power, no internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. slave address 0 0 1 1 A2 fixed A1 A0 R/W programmable 002aad279 Fig 8. PCA9557 device address The last bit of the slave address defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.2 Control register Following the successful acknowledgement of the slave address, the bus master will send a byte to the PCA9557, which will be stored in the control register. This register can be written and read via the I2C-bus. bit: 7 6 5 4 3 2 1 0 0 0 0 0 0 0 D1 D0 002aad280 Fig 9. Control register Table 4. PCA9557 Product data sheet Register definition D1 D0 Name Access Description 0 0 Register 0 read-only Input port register 0 1 Register 1 read/write Output port register 1 0 Register 2 read/write Polarity inversion register 1 1 Register 3 read/write Configuration register All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 7 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 7.3 Register descriptions 7.3.1 Register 0 - Input port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register have no effect. Table 5. Register 0 - Input port register bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I7 I6 I5 I4 I3 I2 I1 I0 7.3.2 Register 1 - Output port register This register reflects the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. Table 6. Bit Register 1 - Output port register bit allocation 7 6 5 4 3 2 1 0 Symbol O7 O6 O5 O4 O3 O2 O1 O0 Default 0 0 0 0 0 0 0 0 7.3.3 Register 2 - Polarity inversion register This register enables polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with logic 1), the corresponding port pin’s polarity is inverted. If a bit in this register is cleared (written with logic 0), the corresponding port pin’s original polarity is retained. Table 7. Bit Register 2 - Polarity inversion register bit allocation 7 6 5 4 3 2 1 0 Symbol N7 N6 N5 N4 N3 N2 N1 N0 Default 1 1 1 1 0 0 0 0 7.3.4 Register 3 - Configuration register This register configures the directions of the I/O pins. If a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared, the corresponding port pin is enabled as an output. Table 8. Bit PCA9557 Product data sheet Register 3 - Configuration register bit allocation 7 6 5 4 3 2 1 0 Symbol C7 C6 C5 C4 C3 C2 C1 C0 Default 1 1 1 1 1 1 1 1 All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 8 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 7.4 Power-on reset When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9557 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9557 registers and I2C-bus/SMBus state machine will initialize to their default states. Thereafter, VDD must be lowered below 0.2 V to reset the device. 7.5 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of tw(rst). The PCA9557 registers and SMBus/I2C-bus state machine will be held in their default state until the RESET input is once again HIGH. This input requires a pull-up resistor to VDD if no active connection is used. 8. Characteristics of the I2C-bus The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 10). SDA SCL data line stable; data valid change of data allowed mba607 Fig 10. Bit transfer 8.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 11). PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 9 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset SDA SCL S P START condition STOP condition mba608 Fig 11. Definition of START and STOP conditions 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’ (see Figure 12). SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER SLAVE 002aaa966 Fig 12. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and hold times must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 10 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 S 9 clock pulse for acknowledgement START condition 002aaa987 Fig 13. Acknowledgement on the I2C-bus 8.4 Bus transactions Data is transmitted to the PCA9557 registers using Write Byte transfers (see Figure 14 and Figure 15). Data is read from the PCA9557 registers using Read and Receive Byte transfers (see Figure 16 and Figure 17). SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 0 1 1 A2 A1 A0 0 START condition R/W A 0 0 0 0 0 0 STOP condition data to port command byte 0 1 acknowledge from slave A DATA 1 A P acknowledge from slave acknowledge from slave write to port tv(Q) data out from port DATA 1 VALID 002aad281 Fig 14. Write to output port register SCL 1 2 3 4 5 6 7 8 9 slave address SDA S 0 0 1 1 A2 A1 A0 0 START condition R/W A 0 0 0 0 0 0 STOP condition data to register command byte 1 1/0 A acknowledge from slave acknowledge from slave DATA A P acknowledge from slave 002aad282 Fig 15. Write to I/O configuration or polarity inversion registers PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 11 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset slave address SDA S 0 0 1 command byte 1 A2 A1 A0 0 START condition A A R/W acknowledge from slave acknowledge from slave slave address (cont.) S 0 0 1 1 A2 A1 A0 1 (repeated) START condition (cont.) data from register A DATA (first byte) R/W data from register DATA (last byte) A acknowledge from master acknowledge from slave NA P STOP condition no acknowledge from master at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter 002aad283 Fig 16. Read from register no acknowledge from master slave address SDA S 0 0 1 1 A2 A1 A0 1 START condition data from port data from port R/W DATA 1 A A acknowledge from slave DATA 4 acknowledge from master NA P STOP condition read from port tsu(D) th(D) data into port DATA 1 DATA 2 DATA 3 DATA 4 002aad284 Remark: This figure assumes the command byte has previously been programmed with 00h. Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the last acknowledge phase is valid (output mode). Input data is lost. Fig 17. Read input port register PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 12 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 9. Application design-in information VDD (5 V) 1.8 kΩ 1.8 kΩ 2 kΩ 620 Ω 2 kΩ VDD 100 kΩ (× 5) VDD MASTER CONTROLLER SCL SCL IO0 SUBSYSTEM 1 (e.g., temp. sensor) SDA SDA IO1 INT PCA9557 IO2 RESET RESET IO3 RESET SUBSYSTEM 2 (e.g., counter) IO4 VSS IO5 A IO6 IO7 A2 controlled switch (e.g., CBT device) enable A1 B A0 VSS ALARM SUBSYSTEM 3 (e.g., alarm system) VDD 002aad285 Device address configured as 0011 100x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used. Fig 18. Typical application 9.1 Minimizing IDD when the I/Os are used to control LEDs When the I/Os are used to control LEDs, they are normally connected to VDD through a resistor as shown in Figure 18. Since the LED acts as a diode, when the LED is off the I/O VI is about 1.2 V less than VDD. The supply current, IDD, increases as VI becomes lower than VDD. Designs needing to minimize current consumption, such as battery power applications, should consider maintaining the I/O pins greater than or equal to VDD when the LED is off. Figure 19 shows a high value resistor in parallel with the LED. Figure 20 shows VDD less than the LED supply voltage by at least 1.2 V. Both of these methods maintain the I/O VI at or above VDD and prevents additional supply current consumption when the LED is off. PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 13 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 3.3 V VDD VDD LED VDD 100 kΩ IOn 5V LED IOn 002aac660 Fig 19. High value resistor in parallel with the LED 002aac661 Fig 20. Device supplied by a lower voltage 10. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD VI Conditions Min Max Unit supply voltage 0.5 +6 V input voltage VSS  0.5 5.5 V II input current - 20 mA IIHL(max) maximum allowed input current VI  VDD or VI  VSS through protection diode (IO1 to IO7) - 400 A VI/O voltage on an input/output pin I/O as an input, except IO0 VSS  0.5 5.5 V IO0 as an input VSS  0.5 5.5 V IO0 as an input - +400 A II/O input/output current - 20 mA IO(IOn) output current on pin IOn - 50 mA IDD supply current - 85 mA ISS ground supply current - 100 mA Ptot total power dissipation - 200 mW Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +85 C PCA9557 Product data sheet operating All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 14 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 11. Static characteristics Table 10. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Supplies VDD supply voltage 2.3 - 5.5 V IDD supply current operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz - 19 25 A IstbL LOW-level standby current standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs - 0.25 1 A IstbH HIGH-level standby current standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs - 0.25 1 A Istb additional standby current standby mode; VDD = 5.5 V; every LED I/O at VI = 4.3 V; fSCL = 0 kHz - 0.8 1 mA VPOR power-on reset voltage no load; VI = VDD or VSS - 1.65 2.1 V [1] Input SCL; input/output SDA VIL LOW-level input voltage 0.5 - +0.3VDD V VIH HIGH-level input voltage 0.7VDD - 5.5 V IOL LOW-level output current VOL = 0.4 V; VDD = 2.3 V 3 - - mA IL leakage current VI = VDD or VSS 1 - +1 A Ci input capacitance VI = VSS - 6 10 pF I/Os VIL LOW-level input voltage 0.5 - +0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V VOL = 5.5 V; VDD = 2.3 V [2] 8 10 - mA except pin IO0; VOH = 2.4 V [3] 4 - - mA LOW-level output current IOL HIGH-level output current IOH pin IO0; VOH = 4.6 V - - 1 A pin IO0; VOH = 3.3 V - - 1 A VDD = 5.5 V; VI = VSS - - 100 A ILI input leakage current Ci input capacitance - 3.7 5 pF Co output capacitance - 3.7 5 pF Select inputs A0, A1, A2 and RESET VIL LOW-level input voltage 0.5 - +0.8 V VIH HIGH-level input voltage 2.0 - 5.5 V ILI input leakage current 1 - +1 A [1] VDD must be lowered to 0.2 V in order to reset part. [2] The total amount sunk by all I/Os must be limited to 100 mA and 25 mA per bit. [3] The total current sourced by all I/Os must be limited to 85 mA and 20 mA per bit. PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 15 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 12. Dynamic characteristics Table 11. Dynamic characteristics Symbol Parameter Conditions Standard-mode I2C-bus Min Max Fast-mode I2C-bus Min Max Unit fSCL SCL clock frequency 0 100 0 400 tBUF bus free time between a STOP and START condition 4.7 - 1.3 - kHz s tHD;STA hold time (repeated) START condition 4.0 - 0.6 - s tSU;STA set-up time for a repeated START condition 4.7 - 0.6 - s tSU;STO set-up time for STOP condition 4.0 - 0.6 - s tHD;DAT data hold time 0 - 0 - ns - 1 - 0.9 s - 1 - 0.9 s tVD;ACK data valid acknowledge time [1] tVD;DAT data valid time [2] tSU;DAT data set-up time 250 - 100 - ns tLOW LOW period of the SCL clock 4.7 - 1.3 - s tHIGH HIGH period of the SCL clock 4.0 - 0.6 - s tf fall time of both SDA and SCL signals - 300 20 + 0.1Cb[3] 300 ns tr rise time of both SDA and SCL signals - 1000 20 + 0.1Cb[3] 300 ns tSP pulse width of spikes that must be suppressed by the input filter - 50 - 50 ns pin IO0 - 250 - 250 ns pins IO1 to IO7 - 200 - 200 ns Port timing tv(Q) data output valid time tsu(D) data input set-up time th(D) data input hold time 0 - 0 - ns 200 - 200 - ns 6 - 6 - ns Reset timing tw(rst) reset pulse width trec(rst) reset recovery time trst reset time [1] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. [2] tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. [3] Cb = total capacitance of one bus line in pF. PCA9557 Product data sheet 0 - 0 - ns 400 - 400 - ns All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 16 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 0.7 × VDD SDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD tHD;STA P tSU;STA tHD;DAT S tHIGH tSU;DAT tSU;STO Sr P 002aaa986 Fig 21. Definition of timing on the I2C-bus ACK or read cycle START SCL SDA 30 % trst RESET 50 % 50 % trec(rst) 50 % tw(rst) trst IOn 50 % I/O configured as inputs 002aad289 Fig 22. Definition of RESET timing PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 17 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 13. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ =   4 $ $ $  $ SLQLQGH[ ș /S  /  H Z 0 ES   GHWDLO; PP VFDOH ',0(16,216LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP                                                 LQFKHV         ș R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPLQFKPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7(   Fig 23. Package outline SOT109-1 (SO16) PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 18 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ =   4 $ SLQLQGH[ $  $ $ ș /S /   H GHWDLO; Z 0 ES   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = ș PP                            R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7(   Fig 24. Package outline SOT403-1 (TSSOP16) PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 19 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset +94)1SODVWLFWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP % ' 627 $ WHUPLQDO LQGH[DUHD $ $ ( F GHWDLO; H & H H  \ \ & Y 0 & $ % Z 0 & E  /   H H (K H   WHUPLQDO LQGH[DUHD   ; 'K   PP VFDOH ',0(16,216PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 PP $ PD[ $ E      F ' 'K ( (K          H H  / Y Z \ \       H   1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& -(,7$ 627  02  (8523($1 352-(&7,21 ,668('$7(    Fig 25. Package outline SOT629-1 (HVQFN16) PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 20 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 14. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 21 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 26) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350  350 < 2.5 235 220  2.5 220 220 Table 13. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 26. PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 22 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 23 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 16. Soldering: PCB footprints )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI62SDFNDJH 627 +[ *[ 3  +\ *\  %\ $\ & 'î ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3 3 $\ %\ & ' '       *[   *\ +[ +\    Fig 27. PCB footprint for SOT109-1 (SO16); reflow soldering PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 24 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH 627 +[ *[ 3  +\ *\  %\ $\ & '[ ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3 3 $\ %\ & ' ' *[ *\ +[ +\            VRWBIU Fig 28. PCB footprint for SOT403-1 (TSSOP16); reflow soldering PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 25 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI+94)1SDFNDJH 627 +[ *[ ' 3   &  63[ Q63[ +\ 63\WRW 63\ *\ 6/\ Q63\ %\ $\ 63[WRW 6/[ %[ $[ *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG VROGHUSDVWHGHSRVLW VROGHUODQGSOXVVROGHUSDVWH RFFXSLHGDUHD Q63[ Q63\   'LPHQVLRQVLQPP 3 $[ $\ %[ %\ & ' 6/[ 6/\ 63[WRW 63\WRW 63[ 63\ *[ *\ +[ +\                  ,VVXHGDWH   VRWBIU Fig 29. PCB footprint for SOT629-1 (HVQFN16); reflow soldering PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 26 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 17. Abbreviations Table 14. Abbreviations Acronym Description CBT Cross Bar Technology CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model I2C-bus Inter-Integrated Circuit bus I/O Input/Output LED Light-Emitting Diode MM Machine Model PCB Printed-Circuit Board POR Power-On Reset SMBus System Management Bus 18. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9557 v.7 20131210 Product data sheet - PCA9557 v.6 Modifications: • • • Section 2 “Features and benefits”, 17th bullet item: deleted phrase “150 V MM per JESD22-A115” Table 1 “Ordering information”: added column ‘Topside marking’ (moved from Table 2) Table 2 “Ordering options”: – deleted column ‘Topside mark’ (moved to Table 1) – added columns ‘Orderable part number’, ‘Package’, ‘Packing method’ and ‘Minimum order quantity’ • Table 10 “Static characteristics”, sub-section “Input SCL; input/output SDA”: – IOL: added “VDD = 2.3 V” to Conditions • Table 10 “Static characteristics”, sub-section “I/Os”: – IOL: added “VOL = 0.55 V; VDD = 2.3 V” to Conditions • Table 11 “Dynamic characteristics”, tVD;DAT: Unit corrected from “ms” to “s” (this is a correction to documentation only, no change to device) • Added Section 16 “Soldering: PCB footprints” PCA9557 v.6 20080611 Product data sheet - PCA9557 v.5 PCA9557 v.5 20070912 Product data sheet - PCA9557 v.4 PCA9557 v.4 (9397 750 13336) 20041124 Product data sheet - PCA9557 v.3 PCA9557 v.3 (9397 750 10872) 20021213 Product data ECN 853-2308 29160 of 06 Nov 2002 PCA9557 v.2 PCA9557 v.2 (9397 750 09819) 20020513 Product data ECN 853-2308 28188 of 13 May 2002 PCA9557 v.1 PCA9557 v.1 20011212 Product data ECN 853-2308 27449 of 12 Dec 2001 - PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 27 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 19. Legal information 19.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 19.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA9557 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 28 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 20. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCA9557 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 — 10 December 2013 © NXP B.V. 2013. All rights reserved. 29 of 30 PCA9557 NXP Semiconductors 8-bit I2C-bus and SMBus I/O port with reset 21. Contents 1 2 3 3.1 4 5 5.1 5.2 6 7 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.4 7.5 8 8.1 8.1.1 8.2 8.3 8.4 9 9.1 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 19.1 19.2 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 System diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7 Register descriptions . . . . . . . . . . . . . . . . . . . . 8 Register 0 - Input port register . . . . . . . . . . . . . 8 Register 1 - Output port register . . . . . . . . . . . . 8 Register 2 - Polarity inversion register . . . . . . . 8 Register 3 - Configuration register . . . . . . . . . . 8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 RESET input . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Characteristics of the I2C-bus . . . . . . . . . . . . . 9 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 START and STOP conditions . . . . . . . . . . . . . . 9 System configuration . . . . . . . . . . . . . . . . . . . 10 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 10 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . 11 Application design-in information . . . . . . . . . 13 Minimizing IDD when the I/Os are used to control LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 14 Static characteristics. . . . . . . . . . . . . . . . . . . . 15 Dynamic characteristics . . . . . . . . . . . . . . . . . 16 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 18 Handling information. . . . . . . . . . . . . . . . . . . . 21 Soldering of SMD packages . . . . . . . . . . . . . . 21 Introduction to soldering . . . . . . . . . . . . . . . . . 21 Wave and reflow soldering . . . . . . . . . . . . . . . 21 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 21 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 22 Soldering: PCB footprints. . . . . . . . . . . . . . . . 24 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 19.3 19.4 20 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 29 29 30 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 10 December 2013 Document identifier: PCA9557