PCA9560
2
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP
switch
Rev. 5.0 — 2 December 2021
1
Product data sheet
General description
PCA9560 is a 20-pin CMOS device consisting of two 6-bit non-volatile EEPROM
registers, 5 hardware pin inputs and a 5-bit multiplexed output with one latched EEPROM
bit. It is used for DIP switch-free or jumper-less system configuration and supports Mobile
and Desktop VID Configuration, where 3 preset values (2 sets of internal non-volatile
registers and 1 set of external hardware pins) set processor voltage for operation in
either performance, deep sleep or deeper sleep modes. The PCA9560 is also useful
in server and telecom/networking applications when used to replace DIP switches or
jumpers, since the settings can be easily changed via I2C/SMBus without having to
power down the equipment to open the cabinet. The non-volatile memory retains the
most current setting selected before the power is turned off.
The PCA9560 typically resides between the CPU and Voltage Regulator Module (VRM)
when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass
the CPU-defined VID values and provide a different set of VID values to the VRM, if an
increase in the CPU voltage is desired. An increase in CPU voltage combined with an
increase in CPU frequency leads to a performance boost of up to 7.5%. Lower CPU
voltage reduces power consumption. The main advantage of the PCA9560 over the older
PCA9559 device in this application is that it contains two internal non-volatile EEPROM
registers instead of just one, allowing three independent settings (performance operation,
deep sleep mode and deeper sleep mode) instead of only two (performance operation
and deep sleep mode). The PCA9560 is footprint compatible and a drop-in replacement
for the PCA9559, without any software modifications required.
2
The PCA9560 has 2 address pins allow up to 4 devices to be placed on the same I Cbus or SMBus.
2
Features and benefits
•
•
•
•
•
•
•
•
•
•
•
•
•
•
5-bit 3-to-1 multiplexer, 1-bit latch DIP switch
5-bit external hardware pins
Two 6-bit internal non-volatile registers, fully pin-to-pin compatible with PCA9559
Selection between the two non-volatile registers
Selection between non-volatile registers and external hardware pins
2
I C/SMBus interface logic
Internal pull-up resistors on input pin and control signals
Active high write protect on input controls the ability to write to the non-volatile registers
2
2 address pins, allowing up to 4 devices on the I C-bus
5 open drain multiplexed outputs
Open drain non-multiplexed output
2
Internal 6-bit non-volatile registers programmable and readable via I C-bus
2
External hardware 5-bit value readable via I C-bus
2
Multiplexer selection can be overridden by I C-bus
NXP Semiconductors
2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
•
•
•
•
Operating power supply voltage 3.0 V to 3.6 V
5 V and 2.5 V tolerant inputs/outputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
• Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA.
• Offered in TSSOP20 package
3
Ordering information
Table 1. Ordering information
Type number
PCA9560PW
Topside
marking
Package
Name
Description
Version
PCA9560
TSSOP20
plastic thin shrink small outline package; 20 leads; body
width 4.4 mm
SOT360-1
3.1 Ordering options
Table 2. Ordering options
Type number
Orderable part
number
Package
Packing method
Minimum order
quantity
Temperature
PCA9560PW
PCA9560PW,118
TSSOP20
REEL 13" Q1 NDP
2500
Tamb = -40 °C to +85 °C
PCA9560
Product data sheet
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2 / 26
PCA9560
NXP Semiconductors
2
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
4
Block diagram
PCA9560
WRITE PROTECT
NON-VOLATILE
REGISTER 1
6-BIT EEPROM
6
6-BIT
2 to 1
DEMULTIPLEXER
NON-VOLATILE
REGISTER 0
6-BIT EEPROM
6
LATCH
NON-MUXED_OUT
NMO
5
8
A0
A1
SCL
SDA
INPUT
FILTER
I2C/SMBus
CONTROL
LOGIC
MUX_OUT_A
VDD
POWER-ON
RESET
MUX_OUT_B
3
5-BIT
2 to 1
DEMULTIPLEXER
GND
MUX_IN_A
MUX_OUT_C
MUX_OUT_D
MUX_IN_B
MUX_OUT_E
MUX_IN_C
5
MUX_IN_D
MUX_IN_E
MUX_SELECT_1
SELECT LOGIC
MUX_SELECT_0
aaa-044299
Figure 1. Block diagram of PCA9560
PCA9560
Product data sheet
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3 / 26
NXP Semiconductors
2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
5
Pinning information
5.1 Pinning
SCL
1
20 VDD
SDA
2
19 WP
A1
3
18 MUX_SELECT_1
17 NON-MUXED_OUT
A0
4
MUX_IN_A
5
MUX_IN_B
6
MUX_IN_C
7
14 MUX_OUT_C
MUX_IN_D
8
13 MUX_OUT_D
MUX_IN_E
9
12 MUX_OUT_E
PCA9560PW
GND 10
16 MUX_OUT_A
15 MUX_OUT_B
11 MUX_SELECT_0
aaa-044300
Figure 2. Pin configuration for TSSOP20
5.2 Pin description
Table 3. Pin description
Symbol
Pin
Description
SCL
1
serial I C-bus clock line
SDA
2
serial bidirectional I C-bus data line
A1
3
address 1
A0
4
address 0
MUX_IN_A
5
external input A to multiplexer
MUX_IN_B
6
external input B to multiplexer
MUX_IN_C
7
external input C to multiplexer
MUX_IN_D
8
external input D to multiplexer
MUX_IN_E
9
external input E to multiplexer
GND
10
ground
MUX_SELECT_0
11
selects MUX_IN inputs or EEPROM register contents for MUX_OUT outputs
MUX_OUT_E
12
open-drain multiplexed output E
MUX_OUT_D
13
open-drain multiplexed output D
MUX_OUT_C
14
open-drain multiplexed output C
MUX_OUT_B
15
open-drain multiplexed output B
MUX_OUT_A
16
open-drain multiplexed output A
NON-MUXED_
OUTPUT
17
open-drain output from non-volatile memory
MUX_SELECT_1
18
selects between the two non-volatile registers
WP
19
active HIGH non-volatile register write-protect input
VDD
20
supply voltage (3.0 V to 3.6 V)
PCA9560
Product data sheet
2
2
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2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
6
Functional description
Refer to Figure 1.
6.1 Device address
Following a START condition the bus controller must output the address of the target it
is accessing. The address of the PCA9560 is shown in Figure 3. To conserve power, no
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the target address byte defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
MSB
1
LSB
0
0
1
1
fixed
A1
A0 R/W
hardware
selectable
002aah287
Figure 3. target address
6.2 Control register
Following the successful acknowledgement of the target address, the bus controller will
send a byte to the PCA9560, which will be stored in the Control register. This register can
2
be written and read via the I C-bus.
D7
D6
D5
D4
D3
D2
D1
D0
002aah288
Figure 4. Control register
6.2.1 Control register definition
Following the address and acknowledge bit with logic 0 in the read/write bit, the first byte
written is the command byte. If the command byte is reserved and therefore not valid, it
will not be acknowledged. Only valid command bytes will be acknowledged.
Table 4. Address register
D7
D6
D5
D4
D3
D2
D1
D0
Register name
Type
Register function
0
0
0
0
0
0
0
0
EEPROM_0
read/write
EEPROM byte 0 register
0
0
0
0
0
0
0
1
EEPROM_1
read/write
EEPROM byte 1 register
1
1
1
1
1
1
1
1
MUX_IN
read
MUX_IN values register
Table 5. Commands register
All other combinations are reserved.
D7
D6
D5
D4
D3
D2
D1
D0
Command
1
1
1
1
1
0
0
0
MUX_OUT from EEPROM byte 0
1
1
1
1
1
1
0
0
MUX_OUT from EEPROM byte 1
PCA9560
Product data sheet
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5 / 26
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2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
Table 5. Commands register...continued
All other combinations are reserved.
[1]
D7
D6
D5
D4
D3
D2
D1
D0
Command
1
1
1
1
1
x
1
0
MUX_OUT from MUX_IN
1
1
1
1
1
x
x
1
MUX_OUT from MUX_SELECT
[1]
MUX_SELECT pins select between MUX_IN and EEPROM to MUX_OUT.
6.3 Register description
If the command byte is an EEPROM address, the next byte sent will be programmed into
that EEPROM address on the following STOP condition, if the WP is logic 0. If more than
one byte is sent sequentially, the second byte will be written in the other-volatile register,
on the following STOP condition. If any more data bytes are sent after the second byte,
they will not be acknowledged and no bytes will be written to the non-volatile registers.
After a byte is read from or written to the EEPROM, the part automatically points to the
next non-volatile register. If the command code was FFH, the MUX_IN values are sent
with the three MSBs padded with zeroes as shown below. If the command codes was
00H, then the non-volatile register 1 is sent, and if the command code was 01H, then the
non-volatile register 1 is sent.
Table 6. EEPROM byte 0 register
D7
D6
D5
D4
D3
D2
D1
D0
Write
X
X
nonmuxed data
EEPROM
0 data E
EEPROM
0 data D
EEPROM
0 data C
EEPROM
0 data B
EEPROM
0 data A
Read
0
0
nonmuxed data
EEPROM
0 data E
EEPROM
0 data D
EEPROM
0 data C
EEPROM
0 data B
EEPROM
0 data A
Default
0
0
0
0
0
0
0
0
Table 7. EEPROM byte 1 register
D7
D6
D5
D4
D3
D2
D1
D0
Write
X
X
nonmuxed data
EEPROM
1 data E
EEPROM
1 data D
EEPROM
1 data C
EEPROM
1 data B
EEPROM
1 data A
Read
0
0
nonmuxed data
EEPROM
1 data E
EEPROM
1 data D
EEPROM
1 data C
EEPROM
1 data B
EEPROM
1 data A
Default
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
MUX_IN
data E
MUX_IN
data D
MUX_IN
data C
MUX_IN
data B
MUX_IN
data A
Table 8. MUX_IN register
Read
If the command byte is a MUX command byte, any additional data bytes sent after the
MUX command code will not be acknowledged. If the read/write bit in the address is a
logic 1, then a read operation follows and the data sent out depends on the previously
stored command code.
PCA9560
Product data sheet
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6 / 26
NXP Semiconductors
2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
The MUX_SELECT_1 pin can function as the over-ride pin as on the PCA9559 if the
non-volatile register 1 is left at all 0s.
The NON_MUXED_OUT pin is a latched output. It is latched when MUX_SELECT_0
= 1. It is transparent when the MUX_SELECT_0 = 0. The data sent out on the
NON_MUXED_OUT output is the 6th most significant bit of the non-volatile register.
Whether this comes from the non-volatile register 0 or non-volatile register 1 depends on
the command code or the external mux-select pins.
2
After a valid I C write operation to the EEPROM, the part cannot be addressed via the
I2C for 3.6 ms. If the part is addressed prior to this time, the part will not acknowledge its
address.
Remark: To ensure data integrity, the non-volatile register must be internally write2
protected when VDD to the I C-bus is powered down or VDD to the component is dropped
below normal operating levels.
6.4 Conversion from the PCA9959 to the PCA9560
The PCA9560 is a drop in replacement to the PCA9559 with no software modifications.
The PCA9559 has only one MUX_SELECT pin to choose between the MUX_IN values
and the single non-volatile register. Since the PCA9560 has two internal non-volatile
registers, if Register 1 is left to all 0’s (default condition) then the MUX_SELECT_1 pin
can function the same as the PCA9559 OVERRIDE # pin and MUX_SELECT_0 pin can
function the same as the PCA9559 MUX_IN pin.
2
The PCA9560 can read the MUX_IN_X values via I C that the PACA9559 cannot do.
2
Another difference is that the MUX_SELECT_X control pins can be overridden by I C.
To replace the PCA9559 with the PCA9560, the function table for the MUX_OUT outputs
and the NON_MUXED_OUT output must stay the same and the MUX_SELECT pin
2
functions should not be overridden by I C.
6.5 External control signals
The Write Protect (WP) input is used to control the ability to write the content of the non2
volatile registers. If the WP signal is logic 0, the I C-bus will be able to write the contents
of the non-volatile registers. If the WP signal is logic 1, data will not be allowed to be
written into the non-volatile registers. In this case, the target address and the command
code will be acknowledged, but the following data bytes will not be acknowledged and
the EEPROM is not updated.
The factory defaults for the contents of the non-volatile register are all logic
2
0. These stored values can be read or written using the I C-bus (described in
2
Section 7"Characteristics of the I C-bus").
The WP, MUX_IN, and MUX_SELECT_0 and MUX_SELECT_1 signals have internal
pull-up resistors. See Table 13 and Table 14 for hysteresis and signal spike suppression
figures.
Table 9. Function table
2
This table is valid when not overridden by I C-bus control register.
Input
PCA9560
Product data sheet
Commands
WP
MUX_SELECT_1
MUX_
SELECT_0
0
X
X
2
Write to the non-volatile registers through I C-bus allowed
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NXP Semiconductors
2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
Table 9. Function table...continued
2
This table is valid when not overridden by I C-bus control register.
Input
Commands
WP
MUX_SELECT_1
MUX_
SELECT_0
1
X
X
Write to the non-volatile registers through I C-bus not
allowed
X
0
1
MUX_OUT and NON_MUXED_OUT (transparent) from
EEPROM byte 0
X
0
0
MUX_OUT and NON_MUXED_OUT (transparent) from
EEPROM byte 1
X
1
1
MUX_OUT from MUX_IN inputs and NON_MUXED_OUT
latched (from EEPROM 0)
X
X
X
MUX_OUT from MUX_IN inputs and NON_MUXED_OUT
latched (from EEPROM 1)
2
6.6 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9560
in a reset state until VDD has reached VPOR. At that point, the reset condition is released
2
and the PCA9560 volatile registers and I C/SMBus state machine will initialize to their
default states.
The MUX_OUT and NON_MUXED_OUT pin values depend on:
• The MUX_SELECT_0 and MUX_SELECT_1 logic levels, selecting either the MUX_IN
input pins or one of the two 6-bit EEPROMs
• The previously stored values in the EEPROM registers/current MUX_IN pin values as
shown in Table 9.
7
2
Characteristics of the I C-bus
2
The I C-bus is for 2-way, 2-line communication between different ICs or modules. The
two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be
connected to a positive supply via a pull-up resistor when connected to the output stages
of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must
remain stable during the HIGH period of the clock pulse as changes in the data line at
this time will be interpreted as control signals (see Figure 5).
PCA9560
Product data sheet
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NXP Semiconductors
2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Figure 5. Bit transfer
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P) (seeFigure 6.)
SDA
SCL
S
P
START condition
STOP condition
mba608
Figure 6. Definition of START and STOP conditions
7.2 System configuration
A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The
device that controls the message is the ‘controller’ and the devices which are controlled
by the controller are the ‘targets’ (see Figure 7).
SDA
SCL
CONTROLLER
TRANSMITTER/
RECEIVER
TARGET
RECEIVER
TARGET
TRANSMITTER/
RECEIVER
CONTROLLER
TRANSMITTER
CONTROLLER
TRANSMITTER/
RECEIVER
I2C-BUS
MULTIPLEXER
TARGET
002aaa966
Figure 7. System configuration
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions
from transmitter to receiver is not limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,
whereas the controller generates an extra acknowledge related clock pulse.
PCA9560
Product data sheet
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Rev. 5.0 — 2 December 2021
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9 / 26
PCA9560
NXP Semiconductors
2
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
A target receiver which is addressed must generate an acknowledge after the reception
of each byte. Also a controller must generate an acknowledge after the reception of each
byte that has been clocked out of the target transmitter. The device that acknowledges
has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is
stable LOW during the HIGH period of the acknowledge related clock pulse; set-up and
hold times must be taken into account.
A controller receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the target. In this event, the
transmitter must leave the data line HIGH to enable the controller to generate a STOP
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from controller
1
2
8
S
9
clock pulse for
acknowledgement
START
condition
002aaa987
2
Figure 8. Acknowledgement on the I C-bus
7.4 Bus transactions
Data is transmitted to the PCA9560 registers using the Write Byte transfers (see Figure 9
and Figure 10. Data is read from PCA9560 using Read and Receive Byte transfers (see
Figure 11).
control register
write on EEPROM byte 0
target address
SDA
S
1
0
0
START condition
1
1
A1 A0
0
R/W
A
0
0
0
0
0
0
0
EEPROM byte 0 data
0
acknowledge
from target
A
X
X
acknowledge
from target
D5 D4 D3 D2 D1 D0
A
P
acknowledge
from target
STOP condition
002aah289
Figure 9. Write on one EEPROM, assuming WP = 0
PCA9560
Product data sheet
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10 / 26
PCA9560
NXP Semiconductors
2
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
control register
write on EEPROM byte 0
target address
SDA
S
1
0
0
1
1
A1 A0
START condition
0
R/W
A
0
0
0
0
0
0
EEPROM byte 0 data
0
0
acknowledge
from target
A
X
X
D5 D4 D3 D2 D1 D0
A
(cont.)
acknowledge
acknowledge
from target
from target
EEPROM byte 1 data
(cont.)
X
X
D5 D4 D3 D2 D1 D0
A
P
acknowledge
from target
STOP condition
002aah290
Figure 10. Write on two EEPROMs, assuming WP = 0
control register
read MUX_IN values
target address
SDA
S
1
0
0
1
1
A1 A0
START condition
0
R/W
A
1
1
1
1
1
acknowledge
from controller
1
target address
1
1
A
acknowledge
from controller
(cont.)
A
S
1
0
0
1
1
A1 A0
ReSTART
1
(cont.)
R/W
data from MUX_IN
0
0
0
acknowledge
from controller
4
3
2
1
0
NA
P
no acknowledge
from controller
STOP condition
aaa-044302
Figure 11. Read MUX_IN register
8
Limiting values
[1]
Table 10. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VDD
supply voltage
VI
Conditions
input voltage
Min
Max
-0.5
+4.0
-1.5
Unit
V
+5.5
[2]
V
[2]
V
VO
output voltage
-0.5
+5.5
Tstg
storage temperature
-60
+150
[1]
[2]
°C
The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which
are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
The maximum input or output voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short durations (for example, system start-up or shut-down).
PCA9560
Product data sheet
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11 / 26
PCA9560
NXP Semiconductors
2
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
9
Recommended operating conditions
Table 11. Operating conditions
Symbol
Parameter
VDD
supply voltage
VIL
LOW-level input voltage
VIH
VOL
Conditions
Min
Max
Unit
3.0
3.6
V
SCL, SDA; IOL = 3 mA
-0.5
+0.9
V
HIGH-level input voltage
SCL, SDA; IOL = 3 mA
2.7
5.5
LOW-level output voltage
SCL, SDA
IOL = 3 mA
-
0.4
V
IOL = 6 mA
-
0.6
V
V
[1]
V
VIL
LOW-level input voltage
MUX_IN, MUX_SELECT_0,
MUX_SELECT_1
-0.5
+0.8
VIH
HIGH-level input voltage
MUX_IN, MUX_SELECT_0,
MUX_SELECT_1
2.0
5.5
IOL
LOW-level output current
MUX_OUT, NON_MUXED_
OUT
-
8
mA
IOH
HIGH-level output current
MUX_OUT, NON_MUXED_
OUT
-
100
μA
Δt/ΔV
input transition rise and fall rate
0
10
ns/V
Tamb
ambient temperature
-40
+85
°C
[1]
operating in free air
[1]
V
The maximum input voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short durations (for example, system start-up or shut-down).
10 Thermal characteristics
Table 12. Thermal characteristics
Symbol
Parameter
Conditions
Typ
Unit
Rth(j-a)
thermal resistance from junction to ambient
TSSOP20 package
146
°C/W
11 Static characteristics
Table 13. Static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
3
-
3.6
V
all inputs = 0 V
-
-
1
mA
all inputs = VDD
-
-
600
μA
-
2.3
2.7
V
-0.5
-
+0.8
Supply
VDD
supply voltage
IDD
supply current
VPOR
power-on reset voltage
operating mode
no load; VI = VDD or VSS
Input SCL; input/output SDA
VIL
VIH
LOW-level input voltage
HIGH-level input voltage
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5.5
[1]
V
V
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Table 13. Static characteristics...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
IOL
LOW-level output current
VOL = 0.4 V
3
-
-
mA
VOL = 0.6 V
6
-
-
mA
ILIH
HIGH-level input leakage current
VI = VDD
-1
-
+1
μA
ILIL
LOW-level input leakage current
VI = VSS
-1
-
+1
μA
Ci
input capacitance
-
3
6
pF
WP; MUX_SELECT_0, MUX_SELECT_1
ILIH
HIGH-level input leakage current
VI = VDD
-1
-
+1
μA
ILIL
LOW-level input leakage current
VDD = 3.6 V; VI = VSS
-20
-
-50
μA
Ci
input capacitance
-
2.5
5
pF
MUX_IN_A, MUX_IN_B, MUX_IN_C, MUX_IN_D, MUX_IN_E
ILIH
HIGH-level input leakage current
VI = VDD
-1
-
+1
μA
ILIL
LOW-level input leakage current
VDD = 3.6 V; VI = VSS
-20
-
-50
μA
Ci
input capacitance
-
2.5
5
pF
Inputs A0, A1
ILIH
HIGH-level input leakage current
VI = VDD
-1
-
+1
μA
IIL
LOW-level input current
VDD = 3.6 V; VI = VSS
-20
-
-50
μA
Ci
input capacitance
-
2
4
pF
IOL = 100 μA
-
-
0.4
V
IOL = 4 mA
-
-
0.7
V
VOH = VDD
-
-
100
μA
IOL = 100 μA
-
-
0.4
V
IOL = 2 mA
-
-
0.7
V
MUX_OUT
VOL
LOW-level output voltage
IOH
HIGH-level output current
NON-MUX_OUT
VOL
[1]
LOW-level output voltage
The maximum input voltage is the lesser of 5.5 V or VDD + 4.0 V, except for very short durations (for example, system start-up or shut-down).
12 Dynamic characteristics
Table 14. Dynamic characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
MUX_IN ⇒ MUX_OUT
tPLH
LOW to HIGH propagation delay
-
28
40
ns
tPHL
HIGH to LOW propagation delay
-
8
15
ns
Select ⇒ MUX_OUT
tPLH
LOW to HIGH propagation delay
-
30
43
ns
tPHL
HIGH to LOW propagation delay
-
10
15
ns
tr
rise time
1.0
-
3
ns/V
PCA9560
Product data sheet
output
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Table 14. Dynamic characteristics...continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tf
fall time
output
1.0
-
3
ns/V
CL
load capacitance
test load on outputs
-
-
50
pF
Select ⇒ NON-MUX_OUT
tPLH
LOW to HIGH propagation delay
-
30
40
ns
tPHL
HIGH to LOW propagation delay
-
9
15
ns
2
Table 15. I C-bus dynamic characteristics
Symbol
Parameter
Conditions
Standard2
mode I C-bus
Fast-mode
2
I C-bus
Unit
Min
Max
Min
Max
0
100
0
400
fSCL
SCL clock frequency
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
μs
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
μs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
μs
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
μs
tHD;DAT
data hold time
0
-
0
-
μs
tVD;ACK
tVD;DAT
valid time for ACK condition
[2]
data out valid time
0.3
300
3.45
-
0.1
50
0.9
-
µs
ns
tSU;DAT
data set-up time
250
-
100
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
μs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
tr
[1]
rise time of both SDA and SCL signals
-
1000
tf
fall time of both SDA and SCL signals
-
300
tSP
pulse width of spikes that must be
suppressed by the input filters
-
50
[1]
[2]
[3]
MHz
-
μs
20 +
[3]
0.1Cb
300
ns
20 +
[3]
0.1Cb
300
ns
50
ns
-
tVD;ACK = time for Acknowledgement signal from SCL LOW to SDA (out) LOW.
tVD;DAT = minimum time for SDA data out to be valid following SCL LOW.
Cb = total capacitance of one bus line in pF.
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0.7 × VDD
SDA
0.3 × VDD
tr
tBUF
tf
tHD;STA
tSP
tLOW
0.7 × VDD
SCL
0.3 × VDD
P
S
tHD;STA
tHD;DAT
tHIGH
tSU;DAT
Sr
tSU;STA
tSU;STO
P
002aaa986
Figure 12. Definition of timing
MUX input
VM
VM
tPLZ
tPHL
MUX output
VM
VO
VOL + 0.3 V
VOL
002aah292
Figure 13. Open-drain output enable and disable times
13 Non-volatile storage specifications
Table 16. Non-volatile storage specifications
Parameter
Specification
memory cell data retention
10 years (minimum)
number of memory cell write cycles
100,000 cycles (minimum)
Application note AN250, "I2C DIP Switch" provides additional information on memory cell
data retention and the minimum number of write cycles.
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14 Test information
VO
VDD
PULSE
GENERATOR
VI
DUT
RT
VO
RL
CL
002aah293
RL = load resistor; 1 kΩ.
CL = load capacitance; includes jig and probe capacitance; 10 pF.
RT = termination resistance; should be equal to Zo of pulse generators.
Figure 14. Test circuit for open-drain outputs
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15 Package outline
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
D
SOT360-1
E
A
X
c
HE
y
v M A
Z
11
20
Q
A2
pin 1 index
(A 3 )
A1
A
θ
Lp
1
L
10
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.5
0.2
8o
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT360-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
MO-153
Figure 15. Package outline SOT360-1 (TSSOP20)
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16 Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached
to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides
both the mechanical and the electrical connection. There is no single soldering method
that is ideal for all IC packages. Wave soldering is often preferred when through-hole
and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is
not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming
from a standing wave of liquid solder. The wave soldering process is suitable for the
following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
16.4 Reflow soldering
Key characteristics in reflow soldering are:
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• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads
to higher minimum peak temperatures (see Figure 16) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board
is heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder
paste characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 17 and Table 18
Table 17. SnPb eutectic process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 18. Lead-free process (from J-STD-020D)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm³)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 16.
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temperature
maximum peak temperature
= MSL limit, damage level
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Figure 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
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17 Soldering: PCB footprints
Footprint information for reflow soldering of TSSOP20 package
SOT360-1
Hx
Gx
P2
(0.125)
Hy
Gy
(0.125)
By
Ay
C
D2 (4x)
D1
P1
Generic footprint pattern
Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ay
By
C
D1
D2
Gx
Gy
Hx
Hy
0.650
0.750
7.200
4.500
1.350
0.400
0.600
6.900
5.300
7.300
7.450
sot360-1_fr
Figure 17. PCB footprint for SOT360-1 (TSSOP20); reflow soldering
PCA9560
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18 Abbreviations
Table 19. Abbreviations
Acronym
Description
CDM
Charged-Device Model
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
DIP
Dual In-line Package
EEPROM
Electrically Erasable Programmable Read-Only Memory
ESD
ElectroStatic Discharge
HBM
Human Body Model
2
I C-bus
Inter-Integrated Circuit bus
PCB
Printed-Circuit Board
SMBus
System Management Bus
VID
Voltage IDentification code
VRM
Voltage Regulator Module
19 Revision history
Table 20. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA9560 v.5
20211202
Product data sheet
-
PCA9560 v.4
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• The terms "master" and "slave" were replaced by "controller" and "target" to comply with NXP's
inclusive language project.
• Removed PCA9560PW,112 from Table 2.
PCA9560 v.4
20040519
PCA9560
Product data sheet
Product data sheet
-
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20 Legal information
20.1 Data sheet status
Document status
[1][2]
Product status
[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product
development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term 'short data sheet' is explained in section "Definitions".
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — A draft status on a document indicates that the content is still
under internal review and subject to formal approval, which may result
in modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included in a draft version of a document and shall have no
liability for the consequences of use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is
intended for quick reference only and should not be relied upon to contain
detailed and full information. For detailed and full information see the
relevant full data sheet, which is available on request via the local NXP
Semiconductors sales office. In case of any inconsistency or conflict with the
short data sheet, the full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product
is deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed
to be accurate and reliable. However, NXP Semiconductors does not give
any representations or warranties, expressed or implied, as to the accuracy
or completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability
towards customer for the products described herein shall be limited in
accordance with the Terms and conditions of commercial sale of NXP
Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to
make changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA9560
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their
applications and products using NXP Semiconductors products, and NXP
Semiconductors accepts no liability for any assistance with applications or
customer product design. It is customer’s sole responsibility to determine
whether the NXP Semiconductors product is suitable and fit for the
customer’s applications and products planned, as well as for the planned
application and use of customer’s third party customer(s). Customers should
provide appropriate design and operating safeguards to minimize the risks
associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default
in the customer’s applications or products, or the application or use by
customer’s third party customer(s). Customer is responsible for doing all
necessary testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications
and the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those
given in the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or
the grant, conveyance or implication of any license under any copyrights,
patents or other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use in non-automotive qualified products — Unless
this data sheet expressly states that this specific NXP Semiconductors
product is automotive qualified, the product is not suitable for automotive
use. It is neither qualified nor tested in accordance with automotive testing
or application requirements. NXP Semiconductors accepts no liability for
inclusion and/or use of non-automotive qualified products in automotive
equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty
of the product for such automotive applications, use and specifications, and
(b) whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
PCA9560
Product data sheet
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
20.4 Trademarks
Notice: All referenced brands, product names, service names, and
trademarks are the property of their respective owners.
NXP — wordmark and logo are trademarks of NXP B.V.
I2C-bus — logo is a trademark of NXP B.V.
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Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Ordering information ..........................................2
Ordering options ................................................2
Pin description ...................................................4
Address register ................................................ 5
Commands register ........................................... 5
EEPROM byte 0 register ...................................6
EEPROM byte 1 register ...................................6
MUX_IN register ................................................6
Function table ....................................................7
Limiting values ................................................ 11
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Operating conditions ....................................... 12
Thermal characteristics ................................... 12
Static characteristics ....................................... 12
Dynamic characteristics .................................. 13
I2C-bus dynamic characteristics ..................... 14
Non-volatile storage specifications .................. 15
SnPb eutectic process (from J-STD-020D) ..... 19
Lead-free process (from J-STD-020D) ............ 19
Abbreviations ...................................................22
Revision history ...............................................22
Fig. 11.
Fig. 12.
Fig. 13.
Read MUX_IN register .................................... 11
Definition of timing .......................................... 15
Open-drain output enable and disable
times ................................................................ 15
Test circuit for open-drain outputs ................... 16
Package outline SOT360-1 (TSSOP20) ..........17
Temperature profiles for large and small
components ..................................................... 20
PCB footprint for SOT360-1 (TSSOP20);
reflow soldering ............................................... 21
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Block diagram of PCA9560 ...............................3
Pin configuration for TSSOP20 ......................... 4
target address ................................................... 5
Control register ..................................................5
Bit transfer .........................................................9
Definition of START and STOP conditions ........ 9
System configuration .........................................9
Acknowledgement on the I2C-bus .................. 10
Write on one EEPROM, assuming WP = 0 ......10
Write on two EEPROMs, assuming WP = 0 .... 11
PCA9560
Product data sheet
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
All information provided in this document is subject to legal disclaimers.
Rev. 5.0 — 2 December 2021
© NXP B.V. 2021. All rights reserved.
25 / 26
NXP Semiconductors
2
PCA9560
Dual 5-bit multiplexed 1-bit latched I C-bus EEPROM DIP switch
Contents
1
2
3
3.1
4
5
5.1
5.2
6
6.1
6.2
6.2.1
6.3
6.4
6.5
6.6
7
7.1
7.1.1
7.2
7.3
7.4
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
19
20
General description ............................................ 1
Features and benefits .........................................1
Ordering information .......................................... 2
Ordering options ................................................ 2
Block diagram ..................................................... 3
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 4
Functional description ........................................5
Device address ..................................................5
Control register .................................................. 5
Control register definition ...................................5
Register description ........................................... 6
Conversion from the PCA9959 to the
PCA9560 ............................................................7
External control signals ..................................... 7
Power-on reset .................................................. 8
Characteristics of the I2C-bus ........................... 8
Bit transfer ......................................................... 8
START and STOP conditions ............................ 9
System configuration ......................................... 9
Acknowledge ......................................................9
Bus transactions .............................................. 10
Limiting values .................................................. 11
Recommended operating conditions .............. 12
Thermal characteristics ....................................12
Static characteristics ........................................ 12
Dynamic characteristics ...................................13
Non-volatile storage specifications .................15
Test information ................................................ 16
Package outline .................................................17
Soldering of SMD packages .............................18
Introduction to soldering .................................. 18
Wave and reflow soldering .............................. 18
Wave soldering ................................................ 18
Reflow soldering .............................................. 18
Soldering: PCB footprints ................................ 21
Abbreviations .................................................... 22
Revision history ................................................ 22
Legal information .............................................. 23
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section 'Legal information'.
© NXP B.V. 2021.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 December 2021
Document identifier: PCA9560
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