PCA9600DP/S911,118

PCA9600 Dual bidirectional bus buffer Rev. 6.1 — 20 December 2021 1 Product data sheet General description 2 The PCA9600 is designed to isolate I C-bus capacitance, allowing long buses to be driven in point-to-point or multipoint applications of up to 4 000 pF. The PCA9600 is a higher-speed version of the P82B96. It creates a non-latching, bidirectional, logic 2 interface between a normal I C-bus and a range of other higher capacitance or different voltage bus configurations. It can operate at speeds up to at least 1 MHz, and the high drive side is compatible with the Fast-mode Plus (Fm+) specifications. The PCA9600 features temperature-stabilized logic voltage levels at its SX/SY interface 2 making it suitable for interfacing with buses that have non I C-bus-compliant logic levels such as SMBus, PMBus, or with microprocessors that use those same TTL logic levels. 2 The separation of the bidirectional I C-bus signals into unidirectional TX and RX signals enables the SDA and SCL signals to be transmitted via balanced transmission lines (twisted pairs), or with galvanic isolation using opto or magnetic coupling. The TX and RX signals may be connected together to provide a normal bidirectional signal. 2 Features and benefits 2 • Bidirectional data transfer of I C-bus signals • Isolates capacitance allowing 400 pF on SX/SY side and 4 000 pF on TX/TY side • TX/TY outputs have 60 mA sink capability for driving low-impedance or high-capacitive buses • 1 MHz operation on up to 20 meters of wire (see AN10658) 2 • Supply voltage range of 2.5 V to 15 V with I C-bus logic levels on SX/SY side independent of supply voltage 2 • Splits I C-bus signal into pairs of forward/reverse TX/RX, TY/RY signals for interface with opto-electrical isolators and similar devices that need unidirectional input and output signal paths • Low power supply current • ESD protection exceeds 3500 V HBM per JESD22-A114 and 1400 V CDM per JESD22-C101 • Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA • Packages offered: SO8 and TSSOP8 (MSOP8) 3 Applications 2 • Interface between I C-buses operating at different logic levels (for example, 5 V and 3 V or 15 V) 2 • Interface between I C-bus and SMBus (350 μA) standard or Fm+ standard 2 • Simple conversion of I C-bus SDA or SCL signals to multi-drop differential bus hardware, for example, via compatible PCA82C250 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 2 • Interfaces with opto-couplers to provide opto-isolation between I C-bus nodes up to 1 MHz • Long distance point-to-point or multipoint architectures 4 Ordering information Table 1. Ordering information Type number Topside marking Package Name Description Version PCA9600D PCA9600 SO8 plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 PCA9600DP 9600 TSSOP8 plastic thin shrink small outline package; 8 leads; body width 3 mm SOT505-1 4.1 Ordering options Table 2. Ordering options [1] Type number Orderable part number Package Packing method PCA9600D PCA9600D,118 SO8 REEL 13" Q1/T1 2500 *STANDARD MARK SMD Tamb = -40 °C to +85 °C PCA9600DP PCA9600DP,118 TSSOP8 REEL 13" Q1/T1 2500 *STANDARD MARK SMD Tamb = -40 °C to +85 °C TSSOP8 REEL 13" Q1/T1 [3] SSB Tamb = -40 °C to +85 °C PCA9600DPZ [1] [2] [3] [2] Minimum order Temperature quantity 2500 Standard packing quantities and other packaging data are available at www.nxp.com/packages/. Orderable part number PCA9600DPZ is a drop in alternate for PCA9600DP,118. This packing method uses a Static Shielding Bag (SSB) solution. Material should be kept in sealed bag between uses. 5 Block diagram VCC (2.5 V to 15 V) 8 SX (SDA) 1 PCA9600 3 2 SY (SCL) 5 7 6 TX (TxD, SDA) RX (RxD, SDA) TY (TxD, SCL) RY (RxD, SCL) 4 GND 002aac835 Figure 1. Block diagram of PCA9600 PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 2 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 6 Pinning information 6.1 Pinning SX 1 RX 2 TX 3 GND 4 PCA9600D 8 VCC 7 SY 6 RY 5 TY 002aac836 Figure 2. Pin configuration for SO8 SX 1 8 VCC RX 2 7 SY TX 3 6 RY GND 4 5 TY PCA9600DP 002aac837 Figure 3. Pin configuration for TSSOP8 (MSOP8) 6.2 Pin description Table 3. Pin description 7 Symbol Pin Description SX 1 I C-bus (SDA or SCL) RX 2 receive signal TX 3 transmit signal GND 4 negative supply voltage TY 5 transmit signal RY 6 receive signal SY 7 I C-bus (SDA or SCL) VCC 8 positive supply voltage 2 2 Functional description Refer to Figure 1. 2 The PCA9600 has two identical buffers allowing buffering of SDA and SCL I C-bus 2 signals. Each buffer is made up of two logic signal paths, a forward path from the I C-bus interface, pins SX and SY which drive the buffered bus, and a reverse signal path from 2 the buffered bus input, pins RX and RY to drive the I C-bus interface. These paths: 2 • sense the voltage state of I C-bus pins SX (and SY) and transmit this state to pin TX (and TY respectively), and 2 • sense the state of pins RX and RY and pull the I C-bus pin LOW whenever pin RX or pin RY is LOW. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 3 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer The rest of this discussion will address only the ‘X’ side of the buffer; the ‘Y’ side is identical. 2 The I C-bus pin SX is specified to allow interfacing with Fast-mode, Fm+ and TTL-based systems. 2 The logic threshold voltage levels at SX on this I C-bus are independent of the IC supply 2 voltage VCC. The maximum I C-bus supply voltage is 15 V. When interfacing with Fast-mode systems, the SX pin is guaranteed to sink the normal 3 mA with a VOL of 0.74 V maximum. That guarantees compliance with the Fast-mode 2 2 I C-bus specification for all I C-bus voltages greater than 3 V, as well as compliance with SMBus or other systems that use TTL switching levels. SX is guaranteed to sink an external 3 mA in addition to its internally sourced pull-up of typically 300 μA (maximum 1 mA at -40 °C). When selecting the pull-up for the bus at SX, the sink capability of other connected drivers should be taken into account. Most TTL devices are specified to sink at least 4 mA so then the pull-up is limited to 3 mA by the requirement to ensure the 0.8 V TTL LOW. 2 2 For Fast-mode I C-bus operation, the other connected I C-bus parts may have the minimum sink capability of 3 mA. SX sources typically 300 μA (maximum 1 mA at -40 °C), which forms part of the external driver loading. When selecting the pull-up it is necessary to subtract the SX pin pull-up current, so, worst-case at -40 °C, the allowed pull-up can be limited (by external drivers) to 2 mA. When the interface at SX is an Fm+ bus with a voltage greater than 4 V, its higher specified sink capability may be used. PCA9600 has a guaranteed sink capability of 7 mA at VOL = 1 V maximum. That 1 V complies with the bus LOW requirement (0.25Vbus) of any Fm+ bus operating at 4 V or greater. Since the other connected Fm+ devices have a drive capability greater than 20 mA, the pull-up may be selected for 7 mA sink current at VOL = 1 V. For a nominal 5 V bus (5.5 V maximum) the allowed pull-up is (5.5 V - 1 V) / 7 mA = 643 Ω. With 680 Ω pull-up, the Fm+ rise time of 120 ns maximum can be met with total bus loading up to 200 pF. The logic level on RX is determined from the power supply voltage VCC of the chip. Logic LOW is below 40 % of VCC, and logic HIGH is above 55 % of VCC (with a typical switching threshold just slightly below half VCC). TX is an open-collector output without ESD protection diodes to VCC. It may be connected via a pull-up resistor to a supply voltage in excess of VCC, as long as the 15 V 2 rating is not exceeded. It has a larger current sinking capability than a normal I C-bus device, being able to sink a static current of greater than 30 mA, and typical 100 mA dynamic pull-down capability as well. 2 A logic LOW is transmitted to TX when the voltage at I C-bus pin SX is below 0.425 V. 2 A logic LOW at RX will cause I C-bus pin SX to be pulled to a logic LOW level in 2 accordance with I C-bus requirements (maximum 1.5 V in 5 V applications) but not low enough to be looped back to the TX output and cause the buffer to latch LOW. 2 The LOW level this chip can achieve on the I C-bus by a LOW at RX is typically 0.64 V when sinking 1 mA. 2 If the supply voltage VCC fails, then neither the I C-bus nor the TX output will be held LOW. Their open-collector configuration allows them to be pulled up to the rated maximum of 15 V even without VCC present. The input configuration on SX and RX also presents no loading of external signals when VCC is not present. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 4 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer The effective input capacitance of any signal pin, measured by its effect on bus rise times, is less than 10 pF for all bus voltages and supply voltages including VCC = 0 V. Remark: Two or more SX or SY I/Os must not be interconnected. The PCA9600 design 2 does not support this configuration. Bidirectional I C-bus signals do not allow any direction control pin so, instead, slightly different logic LOW voltage levels are used at 2 SX/SY to avoid latching of this buffer. A ‘regular I C-bus LOW’ applied at the RX/RY of a PCA9600 will be propagated to SX/SY as a ‘buffered LOW’ with a slightly higher voltage level. If this special ‘buffered LOW’ is applied to the SX/SY of another PCA9600, that 2 second PCA9600 will not recognize it as a ‘regular I C-bus LOW’ and will not propagate it to its TX/TY output. The SX/SY side of PCA9600 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example P82B96, PCA9511A, PCA9515A, ‘B’ side of PCA9517, etc. The SX/SY side is only intended for, 2 2 and compatible with, the normal I C-bus logic voltage levels of I C-bus master and slave chips, or even TX/RX signals of a second PCA9600 or P82B96 if required. The TX/RX 2 2 and TY/RY I/O pins use the standard I C-bus logic voltage levels of all I C-bus parts. There are no restrictions on the interconnection of the TX/RX and TY/RY I/O pins to other PCA9600s, for example in a star or multipoint configuration with the TX/RX and TY/RY I/O pins on the common bus and the SX/SY side connected to the line card slave 2 devices. For more details see Application Note AN10658, "Sending I C-bus signals via long communication cables". The PCA9600 is a direct upgrade of the P82B96 with the significant differences summarized in Table 4. Table 4. PCA9600 versus P82B96 Detail PCA9600 P82B96 Supply voltage (VCC) range: 2.5 V to 15 V 2 V to 15 V Maximum operating bus voltage (independent of VCC): 15 V 15 V 5 mA 1 mA 0.5 V over -40 °C to +85 °C 0.65 V at 25 °C Typical operating supply current: 2 Typical LOW-level input voltage on I C-bus (SX/SY side): 2 LOW-level output voltage on I C-bus (SX/SY 0.74 V (max.) over -40 °C to +85 °C side; 3 mA sink): 2 LOW-level output voltage on Fm+ I C-bus (SX/SY side; 7 mA sink): 1 V (max.) Temperature coefficient of VIL / VOL: 0 mV/°C 0.88 V (typ.) at 25 °C n/a -2 mV/°C 2 2 Logic voltage levels on SX/SY bus (independent of VCC): compatible with I C-bus and similar compatible with I C-bus and similar buses using TTL levels (SMBus, etc.) buses using TTL levels (SMBus, etc.) Typical propagation delays: < 100 ns 2 TX/RX switching specifications (I C-bus compliant): < 200 ns yes, all classes including 1 MHz Fm+ yes, all classes including Fm+ 2 RX logic levels with tighter control than I Cbus limit of 30 % to 70 %: yes, 40 % to 55 % (48 % nominal) yes, 42 % to 58 % (50 % nominal) Maximum bus speed: > 1 MHz > 400 kHz ESD rating HBM per JESD22-A114: > 3500 V > 3500 V Package: SO8, TSSOP8 (MSOP8) SO8, TSSOP8 (MSOP8) PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 5 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 2 When the device driving the PCA9600 is an I C-bus compatible device, then the PCA9600 is an improvement on the P82B96 as shown in Table 4. There will always be 2 exceptions however, and if the device driving the bus buffer is not I C-bus compatible (e.g., you need to use the micro already in the system and bit-bang using two GPIO pins) then here are some considerations that would point to using the P82B96 instead: • When the pull-up must be the weakest one possible. The spec is 200 μA for P82B96, but it typically works even below that. And if designing for a temperature range -40 °C up to +60 °C, then the driver when sinking 200 μA only needs to drive a guaranteed low of 0.55 V. For the PCA9600, over that same temperature range and when sinking 1.3 mA (at -40 °C), the device driving the bus buffer must provide the required low of 0.425 V. • When the lower operating temperature range is restricted (say 0 °C). The P82B96 larger SX voltage levels then make a better typical match with the driver, even when the supply is as low as 3.3 V. 2 For an I C-bus compliant driver on 3.3 V the P82B96 is required to guarantee a bus low that is below 0.83 V. P82B96 guarantees that with a 200 μA pull-up. 2 • When the operating temperature range is restricted at both limits. An I C driver's typical output is well below 0.4 V and the P82B96 typically requires 0.6 V input even at +60 °C, so there is a reasonable margin. The PCA9600 requires a typical input low of 0.5 V so its typical margin is smaller. At 0 °C the driver requires a typical input low of 1.16 V and P82B96 provides 0.75 V, so again the typical margin is already quite big and even though PCA9600 is better, providing 0.7 V, that difference is not big. 8 Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages with respect to pin GND. Symbol Parameter Conditions VCC supply voltage VCC to GND Product data sheet 2 Max Unit -0.3 +18 V -0.3 +18 V VI2C-bus I C-bus voltage SX and SY; I C-bus SDA or SCL VO output voltage TX and TY; buffered output [1] -0.3 +18 V VI input voltage RX and RY; receive input [1] -0.3 +18 V II2C-bus I C-bus current - 250 mA Ptot total power dissipation - 300 mW Tj junction temperature -40 +125 °C Tstg storage temperature -55 +125 °C Tamb ambient temperature -40 +85 °C [1] PCA9600 2 Min 2 2 SX and SY; I C-bus SDA or SCL operating range operating See also Section 10.2. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 6 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 9 Characteristics Table 6. Characteristics Tamb = -40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit Power supply VCC supply voltage operating 2.5 - 15 V ICC supply current VCC = 5 V; buses HIGH - 5.2 6.75 mA VCC = 15 V; buses HIGH - 5.5 7.3 mA per TX/TY output driven LOW; VCC = 5.5 V - 1.4 3.0 mA - - 15 V - - 15 V 0.3 - 2 mA ΔICC additional supply current Bus pull-up (load) voltages and currents 2 Pins SX and SY; I C-bus VI input voltage open-collector; RX and RY HIGH VO output voltage open-collector; RX and RY HIGH [1] IO output current static; VSX = VSY = 0.4 V IO(sink) output sink current dynamic; VSX = VSY = 1 V; RX and RY LOW 7 15 - mA IL leakage current VSX = VSY = 15 V; RX and RY HIGH - - 10 μA Pins TX and TY VO output voltage open-collector - - 15 V Iload load current maximum recommended on buffered bus; VTX = VTY = 0.4 V; 2 SX and SY LOW on I C-bus = 0.4 V - - 30 mA IO output current from buffered bus; VTX = VTY = 2 1 V; SX and SY LOW on I C-bus = 0.4 V 60 130 - mA IL leakage current on buffered bus; VTX = VTY = VCC = 15 V; SX and SY HIGH - - 10 μA Input currents II IL input current leakage current 2 from I C-bus on SX and SY RX and RY HIGH or LOW; SX and SY LOW ≤ 1 V [1] - -0.3 -1 mA RX and RY HIGH; SX and SY HIGH > 1.4 V [1] - - 10 μA from buffered bus on RX and RY; SX and SY HIGH or LOW; VRX = VRY = 0.4 V [2] - -1.5 -10 μA - - 10 μA on buffered bus input on RX and RY; VRX = VRY = 15 V Output logic LOW level PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 7 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer Table 6. Characteristics...continued Tamb = -40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit ISX = ISY = 3 mA; Figure 6 - 0.7 0.74 V ISX = ISY = 0.3 mA; Figure 5 - 0.6 0.65 V - - 1 V - 0 - %/K - - 425 mV Pins SX and SY VOL on Standard-mode or Fast-mode 2 I C-bus LOW-level output voltage 2 on 5 V Fm+ I C-bus ISX = ISY = 7 mA ΔV/ΔT voltage variation with temperature ISX = ISY = 0.3 mA to 3 mA Input logic switching threshold voltages Pins SX and SY VIL 2 LOW-level input voltage on normal I C-bus; Figure 7 [3] 2 Vth(IH) HIGH-level input threshold voltage on normal I C-bus; Figure 8 580 - - mV ΔV/ΔT voltage variation with temperature - 0 - %/K Pins RX and RY VIH HIGH-level input voltage fraction of applied VCC 0.55VCC - - V Vth(i) input threshold voltage fraction of applied VCC - 0.48VCC - V VIL LOW-level input voltage fraction of applied VCC - - 0.4VCC V 50 - - mV - 127 - K/W - - 1 V - -4 - %/K Logic level threshold difference ΔV voltage difference SX and SY; SX output LOW at 0.3 mA to SX input HIGH maximum [4] Thermal resistance Rth(j-pcb) thermal resistance from junction to SOT96-1 (SO8); average lead printed-circuit board temperature at board interface Bus release on VCC failure VCC supply voltage ΔV/ΔT voltage variation with temperature Figure 9 Buffer response time SX, SY, TX and TY; voltage at which all buses are to be released at 25 °C [5] VCC = 5 V; pin TX pull-up resistor = 160 Ω; pin SX pull-up resistor = 2.2 kΩ; no capacitive load td delay time PCA9600 Product data sheet VSX to VTX, VSY to VTY; on falling input between VSX = input switching threshold, and VTX output falling to 50 % VCC - 50 - ns VSX to VTX, VSY to VTY; on rising input between VSX = input switching threshold, and VTX output reaching 50 % VCC - 60 - ns All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 8 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer Table 6. Characteristics...continued Tamb = -40 °C to +85 °C unless otherwise specified; voltages are specified with respect to GND with VCC = 2.5 V to 15 V unless otherwise specified. Typical values are measured at VCC = 5 V and Tamb = 25 °C. Symbol Parameter Conditions Min Typ Max Unit VRX to VSX, VRY to VSY; on falling input between VRX = input switching threshold, and VSX output falling to 50 % VCC - 100 - ns VRX to VSX, VRY to VSY; on rising input between VRX = input switching threshold, and VSX output reaching 50 % VCC - 95 - ns effective input capacitance of any signal pin measured by incremental bus rise times; guaranteed by design, not production tested - - 10 pF Input capacitance Ci [1] [2] [3] [4] [5] input capacitance This bus pull-up current specification is intended to assist design of the bus pull-up resistor. It is not a specification of the sink capability (see VOL under 2 sub-section "Output logic LOW level"). The maximum static sink current for a Standard/Fast-mode I C-bus is 3 mA and PCA9600 is guaranteed to sink 3 mA at SX/SY when its pins are holding the bus LOW. However, when an external device pulls the SX/SY pins below 1.4 V, the PCA9600 may source a current between 0 mA and 1 mA maximum. When that other external device is driving LOW it will pull the bus connected to SX or SY down to, or below, 2 the 0.4 V level referenced in the I C-bus specification and in these test conditions. Then that device must be able to sink up to 1 mA coming from SX/SY plus the usual pull-up current. Therefore the external pull-up used at SX/SY should be limited to 2 mA. The typical and maximum currents sourced by SX/ SY as a function of junction temperature are shown in Figure 10, and the equivalent circuit at the SX/SY interface is shown in Figure 4. Valid over temperature for VCC ≤ 5 V. At higher VCC, this current may increase to maximum -20 μA at VCC = 15 V. The input logic threshold is independent of the supply voltage. The minimum value requirement for pull-up current, 0.3 mA, guarantees that the minimum value for VSX output LOW will always exceed the maximum VSX input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC. While the tolerances on absolute levels allow a small probability, the LOW from one SX output is recognized by an SX input of another PCA9600, this has no consequences for normal applications. In any design the SX pins of different ICs should never be linked because the resulting system would be very susceptible to induced noise 2 and would not support all I C-bus operating modes. The fall time of VTX from 5 V to 2.5 V in the test is approximately 10 ns. The fall time of VSX from 5 V to 2.5 V in the test is approximately 20 ns. The rise time of VTX from 0 V to 2.5 V in the test is approximately 15 ns. The rise time of VSX from 0.7 V to 2.5 V in the test is approximately 25 ns. VCC ≤ 1 mA SX (SY) Vref 002aac838 Figure 4. Equivalent circuit at SX/SY PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 9 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 002aac839 800 VOL (mV) 700 (1) (2) 600 500 400 - 50 - 25 0 25 50 75 100 125 Tj (°C) VOL at SX typical and limits over temperature. 1. Maximum. 2. Typical. Figure 5. VOL as a function of junction temperature (IOL = 0.3 mA) 800 VOL (mV) 700 002aac840 (1) (2) 600 500 400 - 50 - 25 0 25 50 75 100 125 Tj (°C) VOL at SX typical and limits over temperature. 1. Maximum. 2. Typical. Figure 6. VOL as a function of junction temperature (IOL = 3 mA) 600 VIL (mV) 500 002aag005 typical maximum 400 300 200 - 50 - 25 0 25 50 75 100 125 Tj (°C) VIL at SX changes over temperature range. Figure 7. VIL as a function of junction temperature; maximum and typical values PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 10 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 002aag006 600 VIH (mV) minimum 500 typical 400 300 200 - 50 - 25 0 25 50 75 100 125 Tj (°C) VIH at SX changes over temperature range. Figure 8. VIH as a function of junction temperature; minimum and typical values 002aac075 1400 VCC(max) (mV) 1200 1000 800 600 400 - 50 - 25 0 25 50 75 100 125 Tj (°C) 1. Maximum. 2. Typical. Figure 9. VCC bus release limit over temperature; maximum values 1000 II (µA) 800 001aai062 (1) (2) 600 400 200 0 - 50 - 25 0 25 50 75 100 125 Tj (°C) Figure 10. Current sourced out of SX/SY as a function of junction temperature if these pins are externally pulled to 0.4 V or lower 10 Application information Refer to PCA9600 data sheet and application notes AN10658 and AN255 for more detailed application information. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 11 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer VCC (2.5 V to 15 V) 5V TX (SDA) I2C-bus SDA RX (SDA) R1 'SDA' (new levels) PCA9600 001aai063 2 Figure 11. Interfacing a standard 3 mA I C-bus or one with TTL levels (e.g. SMBus) to higher voltage or higher current sink (e.g. Fast-mode Plus) devices VCC R2 VCC1 R4 R5 RX (SDA) 5V R1 I2C-bus SDA I2C-bus SDA R3 TX (SDA) PCA9600 001aai064 This simple example may be limited, if using lowest-cost couplers, to speeds as low as 5 kHz. Refer to application notes for schematics suitable for operation to 400 kHz or higher. 2 Figure 12. Galvanic isolation of I C-bus nodes via opto-couplers main enclosure 3.3 V to 5 V remote control enclosure 12 V 12 V 3.3 V to 5 V long cables SDA SDA 3.3 V to 5 V 12 V 3.3 V to 5 V SCL SCL PCA9600 PCA9600 002aac846 2 Figure 13. Long distance I C-bus communication PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 12 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer +V cable drive VCC1 R2 SCL VCC VCC R2 RX SX I2C-BUS MASTER SDA VCC2 SY RX R2 TX TX SX TY TY R1 R1 RY R1 R1 SY SDA C2 C2 PCA9600 propagation delay ≈ 5 ns/m C2 GND SCL I2C-BUS SLAVE(S) RY cable PCA9600 C2 R2 BAT54A GND BAT54A 002aac851 Figure 14. Driving ribbon or flat telephone cables Table 7. Examples of bus capability Refer to Figure 14. VCC1 (V) +V VCC2 cable (V) (V) R1 (Ω) R2 C2 (kΩ) (pF) Cable Cable length capacitance (m) Cable delay Set master nominal SCL Effective bus clock HIGH LOW speed period period (kHz) (ns) (ns) Max. slave response delay 5 12 5 750 2.2 400 250 n/a (delay based) 1.25 μs 600 3 850 125 normal specification 400 kHz parts 5 12 5 750 2.2 220 100 n/a (delay based) 500 ns 600 2 450 195 normal specification 400 kHz parts 3.3 5 3.3 330 1 220 25 1 nF 125 ns 260 770 620 meets Fm+ specification 3.3 5 3.3 330 1 100 3 120 pF 15 ns 260 720 690 meets Fm+ specification For more examples of faster alternatives for driving over longer cables such as Cat5 communication cable, see AN10658. Communication at 1 MHz is possible over short cables and > 400 kHz is possible over 50 m of cable. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 13 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 10.1 Calculating system delays and bus clock frequency local master bus buffered expansion bus VCCM remote slave bus VCCB Rm SCL MASTER VCCS Rb SX PCA9600 TX/RX TX/RX Rs PCA9600 SCL SLAVE SX I2C-BUS I2C-BUS Cm Cb master bus capacitance Cs buffered bus wiring capacitance slave bus capacitance GND (0 V) 002aac847 9 Effective delay of SCL at slave: 120 + 17VCCM + (2.5 + 4 × 10 × Cb) × VCCB + 10VCCS (ns). C = F; V = V. Figure 15. Falling edge of SCL at master is delayed by the buffers and bus fall times local master bus buffered expansion bus VCCM VCCB SCL MASTER Rm Rb SX PCA9600 TX/RX TX/RX I2C-BUS Cm master bus capacitance Cb buffered bus wiring capacitance GND (0 V) 002aac848 Effective delay of SCL at master: 115 + (Rm × Cm) + (0.7 × Rb × Cb) (ns). C = F; R = Ω. Figure 16. Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 14 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer local master bus buffered expansion bus VCCM remote slave bus VCCB SDA MASTER VCCS Rm Rb SX PCA9600 TX/RX TX/RX Rs PCA9600 SDA SLAVE SX I2C-BUS I2C-BUS Cm Cb master bus capacitance buffered bus wiring capacitance Cs slave bus capacitance GND (0 V) 001aai158 Effective delay of SDA at master: 115 + 0.2(Rs × Cs) + 0.7[(Rb × Cb) + (Rm × Cm)] (ns). C = F; R = Ω. Figure 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times Figure 15, Figure 16, and Figure 17 show the PCA9600 used to drive extended bus 2 wiring with relatively large capacitances linking two I C-bus nodes. It includes simplified expressions for making the relevant timing calculations for 3.3 V or 5 V operation. Because the buffers and the wiring introduce timing delays, it may be necessary to decrease the nominal SCL frequency. In most cases the actual bus frequency will be lower than the nominal Master timing due to bit-wise stretching of the clock periods. The delay factors involved in calculation of the allowed bus speed are: A: The propagation delay of the master signal through the buffers and wiring to the slave. The important delay is that of the falling edge of SCL because this edge ‘requests’ the data or acknowledge from a slave. See Figure 15. B: The effective stretching of the nominal LOW period of SCL at the master caused by the buffer and bus rise times. See Figure 16. C: The propagation delay of the slave's response signal through the buffers and wiring back to the master. The important delay is that of a rising edge in the SDA signal. Rising edges are always slower and are therefore delayed by a longer time than falling edges. (The rising edges are limited by the passive pull-up while falling edges are actively driven); see Figure 17. 2 The timing requirement in any I C-bus system is that a slave's data response (which is provided in response to a falling edge of SCL) must be received at the master before the end of the corresponding LOW period of SCL as appears on the bus wiring at the master. Since all slaves will, as a minimum, satisfy the worst case timing requirements of their speed class (Fast-mode, Fm+, etc.), they must provide their response, allowing for the set-up time, within the minimum allowed clock LOW period, e.g., 450 ns (max.) for Fm + parts. In systems that introduce additional delays it may be necessary to extend the minimum clock LOW period to accommodate the ‘effective’ delay of the slave's response. The effective delay of the slave’s response equals the total delays in SCL falling edge from the master reaching the slave (Figure 15) minus the effective delay (stretch) of the SCL rising edge (Figure 16) plus total delays in the slave's response data, carried on SDA, reaching the master (Figure 17). The master microcontroller should be programmed to produce a nominal SCL LOW period as follows: PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 15 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer (1) The actual LOW period will become (the programmed value + the stretching time B). When this actual LOW period is then less than the specified minimum, the specified minimum should be used. Example 1: It is required to connect an Fm+ slave, with Rs × Cs product of 100 ns, to a 5 V Fastmode system also having 100 ns Rm × Cm using two PCA9600’s to buffer a 5 V bus with 4 nF loading and 160 Ω pull-up. Calculate the allowed bus speed: Delay A = 120 + 85 + (2.5 + [4 × 4]) × 5 + 50 = 347.5 ns Delay B = 115 + 100 + 70 = 285 ns Delay C = 115 + 20 + 0.7(100 + 100) = 275 ns The maximum Fm+ slave response delay must be < 450 ns so the programmed LOW period is calculated as: LOW ≥ 450 + 347.5 - 285 + 275 + 100 = 887.5 ns The actual LOW period will be 887.5 + 285 = 1 173 ns, which is below the Fast-mode minimum, so the programmed LOW period must be increased to (1300 - 285) = 1015 ns, so the actual LOW equals the 1300 ns requirement and this shows that this Fastmode system may be safely run to its limit of 400 kHz. Example 2: It is required to buffer a Master with Fm+ speed capability, but only 3 mA sink capability, to an Fm+ bus. All the system operates at 3.3 V. The Master Rm × Cm product is 50 ns. Only one PCA9600 is used. The Fm+ bus becomes the buffered bus. The Fm+ bus has 200 pF loading and 150 Ω pull-up, so its Rb × Cb product is 30 ns. The Fm+ slave has a specified data valid time tVD;DAT maximum of 300 ns. Calculate the allowed maximum system bus speed. (Note that the fixed values in the delay equations represent the internal propagation delays of the PCA9600. Only one PCA9600 is used here, so those fixed values used below are taken from the characteristics.) The delays are: Delay A = 40 + 56 + (2.5 + [4 × 0.2]) × 3.3 = 107 ns Delay B = 115 + 50 + 21 = 186 ns Delay C = 70 + 0.7(50 + 30) = 126 ns The programmed LOW period is calculated as: SCL LOW ≥ 300 + 117 - 186 + 126 + 50 = 407 ns The actual LOW period will be 407 + 126 = 533 ns, which exceeds the minimum Fm + 500 ns requirement. This system requires the bus LOW period, and therefore cycle time, to be increased by 33 ns so the system must run slightly below the 1 MHz limit. The possible maximum speed has a cycle period of 1 033 ns or 968 kHz. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 16 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 12 V 12 V twisted-pair telephone wires, USB, or flat ribbon cables; up to 15 V logic levels, include VCC and GND 3.3 V to 5 V SX SDA TX RX 3.3 V to 5 V 12 V SY SCL TY 3.3 V 3.3 V RY PCA9600 PCA9600 PCA9600 PCA9600 SX SX SX SY SCL/SDA SY SCL/SDA PCA9600 SY SY SDA SX SCL SCL/SDA no limit to the number of connected bus devices 001aai065 2 Figure 18. I C-bus multipoint application 2 There is an Excel calculator which makes it easy to determine the maximum I C-bus clock speed when using the PCA9600. The calculator and instructions can be found at www.nxp.com/clockspeedcalculator. 002aac932 7 VCC 6 (V) (1) 5 4 3 (2) 2 1 (1) 0 -1 (2) 0 100 200 300 400 500 600 700 800 900 time (ns) 1. TX output. 2. SX input. Figure 19. Propagation SX to TX with VRX = VCC = 3.3 V (SX pull-up to 3.3 V; TX pull-up to 5.7 V) PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 17 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 002aac933 7 VCC 6 (V) (1) 5 4 3 (2) 2 1 (2) (1) 0 -1 (2) 0 100 200 300 400 500 600 700 800 900 time (ns) 1. TX/RX output. 2. SX input. Figure 20. Propagation SX to TX with RX tied to TX; VCC = 3.3 V (SX pull-up to 3.3 V; TX pull-up to 5.7 V) 002aac934 7 VCC 6 (V) 5 4 (1) 3 (2) 2 (2) 1 0 -1 (1) 0 100 200 300 400 500 600 700 800 900 time (ns) 1. RX input. 2. SX output. Figure 21. Propagation RX to SX (SX pull-up to 3.3 V; VCC = 3.3 V; RX pull-up to 4.6 V) 10.2 Negative undershoot below absolute minimum value The reason why the IC pin reverse voltage on pins TX and RX in Table 5 is specified at such a low value, -0.3 V, is not that applying larger voltages is likely to cause damage but that it is expected that, in normal applications, there is no reason why larger DC voltages will be applied. This ‘absolute maximum’ specification is intended to be a DC 2 or continuous ratings and the nominal DC I C-bus voltage LOW usually does not even reach 0 V. Inside PCA9600 at every pin there is a large protective diode connected to the GND pin and that diode will start to conduct when the pin voltage is more than about -0.55 V with respect to GND at 25 °C ambient. Figure 22 shows the measured characteristic for one of those diodes inside PCA9600. The plot was made using a curve tracer that applies 50 Hz mains voltage via a series resistor, so the pulse durations are long duration (several milliseconds) and are reaching peaks of over 2 A when more than -1.5 V is applied. The IC becomes very hot during this testing but it was not damaged. Whenever there is current flowing in any of these diodes PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 18 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer it is possible that there can be faulty operation of any IC. For that reason we put a specification on the negative voltage that is allowed to be applied. It is selected so that, at the highest allowed junction temperature, there will be a big safety factor that guarantees the diode will not conduct and then we do not need to make any 100 % production tests to guarantee the published specification. For the PCA9600, in specific applications, there will always be transient overshoot and ringing on the wiring that can cause these diodes to conduct. Therefore we designed the IC to withstand those transients and as a part of the qualification procedure we made tests, using DC currents to more than twice the normal bus sink currents, to be sure that the IC was not affected by those currents. For example, the TX/TY and RX/RY pins were tested to at least -80 mA which, from Figure 22, would be more than -0.8 V. The correct functioning of the PCA9600 is not affected even by those large currents. The Absolute Maximum (DC) ratings are not intended to apply to transients but to steady state conditions. This explains why you will never see any problems in practice even if, during transients, more than -0.3 V is applied to the bus interface pins of PCA9600. Figure 22 also explains how the general Absolute Maximum DC specification was selected. The current at 25 °C is near zero at -0.55 V. The PCA9600 is allowed to operate with +125 °C junction and that would cause this diode voltage to decrease by 100 × 2 mV = 200 mV. So for zero current we need to specify -0.35 V and we publish -0.3 V just to have some extra margin. Remark: You should not be concerned about the transients generated on the wiring by a PCA9600 in normal applications and that is input to the TX/RX or TY/RY pins of another PCA9600. Because not all ICs that may be driven by PCA9600 are designed to tolerate negative transients, in Section 10.2.1 we show they can be managed if required. 002aaf063 0 diode current (mA) - 10- 1 -1 - 10 - 102 - 103 - 104 - 2.0 - 1.5 - 1.0 - 0.5 0 voltage (V) Figure 22. Diode characteristic curve 10.2.1 Example with questions and answers Question: On a falling edge of TX we measure undershoot at -800 mV at the linked TX, RX pins of the PCA9600 that is generating the LOW, but the PCA9600 data sheet specifies minimum -0.3 V. Does this mean that we violate the data sheet absolute value? Answer: For PCA9600 the -0.3 V Absolute Maximum rating is not intended to apply to transients, it is a DC rating. As shown in Figure 23, there is no theoretical reason for any undershoot at the IC that is driving the bus LOW and no significant undershoot PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 19 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer should be observed when using reasonable care with the ground connection of the ‘scope. It is more likely that undershoot observed at a driving PCA9600 is caused by local stray inductance and capacitance in the circuit and by the oscilloscope connections. As shown, undershoot will be generated by PCB traces, wiring, or 2 cables driven by a PCA9600 because the allowed value of the I C-bus pull-up resistor generally is larger than that required to correctly terminate the wiring. In this example, with no IC connected at the end of the wiring, the undershoot is about 2 V. 6 voltage (V) 4 send 2 receive 0 -2 horizontal scale = 62.5 ns/div 5V 5V 5V 300 Ω RX SX TX send PCA9600 time (ns) 2 meter cable 300 Ω receive GND 002aaf081 Figure 23. Transients generated by the bus wiring Question: We have 2 meters of cable in a bus that joins the TX/RX sides of two PCA9600 devices. When one TX drives LOW the other PCA9600 TX/RX is driven to -0.8 V for over 50 ns. What is the expected value and the theoretically allowed value of undershoot? Answer: Because the cable joining the two PCA9600s is a ‘transmission line’ that will have a characteristic impedance around 100 Ω and it will be terminated by pullup resistors that are larger than that characteristic impedance there will always be negative undershoot generated. The duration of the undershoot is a function of the cable length and the input impedance of the connected IC. As shown in Figure 24, the transient undershoot will be limited, by the diodes inside PCA9600, to around -0.8 V and that will not cause problems for PCA9600. Those transients will not be passed inside the IC to the SX/SY side of the IC. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 20 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 6 voltage (V) 4 2 receive send 0 -2 horizontal scale = 62.5 ns/div 5V 5V time (ns) 5V 300 Ω SX RX TX send PCA9600 2 meter cable 5V 300 Ω receive RX SX TX GND 002aaf082 Figure 24. Wiring transients limited by the diodes in PCA9600 Question: If we input 800 mV undershoot at TX, RX pins, what kind of problem is expected? Answer: When that undershoot is generated by another PCA9600 and is simply the result of the system wiring, then there will be no problems. Question: Will we have any functional problem or reliability problem? Answer: No. Question: If we add 100 Ω to 200 Ω at signal line, the overshoot becomes slightly smaller. Is this a good idea? Answer: No, it is not necessary to add any resistance. When the logic signal generated by TX or TY of PCA9600 drives long traces or wiring with ICs other than PCA9600 being driven, then adding a Schottky diode (BAT54A) as shown in Figure 25 will clamp the wiring undershoot to a value that will not cause conduction of the IC’s internal diodes. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 21 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 6 voltage (V) 4 2 send 0 receive -2 horizontal scale = 62.5 ns/div 5V 5V 5V 300 Ω RX SX TX send PCA9600 time (ns) 2 meter cable 5V 300 Ω receive 1/ BAT54A 2 RX SX TX GND 002aaf083 Figure 25. Wiring transients limited by a Schottky diode PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 22 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 11 Package outline SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1 D E A X c y HE v M A Z 5 8 A2 Q A (A 3) A1 pin 1 index θ Lp 1 L 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 5.0 4.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.20 0.014 0.0075 0.19 0.16 0.15 inches 0.010 0.057 0.069 0.004 0.049 0.05 0.244 0.039 0.028 0.041 0.228 0.016 0.024 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT96-1 076E03 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Figure 26. Package outline SOT96-1 (SO8) PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 23 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm D E SOT505-1 A X c y HE v M A Z 5 8 A2 pin 1 index (A3) A1 A θ Lp L 1 4 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D(1) E(2) e HE L Lp v w y Z(1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.45 0.25 0.28 0.15 3.1 2.9 3.1 2.9 0.65 5.1 4.7 0.94 0.7 0.4 0.1 0.1 0.1 0.70 0.35 6° 0° Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18 SOT505-1 Figure 27. Package outline SOT505-1 (TSSOP8) PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 24 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 12 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 12.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 12.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 12.4 Reflow soldering Key characteristics in reflow soldering are: PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 25 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 8 and Table 9 Table 8. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 9. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28. PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 26 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. 13 Abbreviations Table 10. Abbreviations Acronym Description CDM Charged-Device Model ESD ElectroStatic Discharge HBM Human Body Model 2 I C-bus Inter-Integrated Circuit bus I/O Input/Output IC Integrated Circuit PMBus Power Management Bus SMBus System Management Bus TTL Transistor-Transistor Logic 14 Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9600 v.6.1 20211219 Product data sheet - PCA9600 v.6 Modifications: • Added orderable part number PCA9600DPZ PCA9600 v.6 20150925 Product data sheet - PCA9600 v.5 PCA9600 v.5 20110505 Product data sheet - PCA9600 v.4 PCA9600 v.4 20091111 Product data sheet - PCA9600 v.3 PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 27 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer Table 11. Revision history...continued Document ID Release date Data sheet status Change notice Supersedes PCA9600 v.3 20090903 Product data sheet - PCA9600 v.2 PCA9600 v.2 20080813 Product data sheet - PCA9600 v.1 PCA9600 v.1 20080602 Product data sheet - - PCA9600 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 28 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer 15 Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCA9600 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 29 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. PCA9600 Product data sheet Security — Customer understands that all NXP products may be subject to unidentified vulnerabilities or may support established security standards or specifications with known limitations. Customer is responsible for the design and operation of its applications and products throughout their lifecycles to reduce the effect of these vulnerabilities on customer’s applications and products. Customer’s responsibility also extends to other open and/or proprietary technologies supported by NXP products for use in customer’s applications. NXP accepts no liability for any vulnerability. Customer should regularly check security updates from NXP and follow up appropriately. Customer shall select products with security features that best meet rules, regulations, and standards of the intended application and make the ultimate design decisions regarding its products and is solely responsible for compliance with all legal, regulatory, and security related requirements concerning its products, regardless of any information or support that may be provided by NXP. NXP has a Product Security Incident Response Team (PSIRT) (reachable at PSIRT@nxp.com) that manages the investigation, reporting, and solution release to security vulnerabilities of NXP products. 15.4 Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 30 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Ordering information ..........................................2 Ordering options ................................................2 Pin description ...................................................3 PCA9600 versus P82B96 ................................. 5 Limiting values .................................................. 6 Characteristics ...................................................7 Tab. 7. Tab. 8. Tab. 9. Tab. 10. Tab. 11. Examples of bus capability ............................. 13 SnPb eutectic process (from J-STD-020D) ..... 26 Lead-free process (from J-STD-020D) ............ 26 Abbreviations ...................................................27 Revision history ...............................................27 Fig. 15. Falling edge of SCL at master is delayed by the buffers and bus fall times ..................... 14 Rising edge of SCL at master is delayed (clock stretch) by buffer and bus rise times ..... 14 Rising edge of SDA at slave is delayed by the buffers and bus rise times .........................15 I2C-bus multipoint application ......................... 17 Propagation SX to TX with VRX = VCC = 3.3 V (SX pull-up to 3.3 V; TX pull-up to 5.7 V) ............................................................... 17 Propagation SX to TX with RX tied to TX; VCC = 3.3 V (SX pull-up to 3.3 V; TX pull-up to 5.7 V) ...............................................18 Propagation RX to SX (SX pull-up to 3.3 V; VCC = 3.3 V; RX pull-up to 4.6 V) .........18 Diode characteristic curve ...............................19 Transients generated by the bus wiring ...........20 Wiring transients limited by the diodes in PCA9600 ......................................................... 21 Wiring transients limited by a Schottky diode ................................................................22 Package outline SOT96-1 (SO8) .....................23 Package outline SOT505-1 (TSSOP8) ............24 Temperature profiles for large and small components ..................................................... 27 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Fig. 7. Fig. 8. Fig. 9. Fig. 10. Fig. 11. Fig. 12. Fig. 13. Fig. 14. Block diagram of PCA9600 ...............................2 Pin configuration for SO8 ..................................3 Pin configuration for TSSOP8 (MSOP8) ........... 3 Equivalent circuit at SX/SY ............................... 9 VOL as a function of junction temperature (IOL = 0.3 mA) ................................................ 10 VOL as a function of junction temperature (IOL = 3 mA) ...................................................10 VIL as a function of junction temperature; maximum and typical values ........................... 10 VIH as a function of junction temperature; minimum and typical values ............................ 11 VCC bus release limit over temperature; maximum values ............................................. 11 Current sourced out of SX/SY as a function of junction temperature if these pins are externally pulled to 0.4 V or lower ................... 11 Interfacing a standard 3 mA I2C-bus or one with TTL levels (e.g. SMBus) to higher voltage or higher current sink (e.g. Fastmode Plus) devices .........................................12 Galvanic isolation of I2C-bus nodes via opto-couplers ...................................................12 Long distance I2C-bus communication ........... 12 Driving ribbon or flat telephone cables ............ 13 PCA9600 Product data sheet Fig. 16. Fig. 17. Fig. 18. Fig. 19. Fig. 20. Fig. 21. Fig. 22. Fig. 23. Fig. 24. Fig. 25. Fig. 26. Fig. 27. Fig. 28. All information provided in this document is subject to legal disclaimers. Rev. 6.1 — 20 December 2021 © NXP B.V. 2021. All rights reserved. 31 / 32 PCA9600 NXP Semiconductors Dual bidirectional bus buffer Contents 1 2 3 4 4.1 5 6 6.1 6.2 7 8 9 10 10.1 General description ............................................ 1 Features and benefits .........................................1 Applications .........................................................1 Ordering information .......................................... 2 Ordering options ................................................ 2 Block diagram ..................................................... 2 Pinning information ............................................ 3 Pinning ............................................................... 3 Pin description ................................................... 3 Functional description ........................................3 Limiting values .................................................... 6 Characteristics .................................................... 7 Application information .................................... 11 Calculating system delays and bus clock frequency ......................................................... 14 10.2 Negative undershoot below absolute minimum value ................................................ 18 10.2.1 Example with questions and answers ..............19 11 Package outline .................................................23 12 Soldering of SMD packages .............................25 12.1 Introduction to soldering .................................. 25 12.2 Wave and reflow soldering .............................. 25 12.3 Wave soldering ................................................ 25 12.4 Reflow soldering .............................................. 25 13 Abbreviations .................................................... 27 14 Revision history ................................................ 27 15 Legal information .............................................. 29 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 20 December 2021 Document identifier: PCA9600